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path: root/drivers/net/wireless/ath/ath9k/hw.c
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Diffstat (limited to 'drivers/net/wireless/ath/ath9k/hw.c')
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.c1761
1 files changed, 362 insertions, 1399 deletions
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index af730c7d50e6..5a29048db3b1 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2008-2009 Atheros Communications Inc. 2 * Copyright (c) 2008-2010 Atheros Communications Inc.
3 * 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any 4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above 5 * purpose with or without fee is hereby granted, provided that the above
@@ -19,15 +19,15 @@
19#include <asm/unaligned.h> 19#include <asm/unaligned.h>
20 20
21#include "hw.h" 21#include "hw.h"
22#include "hw-ops.h"
22#include "rc.h" 23#include "rc.h"
23#include "initvals.h" 24#include "ar9003_mac.h"
24 25
25#define ATH9K_CLOCK_RATE_CCK 22 26#define ATH9K_CLOCK_RATE_CCK 22
26#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40 27#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
27#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44 28#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
28 29
29static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); 30static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
30static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
31 31
32MODULE_AUTHOR("Atheros Communications"); 32MODULE_AUTHOR("Atheros Communications");
33MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 33MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
@@ -46,6 +46,39 @@ static void __exit ath9k_exit(void)
46} 46}
47module_exit(ath9k_exit); 47module_exit(ath9k_exit);
48 48
49/* Private hardware callbacks */
50
51static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
52{
53 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
54}
55
56static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
57{
58 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
59}
60
61static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
62{
63 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
64
65 return priv_ops->macversion_supported(ah->hw_version.macVersion);
66}
67
68static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
69 struct ath9k_channel *chan)
70{
71 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
72}
73
74static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
75{
76 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
77 return;
78
79 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
80}
81
49/********************/ 82/********************/
50/* Helper Functions */ 83/* Helper Functions */
51/********************/ 84/********************/
@@ -233,21 +266,6 @@ static void ath9k_hw_read_revisions(struct ath_hw *ah)
233 } 266 }
234} 267}
235 268
236static int ath9k_hw_get_radiorev(struct ath_hw *ah)
237{
238 u32 val;
239 int i;
240
241 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
242
243 for (i = 0; i < 8; i++)
244 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
245 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
246 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
247
248 return ath9k_hw_reverse_bits(val, 8);
249}
250
251/************************************/ 269/************************************/
252/* HW Attach, Detach, Init Routines */ 270/* HW Attach, Detach, Init Routines */
253/************************************/ 271/************************************/
@@ -257,6 +275,8 @@ static void ath9k_hw_disablepcie(struct ath_hw *ah)
257 if (AR_SREV_9100(ah)) 275 if (AR_SREV_9100(ah))
258 return; 276 return;
259 277
278 ENABLE_REGWRITE_BUFFER(ah);
279
260 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 280 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
261 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 281 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
262 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 282 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
@@ -268,20 +288,30 @@ static void ath9k_hw_disablepcie(struct ath_hw *ah)
268 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 288 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
269 289
270 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 290 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
291
292 REGWRITE_BUFFER_FLUSH(ah);
293 DISABLE_REGWRITE_BUFFER(ah);
271} 294}
272 295
296/* This should work for all families including legacy */
273static bool ath9k_hw_chip_test(struct ath_hw *ah) 297static bool ath9k_hw_chip_test(struct ath_hw *ah)
274{ 298{
275 struct ath_common *common = ath9k_hw_common(ah); 299 struct ath_common *common = ath9k_hw_common(ah);
276 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) }; 300 u32 regAddr[2] = { AR_STA_ID0 };
277 u32 regHold[2]; 301 u32 regHold[2];
278 u32 patternData[4] = { 0x55555555, 302 u32 patternData[4] = { 0x55555555,
279 0xaaaaaaaa, 303 0xaaaaaaaa,
280 0x66666666, 304 0x66666666,
281 0x99999999 }; 305 0x99999999 };
282 int i, j; 306 int i, j, loop_max;
307
308 if (!AR_SREV_9300_20_OR_LATER(ah)) {
309 loop_max = 2;
310 regAddr[1] = AR_PHY_BASE + (8 << 2);
311 } else
312 loop_max = 1;
283 313
284 for (i = 0; i < 2; i++) { 314 for (i = 0; i < loop_max; i++) {
285 u32 addr = regAddr[i]; 315 u32 addr = regAddr[i];
286 u32 wrData, rdData; 316 u32 wrData, rdData;
287 317
@@ -336,7 +366,13 @@ static void ath9k_hw_init_config(struct ath_hw *ah)
336 ah->config.ofdm_trig_high = 500; 366 ah->config.ofdm_trig_high = 500;
337 ah->config.cck_trig_high = 200; 367 ah->config.cck_trig_high = 200;
338 ah->config.cck_trig_low = 100; 368 ah->config.cck_trig_low = 100;
339 ah->config.enable_ani = 1; 369
370 /*
371 * For now ANI is disabled for AR9003, it is still
372 * being tested.
373 */
374 if (!AR_SREV_9300_20_OR_LATER(ah))
375 ah->config.enable_ani = 1;
340 376
341 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 377 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
342 ah->config.spurchans[i][0] = AR_NO_SPUR; 378 ah->config.spurchans[i][0] = AR_NO_SPUR;
@@ -369,7 +405,6 @@ static void ath9k_hw_init_config(struct ath_hw *ah)
369 if (num_possible_cpus() > 1) 405 if (num_possible_cpus() > 1)
370 ah->config.serialize_regmode = SER_REG_MODE_AUTO; 406 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
371} 407}
372EXPORT_SYMBOL(ath9k_hw_init);
373 408
374static void ath9k_hw_init_defaults(struct ath_hw *ah) 409static void ath9k_hw_init_defaults(struct ath_hw *ah)
375{ 410{
@@ -383,8 +418,6 @@ static void ath9k_hw_init_defaults(struct ath_hw *ah)
383 ah->hw_version.subvendorid = 0; 418 ah->hw_version.subvendorid = 0;
384 419
385 ah->ah_flags = 0; 420 ah->ah_flags = 0;
386 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
387 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
388 if (!AR_SREV_9100(ah)) 421 if (!AR_SREV_9100(ah))
389 ah->ah_flags = AH_USE_EEPROM; 422 ah->ah_flags = AH_USE_EEPROM;
390 423
@@ -397,44 +430,17 @@ static void ath9k_hw_init_defaults(struct ath_hw *ah)
397 ah->power_mode = ATH9K_PM_UNDEFINED; 430 ah->power_mode = ATH9K_PM_UNDEFINED;
398} 431}
399 432
400static int ath9k_hw_rf_claim(struct ath_hw *ah)
401{
402 u32 val;
403
404 REG_WRITE(ah, AR_PHY(0), 0x00000007);
405
406 val = ath9k_hw_get_radiorev(ah);
407 switch (val & AR_RADIO_SREV_MAJOR) {
408 case 0:
409 val = AR_RAD5133_SREV_MAJOR;
410 break;
411 case AR_RAD5133_SREV_MAJOR:
412 case AR_RAD5122_SREV_MAJOR:
413 case AR_RAD2133_SREV_MAJOR:
414 case AR_RAD2122_SREV_MAJOR:
415 break;
416 default:
417 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
418 "Radio Chip Rev 0x%02X not supported\n",
419 val & AR_RADIO_SREV_MAJOR);
420 return -EOPNOTSUPP;
421 }
422
423 ah->hw_version.analog5GhzRev = val;
424
425 return 0;
426}
427
428static int ath9k_hw_init_macaddr(struct ath_hw *ah) 433static int ath9k_hw_init_macaddr(struct ath_hw *ah)
429{ 434{
430 struct ath_common *common = ath9k_hw_common(ah); 435 struct ath_common *common = ath9k_hw_common(ah);
431 u32 sum; 436 u32 sum;
432 int i; 437 int i;
433 u16 eeval; 438 u16 eeval;
439 u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
434 440
435 sum = 0; 441 sum = 0;
436 for (i = 0; i < 3; i++) { 442 for (i = 0; i < 3; i++) {
437 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i)); 443 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
438 sum += eeval; 444 sum += eeval;
439 common->macaddr[2 * i] = eeval >> 8; 445 common->macaddr[2 * i] = eeval >> 8;
440 common->macaddr[2 * i + 1] = eeval & 0xff; 446 common->macaddr[2 * i + 1] = eeval & 0xff;
@@ -445,54 +451,6 @@ static int ath9k_hw_init_macaddr(struct ath_hw *ah)
445 return 0; 451 return 0;
446} 452}
447 453
448static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
449{
450 u32 rxgain_type;
451
452 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
453 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
454
455 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
456 INIT_INI_ARRAY(&ah->iniModesRxGain,
457 ar9280Modes_backoff_13db_rxgain_9280_2,
458 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
459 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
460 INIT_INI_ARRAY(&ah->iniModesRxGain,
461 ar9280Modes_backoff_23db_rxgain_9280_2,
462 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
463 else
464 INIT_INI_ARRAY(&ah->iniModesRxGain,
465 ar9280Modes_original_rxgain_9280_2,
466 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
467 } else {
468 INIT_INI_ARRAY(&ah->iniModesRxGain,
469 ar9280Modes_original_rxgain_9280_2,
470 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
471 }
472}
473
474static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
475{
476 u32 txgain_type;
477
478 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
479 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
480
481 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
482 INIT_INI_ARRAY(&ah->iniModesTxGain,
483 ar9280Modes_high_power_tx_gain_9280_2,
484 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
485 else
486 INIT_INI_ARRAY(&ah->iniModesTxGain,
487 ar9280Modes_original_tx_gain_9280_2,
488 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
489 } else {
490 INIT_INI_ARRAY(&ah->iniModesTxGain,
491 ar9280Modes_original_tx_gain_9280_2,
492 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
493 }
494}
495
496static int ath9k_hw_post_init(struct ath_hw *ah) 454static int ath9k_hw_post_init(struct ath_hw *ah)
497{ 455{
498 int ecode; 456 int ecode;
@@ -502,9 +460,11 @@ static int ath9k_hw_post_init(struct ath_hw *ah)
502 return -ENODEV; 460 return -ENODEV;
503 } 461 }
504 462
505 ecode = ath9k_hw_rf_claim(ah); 463 if (!AR_SREV_9300_20_OR_LATER(ah)) {
506 if (ecode != 0) 464 ecode = ar9002_hw_rf_claim(ah);
507 return ecode; 465 if (ecode != 0)
466 return ecode;
467 }
508 468
509 ecode = ath9k_hw_eeprom_init(ah); 469 ecode = ath9k_hw_eeprom_init(ah);
510 if (ecode != 0) 470 if (ecode != 0)
@@ -515,14 +475,12 @@ static int ath9k_hw_post_init(struct ath_hw *ah)
515 ah->eep_ops->get_eeprom_ver(ah), 475 ah->eep_ops->get_eeprom_ver(ah),
516 ah->eep_ops->get_eeprom_rev(ah)); 476 ah->eep_ops->get_eeprom_rev(ah));
517 477
518 if (!AR_SREV_9280_10_OR_LATER(ah)) { 478 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
519 ecode = ath9k_hw_rf_alloc_ext_banks(ah); 479 if (ecode) {
520 if (ecode) { 480 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
521 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 481 "Failed allocating banks for "
522 "Failed allocating banks for " 482 "external radio\n");
523 "external radio\n"); 483 return ecode;
524 return ecode;
525 }
526 } 484 }
527 485
528 if (!AR_SREV_9100(ah)) { 486 if (!AR_SREV_9100(ah)) {
@@ -533,344 +491,22 @@ static int ath9k_hw_post_init(struct ath_hw *ah)
533 return 0; 491 return 0;
534} 492}
535 493
536static bool ath9k_hw_devid_supported(u16 devid) 494static void ath9k_hw_attach_ops(struct ath_hw *ah)
537{
538 switch (devid) {
539 case AR5416_DEVID_PCI:
540 case AR5416_DEVID_PCIE:
541 case AR5416_AR9100_DEVID:
542 case AR9160_DEVID_PCI:
543 case AR9280_DEVID_PCI:
544 case AR9280_DEVID_PCIE:
545 case AR9285_DEVID_PCIE:
546 case AR5416_DEVID_AR9287_PCI:
547 case AR5416_DEVID_AR9287_PCIE:
548 case AR2427_DEVID_PCIE:
549 return true;
550 default:
551 break;
552 }
553 return false;
554}
555
556static bool ath9k_hw_macversion_supported(u32 macversion)
557{
558 switch (macversion) {
559 case AR_SREV_VERSION_5416_PCI:
560 case AR_SREV_VERSION_5416_PCIE:
561 case AR_SREV_VERSION_9160:
562 case AR_SREV_VERSION_9100:
563 case AR_SREV_VERSION_9280:
564 case AR_SREV_VERSION_9285:
565 case AR_SREV_VERSION_9287:
566 case AR_SREV_VERSION_9271:
567 return true;
568 default:
569 break;
570 }
571 return false;
572}
573
574static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
575{
576 if (AR_SREV_9160_10_OR_LATER(ah)) {
577 if (AR_SREV_9280_10_OR_LATER(ah)) {
578 ah->iq_caldata.calData = &iq_cal_single_sample;
579 ah->adcgain_caldata.calData =
580 &adc_gain_cal_single_sample;
581 ah->adcdc_caldata.calData =
582 &adc_dc_cal_single_sample;
583 ah->adcdc_calinitdata.calData =
584 &adc_init_dc_cal;
585 } else {
586 ah->iq_caldata.calData = &iq_cal_multi_sample;
587 ah->adcgain_caldata.calData =
588 &adc_gain_cal_multi_sample;
589 ah->adcdc_caldata.calData =
590 &adc_dc_cal_multi_sample;
591 ah->adcdc_calinitdata.calData =
592 &adc_init_dc_cal;
593 }
594 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
595 }
596}
597
598static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
599{
600 if (AR_SREV_9271(ah)) {
601 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
602 ARRAY_SIZE(ar9271Modes_9271), 6);
603 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
604 ARRAY_SIZE(ar9271Common_9271), 2);
605 INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271,
606 ar9271Common_normal_cck_fir_coeff_9271,
607 ARRAY_SIZE(ar9271Common_normal_cck_fir_coeff_9271), 2);
608 INIT_INI_ARRAY(&ah->iniCommon_japan_2484_cck_fir_coeff_9271,
609 ar9271Common_japan_2484_cck_fir_coeff_9271,
610 ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271), 2);
611 INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
612 ar9271Modes_9271_1_0_only,
613 ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
614 INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg,
615 ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 6);
616 INIT_INI_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
617 ar9271Modes_high_power_tx_gain_9271,
618 ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 6);
619 INIT_INI_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
620 ar9271Modes_normal_power_tx_gain_9271,
621 ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 6);
622 return;
623 }
624
625 if (AR_SREV_9287_11_OR_LATER(ah)) {
626 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
627 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
628 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
629 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
630 if (ah->config.pcie_clock_req)
631 INIT_INI_ARRAY(&ah->iniPcieSerdes,
632 ar9287PciePhy_clkreq_off_L1_9287_1_1,
633 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
634 else
635 INIT_INI_ARRAY(&ah->iniPcieSerdes,
636 ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
637 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
638 2);
639 } else if (AR_SREV_9287_10_OR_LATER(ah)) {
640 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
641 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
642 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
643 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
644
645 if (ah->config.pcie_clock_req)
646 INIT_INI_ARRAY(&ah->iniPcieSerdes,
647 ar9287PciePhy_clkreq_off_L1_9287_1_0,
648 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
649 else
650 INIT_INI_ARRAY(&ah->iniPcieSerdes,
651 ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
652 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
653 2);
654 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
655
656
657 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
658 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
659 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
660 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
661
662 if (ah->config.pcie_clock_req) {
663 INIT_INI_ARRAY(&ah->iniPcieSerdes,
664 ar9285PciePhy_clkreq_off_L1_9285_1_2,
665 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
666 } else {
667 INIT_INI_ARRAY(&ah->iniPcieSerdes,
668 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
669 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
670 2);
671 }
672 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
673 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
674 ARRAY_SIZE(ar9285Modes_9285), 6);
675 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
676 ARRAY_SIZE(ar9285Common_9285), 2);
677
678 if (ah->config.pcie_clock_req) {
679 INIT_INI_ARRAY(&ah->iniPcieSerdes,
680 ar9285PciePhy_clkreq_off_L1_9285,
681 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
682 } else {
683 INIT_INI_ARRAY(&ah->iniPcieSerdes,
684 ar9285PciePhy_clkreq_always_on_L1_9285,
685 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
686 }
687 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
688 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
689 ARRAY_SIZE(ar9280Modes_9280_2), 6);
690 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
691 ARRAY_SIZE(ar9280Common_9280_2), 2);
692
693 if (ah->config.pcie_clock_req) {
694 INIT_INI_ARRAY(&ah->iniPcieSerdes,
695 ar9280PciePhy_clkreq_off_L1_9280,
696 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
697 } else {
698 INIT_INI_ARRAY(&ah->iniPcieSerdes,
699 ar9280PciePhy_clkreq_always_on_L1_9280,
700 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
701 }
702 INIT_INI_ARRAY(&ah->iniModesAdditional,
703 ar9280Modes_fast_clock_9280_2,
704 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
705 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
706 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
707 ARRAY_SIZE(ar9280Modes_9280), 6);
708 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
709 ARRAY_SIZE(ar9280Common_9280), 2);
710 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
711 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
712 ARRAY_SIZE(ar5416Modes_9160), 6);
713 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
714 ARRAY_SIZE(ar5416Common_9160), 2);
715 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
716 ARRAY_SIZE(ar5416Bank0_9160), 2);
717 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
718 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
719 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
720 ARRAY_SIZE(ar5416Bank1_9160), 2);
721 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
722 ARRAY_SIZE(ar5416Bank2_9160), 2);
723 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
724 ARRAY_SIZE(ar5416Bank3_9160), 3);
725 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
726 ARRAY_SIZE(ar5416Bank6_9160), 3);
727 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
728 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
729 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
730 ARRAY_SIZE(ar5416Bank7_9160), 2);
731 if (AR_SREV_9160_11(ah)) {
732 INIT_INI_ARRAY(&ah->iniAddac,
733 ar5416Addac_91601_1,
734 ARRAY_SIZE(ar5416Addac_91601_1), 2);
735 } else {
736 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
737 ARRAY_SIZE(ar5416Addac_9160), 2);
738 }
739 } else if (AR_SREV_9100_OR_LATER(ah)) {
740 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
741 ARRAY_SIZE(ar5416Modes_9100), 6);
742 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
743 ARRAY_SIZE(ar5416Common_9100), 2);
744 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
745 ARRAY_SIZE(ar5416Bank0_9100), 2);
746 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
747 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
748 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
749 ARRAY_SIZE(ar5416Bank1_9100), 2);
750 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
751 ARRAY_SIZE(ar5416Bank2_9100), 2);
752 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
753 ARRAY_SIZE(ar5416Bank3_9100), 3);
754 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
755 ARRAY_SIZE(ar5416Bank6_9100), 3);
756 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
757 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
758 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
759 ARRAY_SIZE(ar5416Bank7_9100), 2);
760 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
761 ARRAY_SIZE(ar5416Addac_9100), 2);
762 } else {
763 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
764 ARRAY_SIZE(ar5416Modes), 6);
765 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
766 ARRAY_SIZE(ar5416Common), 2);
767 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
768 ARRAY_SIZE(ar5416Bank0), 2);
769 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
770 ARRAY_SIZE(ar5416BB_RfGain), 3);
771 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
772 ARRAY_SIZE(ar5416Bank1), 2);
773 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
774 ARRAY_SIZE(ar5416Bank2), 2);
775 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
776 ARRAY_SIZE(ar5416Bank3), 3);
777 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
778 ARRAY_SIZE(ar5416Bank6), 3);
779 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
780 ARRAY_SIZE(ar5416Bank6TPC), 3);
781 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
782 ARRAY_SIZE(ar5416Bank7), 2);
783 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
784 ARRAY_SIZE(ar5416Addac), 2);
785 }
786}
787
788static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
789{
790 if (AR_SREV_9287_11_OR_LATER(ah))
791 INIT_INI_ARRAY(&ah->iniModesRxGain,
792 ar9287Modes_rx_gain_9287_1_1,
793 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
794 else if (AR_SREV_9287_10(ah))
795 INIT_INI_ARRAY(&ah->iniModesRxGain,
796 ar9287Modes_rx_gain_9287_1_0,
797 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
798 else if (AR_SREV_9280_20(ah))
799 ath9k_hw_init_rxgain_ini(ah);
800
801 if (AR_SREV_9287_11_OR_LATER(ah)) {
802 INIT_INI_ARRAY(&ah->iniModesTxGain,
803 ar9287Modes_tx_gain_9287_1_1,
804 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
805 } else if (AR_SREV_9287_10(ah)) {
806 INIT_INI_ARRAY(&ah->iniModesTxGain,
807 ar9287Modes_tx_gain_9287_1_0,
808 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
809 } else if (AR_SREV_9280_20(ah)) {
810 ath9k_hw_init_txgain_ini(ah);
811 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
812 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
813
814 /* txgain table */
815 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
816 if (AR_SREV_9285E_20(ah)) {
817 INIT_INI_ARRAY(&ah->iniModesTxGain,
818 ar9285Modes_XE2_0_high_power,
819 ARRAY_SIZE(
820 ar9285Modes_XE2_0_high_power), 6);
821 } else {
822 INIT_INI_ARRAY(&ah->iniModesTxGain,
823 ar9285Modes_high_power_tx_gain_9285_1_2,
824 ARRAY_SIZE(
825 ar9285Modes_high_power_tx_gain_9285_1_2), 6);
826 }
827 } else {
828 if (AR_SREV_9285E_20(ah)) {
829 INIT_INI_ARRAY(&ah->iniModesTxGain,
830 ar9285Modes_XE2_0_normal_power,
831 ARRAY_SIZE(
832 ar9285Modes_XE2_0_normal_power), 6);
833 } else {
834 INIT_INI_ARRAY(&ah->iniModesTxGain,
835 ar9285Modes_original_tx_gain_9285_1_2,
836 ARRAY_SIZE(
837 ar9285Modes_original_tx_gain_9285_1_2), 6);
838 }
839 }
840 }
841}
842
843static void ath9k_hw_init_eeprom_fix(struct ath_hw *ah)
844{ 495{
845 struct base_eep_header *pBase = &(ah->eeprom.def.baseEepHeader); 496 if (AR_SREV_9300_20_OR_LATER(ah))
846 struct ath_common *common = ath9k_hw_common(ah); 497 ar9003_hw_attach_ops(ah);
847 498 else
848 ah->need_an_top2_fixup = (ah->hw_version.devid == AR9280_DEVID_PCI) && 499 ar9002_hw_attach_ops(ah);
849 (ah->eep_map != EEP_MAP_4KBITS) &&
850 ((pBase->version & 0xff) > 0x0a) &&
851 (pBase->pwdclkind == 0);
852
853 if (ah->need_an_top2_fixup)
854 ath_print(common, ATH_DBG_EEPROM,
855 "needs fixup for AR_AN_TOP2 register\n");
856} 500}
857 501
858int ath9k_hw_init(struct ath_hw *ah) 502/* Called for all hardware families */
503static int __ath9k_hw_init(struct ath_hw *ah)
859{ 504{
860 struct ath_common *common = ath9k_hw_common(ah); 505 struct ath_common *common = ath9k_hw_common(ah);
861 int r = 0; 506 int r = 0;
862 507
863 if (common->bus_ops->ath_bus_type != ATH_USB) { 508 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
864 if (!ath9k_hw_devid_supported(ah->hw_version.devid)) { 509 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
865 ath_print(common, ATH_DBG_FATAL,
866 "Unsupported device ID: 0x%0x\n",
867 ah->hw_version.devid);
868 return -EOPNOTSUPP;
869 }
870 }
871
872 ath9k_hw_init_defaults(ah);
873 ath9k_hw_init_config(ah);
874 510
875 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 511 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
876 ath_print(common, ATH_DBG_FATAL, 512 ath_print(common, ATH_DBG_FATAL,
@@ -878,6 +514,11 @@ int ath9k_hw_init(struct ath_hw *ah)
878 return -EIO; 514 return -EIO;
879 } 515 }
880 516
517 ath9k_hw_init_defaults(ah);
518 ath9k_hw_init_config(ah);
519
520 ath9k_hw_attach_ops(ah);
521
881 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 522 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
882 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n"); 523 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
883 return -EIO; 524 return -EIO;
@@ -902,7 +543,7 @@ int ath9k_hw_init(struct ath_hw *ah)
902 else 543 else
903 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; 544 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
904 545
905 if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) { 546 if (!ath9k_hw_macversion_supported(ah)) {
906 ath_print(common, ATH_DBG_FATAL, 547 ath_print(common, ATH_DBG_FATAL,
907 "Mac Chip Rev 0x%02x.%x is not supported by " 548 "Mac Chip Rev 0x%02x.%x is not supported by "
908 "this driver\n", ah->hw_version.macVersion, 549 "this driver\n", ah->hw_version.macVersion,
@@ -910,28 +551,15 @@ int ath9k_hw_init(struct ath_hw *ah)
910 return -EOPNOTSUPP; 551 return -EOPNOTSUPP;
911 } 552 }
912 553
913 if (AR_SREV_9100(ah)) { 554 if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
914 ah->iq_caldata.calData = &iq_cal_multi_sample;
915 ah->supp_cals = IQ_MISMATCH_CAL;
916 ah->is_pciexpress = false;
917 }
918
919 if (AR_SREV_9271(ah))
920 ah->is_pciexpress = false; 555 ah->is_pciexpress = false;
921 556
922 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 557 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
923
924 ath9k_hw_init_cal_settings(ah); 558 ath9k_hw_init_cal_settings(ah);
925 559
926 ah->ani_function = ATH9K_ANI_ALL; 560 ah->ani_function = ATH9K_ANI_ALL;
927 if (AR_SREV_9280_10_OR_LATER(ah)) { 561 if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
928 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; 562 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
929 ah->ath9k_hw_rf_set_freq = &ath9k_hw_ar9280_set_channel;
930 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_9280_spur_mitigate;
931 } else {
932 ah->ath9k_hw_rf_set_freq = &ath9k_hw_set_channel;
933 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_spur_mitigate;
934 }
935 563
936 ath9k_hw_init_mode_regs(ah); 564 ath9k_hw_init_mode_regs(ah);
937 565
@@ -940,15 +568,8 @@ int ath9k_hw_init(struct ath_hw *ah)
940 else 568 else
941 ath9k_hw_disablepcie(ah); 569 ath9k_hw_disablepcie(ah);
942 570
943 /* Support for Japan ch.14 (2484) spread */ 571 if (!AR_SREV_9300_20_OR_LATER(ah))
944 if (AR_SREV_9287_11_OR_LATER(ah)) { 572 ar9002_hw_cck_chan14_spread(ah);
945 INIT_INI_ARRAY(&ah->iniCckfirNormal,
946 ar9287Common_normal_cck_fir_coeff_92871_1,
947 ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
948 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
949 ar9287Common_japan_2484_cck_fir_coeff_92871_1,
950 ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
951 }
952 573
953 r = ath9k_hw_post_init(ah); 574 r = ath9k_hw_post_init(ah);
954 if (r) 575 if (r)
@@ -959,8 +580,6 @@ int ath9k_hw_init(struct ath_hw *ah)
959 if (r) 580 if (r)
960 return r; 581 return r;
961 582
962 ath9k_hw_init_eeprom_fix(ah);
963
964 r = ath9k_hw_init_macaddr(ah); 583 r = ath9k_hw_init_macaddr(ah);
965 if (r) { 584 if (r) {
966 ath_print(common, ATH_DBG_FATAL, 585 ath_print(common, ATH_DBG_FATAL,
@@ -973,6 +592,9 @@ int ath9k_hw_init(struct ath_hw *ah)
973 else 592 else
974 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 593 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
975 594
595 if (AR_SREV_9300_20_OR_LATER(ah))
596 ar9003_hw_set_nf_limits(ah);
597
976 ath9k_init_nfcal_hist_buffer(ah); 598 ath9k_init_nfcal_hist_buffer(ah);
977 599
978 common->state = ATH_HW_INITIALIZED; 600 common->state = ATH_HW_INITIALIZED;
@@ -980,24 +602,50 @@ int ath9k_hw_init(struct ath_hw *ah)
980 return 0; 602 return 0;
981} 603}
982 604
983static void ath9k_hw_init_bb(struct ath_hw *ah, 605int ath9k_hw_init(struct ath_hw *ah)
984 struct ath9k_channel *chan)
985{ 606{
986 u32 synthDelay; 607 int ret;
608 struct ath_common *common = ath9k_hw_common(ah);
987 609
988 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 610 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
989 if (IS_CHAN_B(chan)) 611 switch (ah->hw_version.devid) {
990 synthDelay = (4 * synthDelay) / 22; 612 case AR5416_DEVID_PCI:
991 else 613 case AR5416_DEVID_PCIE:
992 synthDelay /= 10; 614 case AR5416_AR9100_DEVID:
615 case AR9160_DEVID_PCI:
616 case AR9280_DEVID_PCI:
617 case AR9280_DEVID_PCIE:
618 case AR9285_DEVID_PCIE:
619 case AR9287_DEVID_PCI:
620 case AR9287_DEVID_PCIE:
621 case AR2427_DEVID_PCIE:
622 case AR9300_DEVID_PCIE:
623 break;
624 default:
625 if (common->bus_ops->ath_bus_type == ATH_USB)
626 break;
627 ath_print(common, ATH_DBG_FATAL,
628 "Hardware device ID 0x%04x not supported\n",
629 ah->hw_version.devid);
630 return -EOPNOTSUPP;
631 }
993 632
994 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 633 ret = __ath9k_hw_init(ah);
634 if (ret) {
635 ath_print(common, ATH_DBG_FATAL,
636 "Unable to initialize hardware; "
637 "initialization status: %d\n", ret);
638 return ret;
639 }
995 640
996 udelay(synthDelay + BASE_ACTIVATE_DELAY); 641 return 0;
997} 642}
643EXPORT_SYMBOL(ath9k_hw_init);
998 644
999static void ath9k_hw_init_qos(struct ath_hw *ah) 645static void ath9k_hw_init_qos(struct ath_hw *ah)
1000{ 646{
647 ENABLE_REGWRITE_BUFFER(ah);
648
1001 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); 649 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
1002 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); 650 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
1003 651
@@ -1011,69 +659,16 @@ static void ath9k_hw_init_qos(struct ath_hw *ah)
1011 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); 659 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
1012 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); 660 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
1013 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 661 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
662
663 REGWRITE_BUFFER_FLUSH(ah);
664 DISABLE_REGWRITE_BUFFER(ah);
1014} 665}
1015 666
1016static void ath9k_hw_init_pll(struct ath_hw *ah, 667static void ath9k_hw_init_pll(struct ath_hw *ah,
1017 struct ath9k_channel *chan) 668 struct ath9k_channel *chan)
1018{ 669{
1019 u32 pll; 670 u32 pll = ath9k_hw_compute_pll_control(ah, chan);
1020
1021 if (AR_SREV_9100(ah)) {
1022 if (chan && IS_CHAN_5GHZ(chan))
1023 pll = 0x1450;
1024 else
1025 pll = 0x1458;
1026 } else {
1027 if (AR_SREV_9280_10_OR_LATER(ah)) {
1028 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1029
1030 if (chan && IS_CHAN_HALF_RATE(chan))
1031 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1032 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1033 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1034
1035 if (chan && IS_CHAN_5GHZ(chan)) {
1036 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1037
1038
1039 if (AR_SREV_9280_20(ah)) {
1040 if (((chan->channel % 20) == 0)
1041 || ((chan->channel % 10) == 0))
1042 pll = 0x2850;
1043 else
1044 pll = 0x142c;
1045 }
1046 } else {
1047 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1048 }
1049 671
1050 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1051
1052 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1053
1054 if (chan && IS_CHAN_HALF_RATE(chan))
1055 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1056 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1057 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1058
1059 if (chan && IS_CHAN_5GHZ(chan))
1060 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1061 else
1062 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1063 } else {
1064 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1065
1066 if (chan && IS_CHAN_HALF_RATE(chan))
1067 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1068 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1069 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1070
1071 if (chan && IS_CHAN_5GHZ(chan))
1072 pll |= SM(0xa, AR_RTC_PLL_DIV);
1073 else
1074 pll |= SM(0xb, AR_RTC_PLL_DIV);
1075 }
1076 }
1077 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 672 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1078 673
1079 /* Switch the core clock for ar9271 to 117Mhz */ 674 /* Switch the core clock for ar9271 to 117Mhz */
@@ -1087,43 +682,6 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
1087 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 682 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1088} 683}
1089 684
1090static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1091{
1092 int rx_chainmask, tx_chainmask;
1093
1094 rx_chainmask = ah->rxchainmask;
1095 tx_chainmask = ah->txchainmask;
1096
1097 switch (rx_chainmask) {
1098 case 0x5:
1099 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1100 AR_PHY_SWAP_ALT_CHAIN);
1101 case 0x3:
1102 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
1103 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1104 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1105 break;
1106 }
1107 case 0x1:
1108 case 0x2:
1109 case 0x7:
1110 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1111 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1112 break;
1113 default:
1114 break;
1115 }
1116
1117 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1118 if (tx_chainmask == 0x5) {
1119 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1120 AR_PHY_SWAP_ALT_CHAIN);
1121 }
1122 if (AR_SREV_9100(ah))
1123 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1124 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1125}
1126
1127static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, 685static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1128 enum nl80211_iftype opmode) 686 enum nl80211_iftype opmode)
1129{ 687{
@@ -1133,16 +691,30 @@ static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1133 AR_IMR_RXORN | 691 AR_IMR_RXORN |
1134 AR_IMR_BCNMISC; 692 AR_IMR_BCNMISC;
1135 693
1136 if (ah->config.rx_intr_mitigation) 694 if (AR_SREV_9300_20_OR_LATER(ah)) {
1137 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 695 imr_reg |= AR_IMR_RXOK_HP;
1138 else 696 if (ah->config.rx_intr_mitigation)
1139 imr_reg |= AR_IMR_RXOK; 697 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
698 else
699 imr_reg |= AR_IMR_RXOK_LP;
1140 700
1141 imr_reg |= AR_IMR_TXOK; 701 } else {
702 if (ah->config.rx_intr_mitigation)
703 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
704 else
705 imr_reg |= AR_IMR_RXOK;
706 }
707
708 if (ah->config.tx_intr_mitigation)
709 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
710 else
711 imr_reg |= AR_IMR_TXOK;
1142 712
1143 if (opmode == NL80211_IFTYPE_AP) 713 if (opmode == NL80211_IFTYPE_AP)
1144 imr_reg |= AR_IMR_MIB; 714 imr_reg |= AR_IMR_MIB;
1145 715
716 ENABLE_REGWRITE_BUFFER(ah);
717
1146 REG_WRITE(ah, AR_IMR, imr_reg); 718 REG_WRITE(ah, AR_IMR, imr_reg);
1147 ah->imrs2_reg |= AR_IMR_S2_GTT; 719 ah->imrs2_reg |= AR_IMR_S2_GTT;
1148 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); 720 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
@@ -1152,6 +724,16 @@ static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1152 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT); 724 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1153 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); 725 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1154 } 726 }
727
728 REGWRITE_BUFFER_FLUSH(ah);
729 DISABLE_REGWRITE_BUFFER(ah);
730
731 if (AR_SREV_9300_20_OR_LATER(ah)) {
732 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
733 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
734 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
735 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
736 }
1155} 737}
1156 738
1157static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) 739static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
@@ -1243,8 +825,7 @@ void ath9k_hw_deinit(struct ath_hw *ah)
1243 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 825 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1244 826
1245free_hw: 827free_hw:
1246 if (!AR_SREV_9280_10_OR_LATER(ah)) 828 ath9k_hw_rf_free_ext_banks(ah);
1247 ath9k_hw_rf_free_ext_banks(ah);
1248} 829}
1249EXPORT_SYMBOL(ath9k_hw_deinit); 830EXPORT_SYMBOL(ath9k_hw_deinit);
1250 831
@@ -1252,73 +833,7 @@ EXPORT_SYMBOL(ath9k_hw_deinit);
1252/* INI */ 833/* INI */
1253/*******/ 834/*******/
1254 835
1255static void ath9k_hw_override_ini(struct ath_hw *ah, 836u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
1256 struct ath9k_channel *chan)
1257{
1258 u32 val;
1259
1260 /*
1261 * Set the RX_ABORT and RX_DIS and clear if off only after
1262 * RXE is set for MAC. This prevents frames with corrupted
1263 * descriptor status.
1264 */
1265 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1266
1267 if (AR_SREV_9280_10_OR_LATER(ah)) {
1268 val = REG_READ(ah, AR_PCU_MISC_MODE2);
1269
1270 if (!AR_SREV_9271(ah))
1271 val &= ~AR_PCU_MISC_MODE2_HWWAR1;
1272
1273 if (AR_SREV_9287_10_OR_LATER(ah))
1274 val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
1275
1276 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
1277 }
1278
1279 if (!AR_SREV_5416_20_OR_LATER(ah) ||
1280 AR_SREV_9280_10_OR_LATER(ah))
1281 return;
1282 /*
1283 * Disable BB clock gating
1284 * Necessary to avoid issues on AR5416 2.0
1285 */
1286 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1287
1288 /*
1289 * Disable RIFS search on some chips to avoid baseband
1290 * hang issues.
1291 */
1292 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
1293 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
1294 val &= ~AR_PHY_RIFS_INIT_DELAY;
1295 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
1296 }
1297}
1298
1299static void ath9k_olc_init(struct ath_hw *ah)
1300{
1301 u32 i;
1302
1303 if (OLC_FOR_AR9287_10_LATER) {
1304 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
1305 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
1306 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
1307 AR9287_AN_TXPC0_TXPCMODE,
1308 AR9287_AN_TXPC0_TXPCMODE_S,
1309 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
1310 udelay(100);
1311 } else {
1312 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1313 ah->originalGain[i] =
1314 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1315 AR_PHY_TX_GAIN);
1316 ah->PDADCdelta = 0;
1317 }
1318}
1319
1320static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1321 struct ath9k_channel *chan)
1322{ 837{
1323 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); 838 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1324 839
@@ -1332,193 +847,24 @@ static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1332 return ctl; 847 return ctl;
1333} 848}
1334 849
1335static int ath9k_hw_process_ini(struct ath_hw *ah,
1336 struct ath9k_channel *chan)
1337{
1338 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1339 int i, regWrites = 0;
1340 struct ieee80211_channel *channel = chan->chan;
1341 u32 modesIndex, freqIndex;
1342
1343 switch (chan->chanmode) {
1344 case CHANNEL_A:
1345 case CHANNEL_A_HT20:
1346 modesIndex = 1;
1347 freqIndex = 1;
1348 break;
1349 case CHANNEL_A_HT40PLUS:
1350 case CHANNEL_A_HT40MINUS:
1351 modesIndex = 2;
1352 freqIndex = 1;
1353 break;
1354 case CHANNEL_G:
1355 case CHANNEL_G_HT20:
1356 case CHANNEL_B:
1357 modesIndex = 4;
1358 freqIndex = 2;
1359 break;
1360 case CHANNEL_G_HT40PLUS:
1361 case CHANNEL_G_HT40MINUS:
1362 modesIndex = 3;
1363 freqIndex = 2;
1364 break;
1365
1366 default:
1367 return -EINVAL;
1368 }
1369
1370 /* Set correct baseband to analog shift setting to access analog chips */
1371 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1372
1373 /* Write ADDAC shifts */
1374 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1375 ah->eep_ops->set_addac(ah, chan);
1376
1377 if (AR_SREV_5416_22_OR_LATER(ah)) {
1378 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1379 } else {
1380 struct ar5416IniArray temp;
1381 u32 addacSize =
1382 sizeof(u32) * ah->iniAddac.ia_rows *
1383 ah->iniAddac.ia_columns;
1384
1385 /* For AR5416 2.0/2.1 */
1386 memcpy(ah->addac5416_21,
1387 ah->iniAddac.ia_array, addacSize);
1388
1389 /* override CLKDRV value at [row, column] = [31, 1] */
1390 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1391
1392 temp.ia_array = ah->addac5416_21;
1393 temp.ia_columns = ah->iniAddac.ia_columns;
1394 temp.ia_rows = ah->iniAddac.ia_rows;
1395 REG_WRITE_ARRAY(&temp, 1, regWrites);
1396 }
1397
1398 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1399
1400 for (i = 0; i < ah->iniModes.ia_rows; i++) {
1401 u32 reg = INI_RA(&ah->iniModes, i, 0);
1402 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1403
1404 if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup)
1405 val &= ~AR_AN_TOP2_PWDCLKIND;
1406
1407 REG_WRITE(ah, reg, val);
1408
1409 if (reg >= 0x7800 && reg < 0x78a0
1410 && ah->config.analog_shiftreg) {
1411 udelay(100);
1412 }
1413
1414 DO_DELAY(regWrites);
1415 }
1416
1417 if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1418 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1419
1420 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1421 AR_SREV_9287_10_OR_LATER(ah))
1422 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1423
1424 if (AR_SREV_9271_10(ah))
1425 REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
1426 modesIndex, regWrites);
1427
1428 /* Write common array parameters */
1429 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1430 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1431 u32 val = INI_RA(&ah->iniCommon, i, 1);
1432
1433 REG_WRITE(ah, reg, val);
1434
1435 if (reg >= 0x7800 && reg < 0x78a0
1436 && ah->config.analog_shiftreg) {
1437 udelay(100);
1438 }
1439
1440 DO_DELAY(regWrites);
1441 }
1442
1443 if (AR_SREV_9271(ah)) {
1444 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1)
1445 REG_WRITE_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
1446 modesIndex, regWrites);
1447 else
1448 REG_WRITE_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
1449 modesIndex, regWrites);
1450 }
1451
1452 ath9k_hw_write_regs(ah, freqIndex, regWrites);
1453
1454 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1455 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1456 regWrites);
1457 }
1458
1459 ath9k_hw_override_ini(ah, chan);
1460 ath9k_hw_set_regs(ah, chan);
1461 ath9k_hw_init_chain_masks(ah);
1462
1463 if (OLC_FOR_AR9280_20_LATER)
1464 ath9k_olc_init(ah);
1465
1466 /* Set TX power */
1467 ah->eep_ops->set_txpower(ah, chan,
1468 ath9k_regd_get_ctl(regulatory, chan),
1469 channel->max_antenna_gain * 2,
1470 channel->max_power * 2,
1471 min((u32) MAX_RATE_POWER,
1472 (u32) regulatory->power_limit));
1473
1474 /* Write analog registers */
1475 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1476 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1477 "ar5416SetRfRegs failed\n");
1478 return -EIO;
1479 }
1480
1481 return 0;
1482}
1483
1484/****************************************/ 850/****************************************/
1485/* Reset and Channel Switching Routines */ 851/* Reset and Channel Switching Routines */
1486/****************************************/ 852/****************************************/
1487 853
1488static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1489{
1490 u32 rfMode = 0;
1491
1492 if (chan == NULL)
1493 return;
1494
1495 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1496 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1497
1498 if (!AR_SREV_9280_10_OR_LATER(ah))
1499 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1500 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1501
1502 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1503 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1504
1505 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1506}
1507
1508static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1509{
1510 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1511}
1512
1513static inline void ath9k_hw_set_dma(struct ath_hw *ah) 854static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1514{ 855{
856 struct ath_common *common = ath9k_hw_common(ah);
1515 u32 regval; 857 u32 regval;
1516 858
859 ENABLE_REGWRITE_BUFFER(ah);
860
1517 /* 861 /*
1518 * set AHB_MODE not to do cacheline prefetches 862 * set AHB_MODE not to do cacheline prefetches
1519 */ 863 */
1520 regval = REG_READ(ah, AR_AHB_MODE); 864 if (!AR_SREV_9300_20_OR_LATER(ah)) {
1521 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN); 865 regval = REG_READ(ah, AR_AHB_MODE);
866 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
867 }
1522 868
1523 /* 869 /*
1524 * let mac dma reads be in 128 byte chunks 870 * let mac dma reads be in 128 byte chunks
@@ -1526,12 +872,18 @@ static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1526 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK; 872 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1527 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B); 873 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1528 874
875 REGWRITE_BUFFER_FLUSH(ah);
876 DISABLE_REGWRITE_BUFFER(ah);
877
1529 /* 878 /*
1530 * Restore TX Trigger Level to its pre-reset value. 879 * Restore TX Trigger Level to its pre-reset value.
1531 * The initial value depends on whether aggregation is enabled, and is 880 * The initial value depends on whether aggregation is enabled, and is
1532 * adjusted whenever underruns are detected. 881 * adjusted whenever underruns are detected.
1533 */ 882 */
1534 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); 883 if (!AR_SREV_9300_20_OR_LATER(ah))
884 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
885
886 ENABLE_REGWRITE_BUFFER(ah);
1535 887
1536 /* 888 /*
1537 * let mac dma writes be in 128 byte chunks 889 * let mac dma writes be in 128 byte chunks
@@ -1544,6 +896,14 @@ static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1544 */ 896 */
1545 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); 897 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1546 898
899 if (AR_SREV_9300_20_OR_LATER(ah)) {
900 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
901 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
902
903 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
904 ah->caps.rx_status_len);
905 }
906
1547 /* 907 /*
1548 * reduce the number of usable entries in PCU TXBUF to avoid 908 * reduce the number of usable entries in PCU TXBUF to avoid
1549 * wrap around issues. 909 * wrap around issues.
@@ -1559,6 +919,12 @@ static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1559 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 919 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1560 AR_PCU_TXBUF_CTRL_USABLE_SIZE); 920 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1561 } 921 }
922
923 REGWRITE_BUFFER_FLUSH(ah);
924 DISABLE_REGWRITE_BUFFER(ah);
925
926 if (AR_SREV_9300_20_OR_LATER(ah))
927 ath9k_hw_reset_txstatus_ring(ah);
1562} 928}
1563 929
1564static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) 930static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
@@ -1586,10 +952,8 @@ static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1586 } 952 }
1587} 953}
1588 954
1589static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, 955void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1590 u32 coef_scaled, 956 u32 *coef_mantissa, u32 *coef_exponent)
1591 u32 *coef_mantissa,
1592 u32 *coef_exponent)
1593{ 957{
1594 u32 coef_exp, coef_man; 958 u32 coef_exp, coef_man;
1595 959
@@ -1605,40 +969,6 @@ static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1605 *coef_exponent = coef_exp - 16; 969 *coef_exponent = coef_exp - 16;
1606} 970}
1607 971
1608static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1609 struct ath9k_channel *chan)
1610{
1611 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1612 u32 clockMhzScaled = 0x64000000;
1613 struct chan_centers centers;
1614
1615 if (IS_CHAN_HALF_RATE(chan))
1616 clockMhzScaled = clockMhzScaled >> 1;
1617 else if (IS_CHAN_QUARTER_RATE(chan))
1618 clockMhzScaled = clockMhzScaled >> 2;
1619
1620 ath9k_hw_get_channel_centers(ah, chan, &centers);
1621 coef_scaled = clockMhzScaled / centers.synth_center;
1622
1623 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1624 &ds_coef_exp);
1625
1626 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1627 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1628 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1629 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1630
1631 coef_scaled = (9 * coef_scaled) / 10;
1632
1633 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1634 &ds_coef_exp);
1635
1636 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1637 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1638 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1639 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1640}
1641
1642static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) 972static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1643{ 973{
1644 u32 rst_flags; 974 u32 rst_flags;
@@ -1652,6 +982,8 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1652 (void)REG_READ(ah, AR_RTC_DERIVED_CLK); 982 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1653 } 983 }
1654 984
985 ENABLE_REGWRITE_BUFFER(ah);
986
1655 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 987 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1656 AR_RTC_FORCE_WAKE_ON_INT); 988 AR_RTC_FORCE_WAKE_ON_INT);
1657 989
@@ -1663,11 +995,16 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1663 if (tmpReg & 995 if (tmpReg &
1664 (AR_INTR_SYNC_LOCAL_TIMEOUT | 996 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1665 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { 997 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
998 u32 val;
1666 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 999 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1667 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 1000
1668 } else { 1001 val = AR_RC_HOSTIF;
1002 if (!AR_SREV_9300_20_OR_LATER(ah))
1003 val |= AR_RC_AHB;
1004 REG_WRITE(ah, AR_RC, val);
1005
1006 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1669 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1007 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1670 }
1671 1008
1672 rst_flags = AR_RTC_RC_MAC_WARM; 1009 rst_flags = AR_RTC_RC_MAC_WARM;
1673 if (type == ATH9K_RESET_COLD) 1010 if (type == ATH9K_RESET_COLD)
@@ -1675,6 +1012,10 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1675 } 1012 }
1676 1013
1677 REG_WRITE(ah, AR_RTC_RC, rst_flags); 1014 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1015
1016 REGWRITE_BUFFER_FLUSH(ah);
1017 DISABLE_REGWRITE_BUFFER(ah);
1018
1678 udelay(50); 1019 udelay(50);
1679 1020
1680 REG_WRITE(ah, AR_RTC_RC, 0); 1021 REG_WRITE(ah, AR_RTC_RC, 0);
@@ -1695,16 +1036,23 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1695 1036
1696static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) 1037static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1697{ 1038{
1039 ENABLE_REGWRITE_BUFFER(ah);
1040
1698 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1041 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1699 AR_RTC_FORCE_WAKE_ON_INT); 1042 AR_RTC_FORCE_WAKE_ON_INT);
1700 1043
1701 if (!AR_SREV_9100(ah)) 1044 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1702 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1045 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1703 1046
1704 REG_WRITE(ah, AR_RTC_RESET, 0); 1047 REG_WRITE(ah, AR_RTC_RESET, 0);
1705 udelay(2);
1706 1048
1707 if (!AR_SREV_9100(ah)) 1049 REGWRITE_BUFFER_FLUSH(ah);
1050 DISABLE_REGWRITE_BUFFER(ah);
1051
1052 if (!AR_SREV_9300_20_OR_LATER(ah))
1053 udelay(2);
1054
1055 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1708 REG_WRITE(ah, AR_RC, 0); 1056 REG_WRITE(ah, AR_RC, 0);
1709 1057
1710 REG_WRITE(ah, AR_RTC_RESET, 1); 1058 REG_WRITE(ah, AR_RTC_RESET, 1);
@@ -1740,34 +1088,6 @@ static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1740 } 1088 }
1741} 1089}
1742 1090
1743static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan)
1744{
1745 u32 phymode;
1746 u32 enableDacFifo = 0;
1747
1748 if (AR_SREV_9285_10_OR_LATER(ah))
1749 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1750 AR_PHY_FC_ENABLE_DAC_FIFO);
1751
1752 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1753 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1754
1755 if (IS_CHAN_HT40(chan)) {
1756 phymode |= AR_PHY_FC_DYN2040_EN;
1757
1758 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1759 (chan->chanmode == CHANNEL_G_HT40PLUS))
1760 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1761
1762 }
1763 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1764
1765 ath9k_hw_set11nmac2040(ah);
1766
1767 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1768 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1769}
1770
1771static bool ath9k_hw_chip_reset(struct ath_hw *ah, 1091static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1772 struct ath9k_channel *chan) 1092 struct ath9k_channel *chan)
1773{ 1093{
@@ -1793,7 +1113,7 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1793 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 1113 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1794 struct ath_common *common = ath9k_hw_common(ah); 1114 struct ath_common *common = ath9k_hw_common(ah);
1795 struct ieee80211_channel *channel = chan->chan; 1115 struct ieee80211_channel *channel = chan->chan;
1796 u32 synthDelay, qnum; 1116 u32 qnum;
1797 int r; 1117 int r;
1798 1118
1799 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1119 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
@@ -1805,17 +1125,15 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1805 } 1125 }
1806 } 1126 }
1807 1127
1808 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); 1128 if (!ath9k_hw_rfbus_req(ah)) {
1809 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1810 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1811 ath_print(common, ATH_DBG_FATAL, 1129 ath_print(common, ATH_DBG_FATAL,
1812 "Could not kill baseband RX\n"); 1130 "Could not kill baseband RX\n");
1813 return false; 1131 return false;
1814 } 1132 }
1815 1133
1816 ath9k_hw_set_regs(ah, chan); 1134 ath9k_hw_set_channel_regs(ah, chan);
1817 1135
1818 r = ah->ath9k_hw_rf_set_freq(ah, chan); 1136 r = ath9k_hw_rf_set_freq(ah, chan);
1819 if (r) { 1137 if (r) {
1820 ath_print(common, ATH_DBG_FATAL, 1138 ath_print(common, ATH_DBG_FATAL,
1821 "Failed to set channel\n"); 1139 "Failed to set channel\n");
@@ -1829,20 +1147,12 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1829 min((u32) MAX_RATE_POWER, 1147 min((u32) MAX_RATE_POWER,
1830 (u32) regulatory->power_limit)); 1148 (u32) regulatory->power_limit));
1831 1149
1832 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 1150 ath9k_hw_rfbus_done(ah);
1833 if (IS_CHAN_B(chan))
1834 synthDelay = (4 * synthDelay) / 22;
1835 else
1836 synthDelay /= 10;
1837
1838 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1839
1840 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1841 1151
1842 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1152 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1843 ath9k_hw_set_delta_slope(ah, chan); 1153 ath9k_hw_set_delta_slope(ah, chan);
1844 1154
1845 ah->ath9k_hw_spur_mitigate_freq(ah, chan); 1155 ath9k_hw_spur_mitigate_freq(ah, chan);
1846 1156
1847 if (!chan->oneTimeCalsDone) 1157 if (!chan->oneTimeCalsDone)
1848 chan->oneTimeCalsDone = true; 1158 chan->oneTimeCalsDone = true;
@@ -1850,17 +1160,33 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1850 return true; 1160 return true;
1851} 1161}
1852 1162
1853static void ath9k_enable_rfkill(struct ath_hw *ah) 1163bool ath9k_hw_check_alive(struct ath_hw *ah)
1854{ 1164{
1855 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, 1165 int count = 50;
1856 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB); 1166 u32 reg;
1167
1168 if (AR_SREV_9285_10_OR_LATER(ah))
1169 return true;
1170
1171 do {
1172 reg = REG_READ(ah, AR_OBS_BUS_1);
1857 1173
1858 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2, 1174 if ((reg & 0x7E7FFFEF) == 0x00702400)
1859 AR_GPIO_INPUT_MUX2_RFSILENT); 1175 continue;
1176
1177 switch (reg & 0x7E000B00) {
1178 case 0x1E000000:
1179 case 0x52000B00:
1180 case 0x18000B00:
1181 continue;
1182 default:
1183 return true;
1184 }
1185 } while (count-- > 0);
1860 1186
1861 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio); 1187 return false;
1862 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
1863} 1188}
1189EXPORT_SYMBOL(ath9k_hw_check_alive);
1864 1190
1865int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 1191int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1866 bool bChannelChange) 1192 bool bChannelChange)
@@ -1871,11 +1197,18 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1871 u32 saveDefAntenna; 1197 u32 saveDefAntenna;
1872 u32 macStaId1; 1198 u32 macStaId1;
1873 u64 tsf = 0; 1199 u64 tsf = 0;
1874 int i, rx_chainmask, r; 1200 int i, r;
1875 1201
1876 ah->txchainmask = common->tx_chainmask; 1202 ah->txchainmask = common->tx_chainmask;
1877 ah->rxchainmask = common->rx_chainmask; 1203 ah->rxchainmask = common->rx_chainmask;
1878 1204
1205 if (!ah->chip_fullsleep) {
1206 ath9k_hw_abortpcurecv(ah);
1207 if (!ath9k_hw_stopdmarecv(ah))
1208 ath_print(common, ATH_DBG_XMIT,
1209 "Failed to stop receive dma\n");
1210 }
1211
1879 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1212 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1880 return -EIO; 1213 return -EIO;
1881 1214
@@ -1943,16 +1276,6 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1943 if (AR_SREV_9280_10_OR_LATER(ah)) 1276 if (AR_SREV_9280_10_OR_LATER(ah))
1944 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 1277 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1945 1278
1946 if (AR_SREV_9287_12_OR_LATER(ah)) {
1947 /* Enable ASYNC FIFO */
1948 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1949 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
1950 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
1951 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1952 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
1953 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1954 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
1955 }
1956 r = ath9k_hw_process_ini(ah, chan); 1279 r = ath9k_hw_process_ini(ah, chan);
1957 if (r) 1280 if (r)
1958 return r; 1281 return r;
@@ -1977,9 +1300,13 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1977 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1300 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1978 ath9k_hw_set_delta_slope(ah, chan); 1301 ath9k_hw_set_delta_slope(ah, chan);
1979 1302
1980 ah->ath9k_hw_spur_mitigate_freq(ah, chan); 1303 ath9k_hw_spur_mitigate_freq(ah, chan);
1981 ah->eep_ops->set_board_values(ah, chan); 1304 ah->eep_ops->set_board_values(ah, chan);
1982 1305
1306 ath9k_hw_set_operating_mode(ah, ah->opmode);
1307
1308 ENABLE_REGWRITE_BUFFER(ah);
1309
1983 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); 1310 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1984 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4) 1311 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1985 | macStaId1 1312 | macStaId1
@@ -1987,25 +1314,27 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1987 | (ah->config. 1314 | (ah->config.
1988 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) 1315 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1989 | ah->sta_id1_defaults); 1316 | ah->sta_id1_defaults);
1990 ath9k_hw_set_operating_mode(ah, ah->opmode);
1991
1992 ath_hw_setbssidmask(common); 1317 ath_hw_setbssidmask(common);
1993
1994 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 1318 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1995
1996 ath9k_hw_write_associd(ah); 1319 ath9k_hw_write_associd(ah);
1997
1998 REG_WRITE(ah, AR_ISR, ~0); 1320 REG_WRITE(ah, AR_ISR, ~0);
1999
2000 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 1321 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2001 1322
2002 r = ah->ath9k_hw_rf_set_freq(ah, chan); 1323 REGWRITE_BUFFER_FLUSH(ah);
1324 DISABLE_REGWRITE_BUFFER(ah);
1325
1326 r = ath9k_hw_rf_set_freq(ah, chan);
2003 if (r) 1327 if (r)
2004 return r; 1328 return r;
2005 1329
1330 ENABLE_REGWRITE_BUFFER(ah);
1331
2006 for (i = 0; i < AR_NUM_DCU; i++) 1332 for (i = 0; i < AR_NUM_DCU; i++)
2007 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 1333 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2008 1334
1335 REGWRITE_BUFFER_FLUSH(ah);
1336 DISABLE_REGWRITE_BUFFER(ah);
1337
2009 ah->intr_txqs = 0; 1338 ah->intr_txqs = 0;
2010 for (i = 0; i < ah->caps.total_queues; i++) 1339 for (i = 0; i < ah->caps.total_queues; i++)
2011 ath9k_hw_resettxqueue(ah, i); 1340 ath9k_hw_resettxqueue(ah, i);
@@ -2018,25 +1347,9 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2018 1347
2019 ath9k_hw_init_global_settings(ah); 1348 ath9k_hw_init_global_settings(ah);
2020 1349
2021 if (AR_SREV_9287_12_OR_LATER(ah)) { 1350 if (!AR_SREV_9300_20_OR_LATER(ah)) {
2022 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 1351 ar9002_hw_enable_async_fifo(ah);
2023 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR); 1352 ar9002_hw_enable_wep_aggregation(ah);
2024 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2025 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2026 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2027 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2028
2029 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2030 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2031
2032 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2033 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2034 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2035 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2036 }
2037 if (AR_SREV_9287_12_OR_LATER(ah)) {
2038 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2039 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2040 } 1353 }
2041 1354
2042 REG_WRITE(ah, AR_STA_ID1, 1355 REG_WRITE(ah, AR_STA_ID1,
@@ -2051,19 +1364,24 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2051 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); 1364 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2052 } 1365 }
2053 1366
1367 if (ah->config.tx_intr_mitigation) {
1368 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1369 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1370 }
1371
2054 ath9k_hw_init_bb(ah, chan); 1372 ath9k_hw_init_bb(ah, chan);
2055 1373
2056 if (!ath9k_hw_init_cal(ah, chan)) 1374 if (!ath9k_hw_init_cal(ah, chan))
2057 return -EIO; 1375 return -EIO;
2058 1376
2059 rx_chainmask = ah->rxchainmask; 1377 ENABLE_REGWRITE_BUFFER(ah);
2060 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2061 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2062 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2063 }
2064 1378
1379 ath9k_hw_restore_chainmask(ah);
2065 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); 1380 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2066 1381
1382 REGWRITE_BUFFER_FLUSH(ah);
1383 DISABLE_REGWRITE_BUFFER(ah);
1384
2067 /* 1385 /*
2068 * For big endian systems turn on swapping for descriptors 1386 * For big endian systems turn on swapping for descriptors
2069 */ 1387 */
@@ -2093,6 +1411,11 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2093 if (ah->btcoex_hw.enabled) 1411 if (ah->btcoex_hw.enabled)
2094 ath9k_hw_btcoex_enable(ah); 1412 ath9k_hw_btcoex_enable(ah);
2095 1413
1414 if (AR_SREV_9300_20_OR_LATER(ah)) {
1415 ath9k_hw_loadnf(ah, curchan);
1416 ath9k_hw_start_nfcal(ah);
1417 }
1418
2096 return 0; 1419 return 0;
2097} 1420}
2098EXPORT_SYMBOL(ath9k_hw_reset); 1421EXPORT_SYMBOL(ath9k_hw_reset);
@@ -2379,21 +1702,35 @@ EXPORT_SYMBOL(ath9k_hw_keyisvalid);
2379/* Power Management (Chipset) */ 1702/* Power Management (Chipset) */
2380/******************************/ 1703/******************************/
2381 1704
1705/*
1706 * Notify Power Mgt is disabled in self-generated frames.
1707 * If requested, force chip to sleep.
1708 */
2382static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip) 1709static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2383{ 1710{
2384 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1711 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2385 if (setChip) { 1712 if (setChip) {
1713 /*
1714 * Clear the RTC force wake bit to allow the
1715 * mac to go to sleep.
1716 */
2386 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, 1717 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2387 AR_RTC_FORCE_WAKE_EN); 1718 AR_RTC_FORCE_WAKE_EN);
2388 if (!AR_SREV_9100(ah)) 1719 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
2389 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 1720 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2390 1721
1722 /* Shutdown chip. Active low */
2391 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) 1723 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
2392 REG_CLR_BIT(ah, (AR_RTC_RESET), 1724 REG_CLR_BIT(ah, (AR_RTC_RESET),
2393 AR_RTC_RESET_EN); 1725 AR_RTC_RESET_EN);
2394 } 1726 }
2395} 1727}
2396 1728
1729/*
1730 * Notify Power Management is enabled in self-generating
1731 * frames. If request, set power mode of chip to
1732 * auto/normal. Duration in units of 128us (1/8 TU).
1733 */
2397static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip) 1734static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2398{ 1735{
2399 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1736 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
@@ -2401,9 +1738,14 @@ static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2401 struct ath9k_hw_capabilities *pCap = &ah->caps; 1738 struct ath9k_hw_capabilities *pCap = &ah->caps;
2402 1739
2403 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1740 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1741 /* Set WakeOnInterrupt bit; clear ForceWake bit */
2404 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1742 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2405 AR_RTC_FORCE_WAKE_ON_INT); 1743 AR_RTC_FORCE_WAKE_ON_INT);
2406 } else { 1744 } else {
1745 /*
1746 * Clear the RTC force wake bit to allow the
1747 * mac to go to sleep.
1748 */
2407 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, 1749 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2408 AR_RTC_FORCE_WAKE_EN); 1750 AR_RTC_FORCE_WAKE_EN);
2409 } 1751 }
@@ -2422,7 +1764,8 @@ static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2422 ATH9K_RESET_POWER_ON) != true) { 1764 ATH9K_RESET_POWER_ON) != true) {
2423 return false; 1765 return false;
2424 } 1766 }
2425 ath9k_hw_init_pll(ah, NULL); 1767 if (!AR_SREV_9300_20_OR_LATER(ah))
1768 ath9k_hw_init_pll(ah, NULL);
2426 } 1769 }
2427 if (AR_SREV_9100(ah)) 1770 if (AR_SREV_9100(ah))
2428 REG_SET_BIT(ah, AR_RTC_RESET, 1771 REG_SET_BIT(ah, AR_RTC_RESET,
@@ -2492,420 +1835,6 @@ bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2492} 1835}
2493EXPORT_SYMBOL(ath9k_hw_setpower); 1836EXPORT_SYMBOL(ath9k_hw_setpower);
2494 1837
2495/*
2496 * Helper for ASPM support.
2497 *
2498 * Disable PLL when in L0s as well as receiver clock when in L1.
2499 * This power saving option must be enabled through the SerDes.
2500 *
2501 * Programming the SerDes must go through the same 288 bit serial shift
2502 * register as the other analog registers. Hence the 9 writes.
2503 */
2504void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
2505{
2506 u8 i;
2507 u32 val;
2508
2509 if (ah->is_pciexpress != true)
2510 return;
2511
2512 /* Do not touch SerDes registers */
2513 if (ah->config.pcie_powersave_enable == 2)
2514 return;
2515
2516 /* Nothing to do on restore for 11N */
2517 if (!restore) {
2518 if (AR_SREV_9280_20_OR_LATER(ah)) {
2519 /*
2520 * AR9280 2.0 or later chips use SerDes values from the
2521 * initvals.h initialized depending on chipset during
2522 * ath9k_hw_init()
2523 */
2524 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2525 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2526 INI_RA(&ah->iniPcieSerdes, i, 1));
2527 }
2528 } else if (AR_SREV_9280(ah) &&
2529 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2530 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2531 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2532
2533 /* RX shut off when elecidle is asserted */
2534 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2535 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2536 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2537
2538 /* Shut off CLKREQ active in L1 */
2539 if (ah->config.pcie_clock_req)
2540 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2541 else
2542 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2543
2544 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2545 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2546 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2547
2548 /* Load the new settings */
2549 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2550
2551 } else {
2552 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2553 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2554
2555 /* RX shut off when elecidle is asserted */
2556 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2557 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2558 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2559
2560 /*
2561 * Ignore ah->ah_config.pcie_clock_req setting for
2562 * pre-AR9280 11n
2563 */
2564 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2565
2566 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2567 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2568 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2569
2570 /* Load the new settings */
2571 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2572 }
2573
2574 udelay(1000);
2575
2576 /* set bit 19 to allow forcing of pcie core into L1 state */
2577 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2578
2579 /* Several PCIe massages to ensure proper behaviour */
2580 if (ah->config.pcie_waen) {
2581 val = ah->config.pcie_waen;
2582 if (!power_off)
2583 val &= (~AR_WA_D3_L1_DISABLE);
2584 } else {
2585 if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2586 AR_SREV_9287(ah)) {
2587 val = AR9285_WA_DEFAULT;
2588 if (!power_off)
2589 val &= (~AR_WA_D3_L1_DISABLE);
2590 } else if (AR_SREV_9280(ah)) {
2591 /*
2592 * On AR9280 chips bit 22 of 0x4004 needs to be
2593 * set otherwise card may disappear.
2594 */
2595 val = AR9280_WA_DEFAULT;
2596 if (!power_off)
2597 val &= (~AR_WA_D3_L1_DISABLE);
2598 } else
2599 val = AR_WA_DEFAULT;
2600 }
2601
2602 REG_WRITE(ah, AR_WA, val);
2603 }
2604
2605 if (power_off) {
2606 /*
2607 * Set PCIe workaround bits
2608 * bit 14 in WA register (disable L1) should only
2609 * be set when device enters D3 and be cleared
2610 * when device comes back to D0.
2611 */
2612 if (ah->config.pcie_waen) {
2613 if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
2614 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2615 } else {
2616 if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2617 AR_SREV_9287(ah)) &&
2618 (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
2619 (AR_SREV_9280(ah) &&
2620 (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
2621 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2622 }
2623 }
2624 }
2625}
2626EXPORT_SYMBOL(ath9k_hw_configpcipowersave);
2627
2628/**********************/
2629/* Interrupt Handling */
2630/**********************/
2631
2632bool ath9k_hw_intrpend(struct ath_hw *ah)
2633{
2634 u32 host_isr;
2635
2636 if (AR_SREV_9100(ah))
2637 return true;
2638
2639 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2640 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2641 return true;
2642
2643 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2644 if ((host_isr & AR_INTR_SYNC_DEFAULT)
2645 && (host_isr != AR_INTR_SPURIOUS))
2646 return true;
2647
2648 return false;
2649}
2650EXPORT_SYMBOL(ath9k_hw_intrpend);
2651
2652bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2653{
2654 u32 isr = 0;
2655 u32 mask2 = 0;
2656 struct ath9k_hw_capabilities *pCap = &ah->caps;
2657 u32 sync_cause = 0;
2658 bool fatal_int = false;
2659 struct ath_common *common = ath9k_hw_common(ah);
2660
2661 if (!AR_SREV_9100(ah)) {
2662 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2663 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2664 == AR_RTC_STATUS_ON) {
2665 isr = REG_READ(ah, AR_ISR);
2666 }
2667 }
2668
2669 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2670 AR_INTR_SYNC_DEFAULT;
2671
2672 *masked = 0;
2673
2674 if (!isr && !sync_cause)
2675 return false;
2676 } else {
2677 *masked = 0;
2678 isr = REG_READ(ah, AR_ISR);
2679 }
2680
2681 if (isr) {
2682 if (isr & AR_ISR_BCNMISC) {
2683 u32 isr2;
2684 isr2 = REG_READ(ah, AR_ISR_S2);
2685 if (isr2 & AR_ISR_S2_TIM)
2686 mask2 |= ATH9K_INT_TIM;
2687 if (isr2 & AR_ISR_S2_DTIM)
2688 mask2 |= ATH9K_INT_DTIM;
2689 if (isr2 & AR_ISR_S2_DTIMSYNC)
2690 mask2 |= ATH9K_INT_DTIMSYNC;
2691 if (isr2 & (AR_ISR_S2_CABEND))
2692 mask2 |= ATH9K_INT_CABEND;
2693 if (isr2 & AR_ISR_S2_GTT)
2694 mask2 |= ATH9K_INT_GTT;
2695 if (isr2 & AR_ISR_S2_CST)
2696 mask2 |= ATH9K_INT_CST;
2697 if (isr2 & AR_ISR_S2_TSFOOR)
2698 mask2 |= ATH9K_INT_TSFOOR;
2699 }
2700
2701 isr = REG_READ(ah, AR_ISR_RAC);
2702 if (isr == 0xffffffff) {
2703 *masked = 0;
2704 return false;
2705 }
2706
2707 *masked = isr & ATH9K_INT_COMMON;
2708
2709 if (ah->config.rx_intr_mitigation) {
2710 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2711 *masked |= ATH9K_INT_RX;
2712 }
2713
2714 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2715 *masked |= ATH9K_INT_RX;
2716 if (isr &
2717 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2718 AR_ISR_TXEOL)) {
2719 u32 s0_s, s1_s;
2720
2721 *masked |= ATH9K_INT_TX;
2722
2723 s0_s = REG_READ(ah, AR_ISR_S0_S);
2724 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2725 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2726
2727 s1_s = REG_READ(ah, AR_ISR_S1_S);
2728 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2729 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2730 }
2731
2732 if (isr & AR_ISR_RXORN) {
2733 ath_print(common, ATH_DBG_INTERRUPT,
2734 "receive FIFO overrun interrupt\n");
2735 }
2736
2737 if (!AR_SREV_9100(ah)) {
2738 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2739 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2740 if (isr5 & AR_ISR_S5_TIM_TIMER)
2741 *masked |= ATH9K_INT_TIM_TIMER;
2742 }
2743 }
2744
2745 *masked |= mask2;
2746 }
2747
2748 if (AR_SREV_9100(ah))
2749 return true;
2750
2751 if (isr & AR_ISR_GENTMR) {
2752 u32 s5_s;
2753
2754 s5_s = REG_READ(ah, AR_ISR_S5_S);
2755 if (isr & AR_ISR_GENTMR) {
2756 ah->intr_gen_timer_trigger =
2757 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
2758
2759 ah->intr_gen_timer_thresh =
2760 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
2761
2762 if (ah->intr_gen_timer_trigger)
2763 *masked |= ATH9K_INT_GENTIMER;
2764
2765 }
2766 }
2767
2768 if (sync_cause) {
2769 fatal_int =
2770 (sync_cause &
2771 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2772 ? true : false;
2773
2774 if (fatal_int) {
2775 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2776 ath_print(common, ATH_DBG_ANY,
2777 "received PCI FATAL interrupt\n");
2778 }
2779 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2780 ath_print(common, ATH_DBG_ANY,
2781 "received PCI PERR interrupt\n");
2782 }
2783 *masked |= ATH9K_INT_FATAL;
2784 }
2785 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2786 ath_print(common, ATH_DBG_INTERRUPT,
2787 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2788 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2789 REG_WRITE(ah, AR_RC, 0);
2790 *masked |= ATH9K_INT_FATAL;
2791 }
2792 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2793 ath_print(common, ATH_DBG_INTERRUPT,
2794 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2795 }
2796
2797 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2798 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2799 }
2800
2801 return true;
2802}
2803EXPORT_SYMBOL(ath9k_hw_getisr);
2804
2805enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
2806{
2807 enum ath9k_int omask = ah->imask;
2808 u32 mask, mask2;
2809 struct ath9k_hw_capabilities *pCap = &ah->caps;
2810 struct ath_common *common = ath9k_hw_common(ah);
2811
2812 ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
2813
2814 if (omask & ATH9K_INT_GLOBAL) {
2815 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
2816 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2817 (void) REG_READ(ah, AR_IER);
2818 if (!AR_SREV_9100(ah)) {
2819 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2820 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2821
2822 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2823 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2824 }
2825 }
2826
2827 mask = ints & ATH9K_INT_COMMON;
2828 mask2 = 0;
2829
2830 if (ints & ATH9K_INT_TX) {
2831 if (ah->txok_interrupt_mask)
2832 mask |= AR_IMR_TXOK;
2833 if (ah->txdesc_interrupt_mask)
2834 mask |= AR_IMR_TXDESC;
2835 if (ah->txerr_interrupt_mask)
2836 mask |= AR_IMR_TXERR;
2837 if (ah->txeol_interrupt_mask)
2838 mask |= AR_IMR_TXEOL;
2839 }
2840 if (ints & ATH9K_INT_RX) {
2841 mask |= AR_IMR_RXERR;
2842 if (ah->config.rx_intr_mitigation)
2843 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2844 else
2845 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
2846 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
2847 mask |= AR_IMR_GENTMR;
2848 }
2849
2850 if (ints & (ATH9K_INT_BMISC)) {
2851 mask |= AR_IMR_BCNMISC;
2852 if (ints & ATH9K_INT_TIM)
2853 mask2 |= AR_IMR_S2_TIM;
2854 if (ints & ATH9K_INT_DTIM)
2855 mask2 |= AR_IMR_S2_DTIM;
2856 if (ints & ATH9K_INT_DTIMSYNC)
2857 mask2 |= AR_IMR_S2_DTIMSYNC;
2858 if (ints & ATH9K_INT_CABEND)
2859 mask2 |= AR_IMR_S2_CABEND;
2860 if (ints & ATH9K_INT_TSFOOR)
2861 mask2 |= AR_IMR_S2_TSFOOR;
2862 }
2863
2864 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
2865 mask |= AR_IMR_BCNMISC;
2866 if (ints & ATH9K_INT_GTT)
2867 mask2 |= AR_IMR_S2_GTT;
2868 if (ints & ATH9K_INT_CST)
2869 mask2 |= AR_IMR_S2_CST;
2870 }
2871
2872 ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
2873 REG_WRITE(ah, AR_IMR, mask);
2874 ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
2875 AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
2876 AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
2877 ah->imrs2_reg |= mask2;
2878 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
2879
2880 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2881 if (ints & ATH9K_INT_TIM_TIMER)
2882 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2883 else
2884 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2885 }
2886
2887 if (ints & ATH9K_INT_GLOBAL) {
2888 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
2889 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
2890 if (!AR_SREV_9100(ah)) {
2891 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
2892 AR_INTR_MAC_IRQ);
2893 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
2894
2895
2896 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
2897 AR_INTR_SYNC_DEFAULT);
2898 REG_WRITE(ah, AR_INTR_SYNC_MASK,
2899 AR_INTR_SYNC_DEFAULT);
2900 }
2901 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
2902 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
2903 }
2904
2905 return omask;
2906}
2907EXPORT_SYMBOL(ath9k_hw_set_interrupts);
2908
2909/*******************/ 1838/*******************/
2910/* Beacon Handling */ 1839/* Beacon Handling */
2911/*******************/ 1840/*******************/
@@ -2916,6 +1845,8 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2916 1845
2917 ah->beacon_interval = beacon_period; 1846 ah->beacon_interval = beacon_period;
2918 1847
1848 ENABLE_REGWRITE_BUFFER(ah);
1849
2919 switch (ah->opmode) { 1850 switch (ah->opmode) {
2920 case NL80211_IFTYPE_STATION: 1851 case NL80211_IFTYPE_STATION:
2921 case NL80211_IFTYPE_MONITOR: 1852 case NL80211_IFTYPE_MONITOR:
@@ -2959,6 +1890,9 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2959 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period)); 1890 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
2960 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period)); 1891 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
2961 1892
1893 REGWRITE_BUFFER_FLUSH(ah);
1894 DISABLE_REGWRITE_BUFFER(ah);
1895
2962 beacon_period &= ~ATH9K_BEACON_ENA; 1896 beacon_period &= ~ATH9K_BEACON_ENA;
2963 if (beacon_period & ATH9K_BEACON_RESET_TSF) { 1897 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
2964 ath9k_hw_reset_tsf(ah); 1898 ath9k_hw_reset_tsf(ah);
@@ -2975,6 +1909,8 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
2975 struct ath9k_hw_capabilities *pCap = &ah->caps; 1909 struct ath9k_hw_capabilities *pCap = &ah->caps;
2976 struct ath_common *common = ath9k_hw_common(ah); 1910 struct ath_common *common = ath9k_hw_common(ah);
2977 1911
1912 ENABLE_REGWRITE_BUFFER(ah);
1913
2978 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); 1914 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
2979 1915
2980 REG_WRITE(ah, AR_BEACON_PERIOD, 1916 REG_WRITE(ah, AR_BEACON_PERIOD,
@@ -2982,6 +1918,9 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
2982 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, 1918 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
2983 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); 1919 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
2984 1920
1921 REGWRITE_BUFFER_FLUSH(ah);
1922 DISABLE_REGWRITE_BUFFER(ah);
1923
2985 REG_RMW_FIELD(ah, AR_RSSI_THR, 1924 REG_RMW_FIELD(ah, AR_RSSI_THR,
2986 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); 1925 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2987 1926
@@ -3004,6 +1943,8 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3004 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval); 1943 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3005 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod); 1944 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3006 1945
1946 ENABLE_REGWRITE_BUFFER(ah);
1947
3007 REG_WRITE(ah, AR_NEXT_DTIM, 1948 REG_WRITE(ah, AR_NEXT_DTIM,
3008 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); 1949 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3009 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP)); 1950 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
@@ -3023,6 +1964,9 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3023 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval)); 1964 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3024 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); 1965 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3025 1966
1967 REGWRITE_BUFFER_FLUSH(ah);
1968 DISABLE_REGWRITE_BUFFER(ah);
1969
3026 REG_SET_BIT(ah, AR_TIMER_MODE, 1970 REG_SET_BIT(ah, AR_TIMER_MODE,
3027 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | 1971 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3028 AR_DTIM_TIMER_EN); 1972 AR_DTIM_TIMER_EN);
@@ -3241,6 +2185,20 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
3241 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE; 2185 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
3242 } 2186 }
3243 2187
2188 if (AR_SREV_9300_20_OR_LATER(ah)) {
2189 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_LDPC;
2190 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2191 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2192 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2193 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2194 pCap->txs_len = sizeof(struct ar9003_txs);
2195 } else {
2196 pCap->tx_desc_len = sizeof(struct ath_desc);
2197 }
2198
2199 if (AR_SREV_9300_20_OR_LATER(ah))
2200 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2201
3244 return 0; 2202 return 0;
3245} 2203}
3246 2204
@@ -3273,10 +2231,6 @@ bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3273 case ATH9K_CAP_TKIP_SPLIT: 2231 case ATH9K_CAP_TKIP_SPLIT:
3274 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ? 2232 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3275 false : true; 2233 false : true;
3276 case ATH9K_CAP_DIVERSITY:
3277 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3278 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3279 true : false;
3280 case ATH9K_CAP_MCAST_KEYSRCH: 2234 case ATH9K_CAP_MCAST_KEYSRCH:
3281 switch (capability) { 2235 switch (capability) {
3282 case 0: 2236 case 0:
@@ -3319,8 +2273,6 @@ EXPORT_SYMBOL(ath9k_hw_getcapability);
3319bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type, 2273bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3320 u32 capability, u32 setting, int *status) 2274 u32 capability, u32 setting, int *status)
3321{ 2275{
3322 u32 v;
3323
3324 switch (type) { 2276 switch (type) {
3325 case ATH9K_CAP_TKIP_MIC: 2277 case ATH9K_CAP_TKIP_MIC:
3326 if (setting) 2278 if (setting)
@@ -3330,14 +2282,6 @@ bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3330 ah->sta_id1_defaults &= 2282 ah->sta_id1_defaults &=
3331 ~AR_STA_ID1_CRPT_MIC_ENABLE; 2283 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3332 return true; 2284 return true;
3333 case ATH9K_CAP_DIVERSITY:
3334 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3335 if (setting)
3336 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3337 else
3338 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3339 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3340 return true;
3341 case ATH9K_CAP_MCAST_KEYSRCH: 2285 case ATH9K_CAP_MCAST_KEYSRCH:
3342 if (setting) 2286 if (setting)
3343 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH; 2287 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
@@ -3405,7 +2349,9 @@ u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3405 if (gpio >= ah->caps.num_gpio_pins) 2349 if (gpio >= ah->caps.num_gpio_pins)
3406 return 0xffffffff; 2350 return 0xffffffff;
3407 2351
3408 if (AR_SREV_9271(ah)) 2352 if (AR_SREV_9300_20_OR_LATER(ah))
2353 return MS_REG_READ(AR9300, gpio) != 0;
2354 else if (AR_SREV_9271(ah))
3409 return MS_REG_READ(AR9271, gpio) != 0; 2355 return MS_REG_READ(AR9271, gpio) != 0;
3410 else if (AR_SREV_9287_10_OR_LATER(ah)) 2356 else if (AR_SREV_9287_10_OR_LATER(ah))
3411 return MS_REG_READ(AR9287, gpio) != 0; 2357 return MS_REG_READ(AR9287, gpio) != 0;
@@ -3478,6 +2424,8 @@ void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3478{ 2424{
3479 u32 phybits; 2425 u32 phybits;
3480 2426
2427 ENABLE_REGWRITE_BUFFER(ah);
2428
3481 REG_WRITE(ah, AR_RX_FILTER, bits); 2429 REG_WRITE(ah, AR_RX_FILTER, bits);
3482 2430
3483 phybits = 0; 2431 phybits = 0;
@@ -3493,6 +2441,9 @@ void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3493 else 2441 else
3494 REG_WRITE(ah, AR_RXCFG, 2442 REG_WRITE(ah, AR_RXCFG,
3495 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA); 2443 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
2444
2445 REGWRITE_BUFFER_FLUSH(ah);
2446 DISABLE_REGWRITE_BUFFER(ah);
3496} 2447}
3497EXPORT_SYMBOL(ath9k_hw_setrxfilter); 2448EXPORT_SYMBOL(ath9k_hw_setrxfilter);
3498 2449
@@ -3565,14 +2516,25 @@ void ath9k_hw_write_associd(struct ath_hw *ah)
3565} 2516}
3566EXPORT_SYMBOL(ath9k_hw_write_associd); 2517EXPORT_SYMBOL(ath9k_hw_write_associd);
3567 2518
2519#define ATH9K_MAX_TSF_READ 10
2520
3568u64 ath9k_hw_gettsf64(struct ath_hw *ah) 2521u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3569{ 2522{
3570 u64 tsf; 2523 u32 tsf_lower, tsf_upper1, tsf_upper2;
2524 int i;
2525
2526 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2527 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2528 tsf_lower = REG_READ(ah, AR_TSF_L32);
2529 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2530 if (tsf_upper2 == tsf_upper1)
2531 break;
2532 tsf_upper1 = tsf_upper2;
2533 }
3571 2534
3572 tsf = REG_READ(ah, AR_TSF_U32); 2535 WARN_ON( i == ATH9K_MAX_TSF_READ );
3573 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3574 2536
3575 return tsf; 2537 return (((u64)tsf_upper1 << 32) | tsf_lower);
3576} 2538}
3577EXPORT_SYMBOL(ath9k_hw_gettsf64); 2539EXPORT_SYMBOL(ath9k_hw_gettsf64);
3578 2540
@@ -3847,6 +2809,7 @@ static struct {
3847 { AR_SREV_VERSION_9285, "9285" }, 2809 { AR_SREV_VERSION_9285, "9285" },
3848 { AR_SREV_VERSION_9287, "9287" }, 2810 { AR_SREV_VERSION_9287, "9287" },
3849 { AR_SREV_VERSION_9271, "9271" }, 2811 { AR_SREV_VERSION_9271, "9271" },
2812 { AR_SREV_VERSION_9300, "9300" },
3850}; 2813};
3851 2814
3852/* For devices with external radios */ 2815/* For devices with external radios */
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-26 05:38:19 -0400