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path: root/drivers/net/phy/microchip.c
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Diffstat (limited to 'drivers/net/phy/microchip.c')
-rw-r--r--drivers/net/phy/microchip.c58
1 files changed, 42 insertions, 16 deletions
diff --git a/drivers/net/phy/microchip.c b/drivers/net/phy/microchip.c
index a97ac8c12c4c..04b12e34da58 100644
--- a/drivers/net/phy/microchip.c
+++ b/drivers/net/phy/microchip.c
@@ -21,6 +21,8 @@
21#include <linux/phy.h> 21#include <linux/phy.h>
22#include <linux/microchipphy.h> 22#include <linux/microchipphy.h>
23#include <linux/delay.h> 23#include <linux/delay.h>
24#include <linux/of.h>
25#include <dt-bindings/net/microchip-lan78xx.h>
24 26
25#define DRIVER_AUTHOR "WOOJUNG HUH <woojung.huh@microchip.com>" 27#define DRIVER_AUTHOR "WOOJUNG HUH <woojung.huh@microchip.com>"
26#define DRIVER_DESC "Microchip LAN88XX PHY driver" 28#define DRIVER_DESC "Microchip LAN88XX PHY driver"
@@ -86,7 +88,7 @@ static int lan88xx_TR_reg_set(struct phy_device *phydev, u16 regaddr,
86 /* Save current page */ 88 /* Save current page */
87 save_page = phy_save_page(phydev); 89 save_page = phy_save_page(phydev);
88 if (save_page < 0) { 90 if (save_page < 0) {
89 pr_warn("Failed to get current page\n"); 91 phydev_warn(phydev, "Failed to get current page\n");
90 goto err; 92 goto err;
91 } 93 }
92 94
@@ -96,14 +98,14 @@ static int lan88xx_TR_reg_set(struct phy_device *phydev, u16 regaddr,
96 ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_LOW_DATA, 98 ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_LOW_DATA,
97 (data & 0xFFFF)); 99 (data & 0xFFFF));
98 if (ret < 0) { 100 if (ret < 0) {
99 pr_warn("Failed to write TR low data\n"); 101 phydev_warn(phydev, "Failed to write TR low data\n");
100 goto err; 102 goto err;
101 } 103 }
102 104
103 ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_HIGH_DATA, 105 ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_HIGH_DATA,
104 (data & 0x00FF0000) >> 16); 106 (data & 0x00FF0000) >> 16);
105 if (ret < 0) { 107 if (ret < 0) {
106 pr_warn("Failed to write TR high data\n"); 108 phydev_warn(phydev, "Failed to write TR high data\n");
107 goto err; 109 goto err;
108 } 110 }
109 111
@@ -113,14 +115,15 @@ static int lan88xx_TR_reg_set(struct phy_device *phydev, u16 regaddr,
113 115
114 ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_CR, buf); 116 ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_CR, buf);
115 if (ret < 0) { 117 if (ret < 0) {
116 pr_warn("Failed to write data in reg\n"); 118 phydev_warn(phydev, "Failed to write data in reg\n");
117 goto err; 119 goto err;
118 } 120 }
119 121
120 usleep_range(1000, 2000);/* Wait for Data to be written */ 122 usleep_range(1000, 2000);/* Wait for Data to be written */
121 val = __phy_read(phydev, LAN88XX_EXT_PAGE_TR_CR); 123 val = __phy_read(phydev, LAN88XX_EXT_PAGE_TR_CR);
122 if (!(val & 0x8000)) 124 if (!(val & 0x8000))
123 pr_warn("TR Register[0x%X] configuration failed\n", regaddr); 125 phydev_warn(phydev, "TR Register[0x%X] configuration failed\n",
126 regaddr);
124err: 127err:
125 return phy_restore_page(phydev, save_page, ret); 128 return phy_restore_page(phydev, save_page, ret);
126} 129}
@@ -135,7 +138,7 @@ static void lan88xx_config_TR_regs(struct phy_device *phydev)
135 */ 138 */
136 err = lan88xx_TR_reg_set(phydev, 0x0F82, 0x12B00A); 139 err = lan88xx_TR_reg_set(phydev, 0x0F82, 0x12B00A);
137 if (err < 0) 140 if (err < 0)
138 pr_warn("Failed to Set Register[0x0F82]\n"); 141 phydev_warn(phydev, "Failed to Set Register[0x0F82]\n");
139 142
140 /* Get access to Channel b'10, Node b'1101, Register 0x06. 143 /* Get access to Channel b'10, Node b'1101, Register 0x06.
141 * Write 24-bit value 0xD2C46F to register. Setting SSTrKf1000Slv, 144 * Write 24-bit value 0xD2C46F to register. Setting SSTrKf1000Slv,
@@ -143,7 +146,7 @@ static void lan88xx_config_TR_regs(struct phy_device *phydev)
143 */ 146 */
144 err = lan88xx_TR_reg_set(phydev, 0x168C, 0xD2C46F); 147 err = lan88xx_TR_reg_set(phydev, 0x168C, 0xD2C46F);
145 if (err < 0) 148 if (err < 0)
146 pr_warn("Failed to Set Register[0x168C]\n"); 149 phydev_warn(phydev, "Failed to Set Register[0x168C]\n");
147 150
148 /* Get access to Channel b'10, Node b'1111, Register 0x11. 151 /* Get access to Channel b'10, Node b'1111, Register 0x11.
149 * Write 24-bit value 0x620 to register. Setting rem_upd_done_thresh 152 * Write 24-bit value 0x620 to register. Setting rem_upd_done_thresh
@@ -151,7 +154,7 @@ static void lan88xx_config_TR_regs(struct phy_device *phydev)
151 */ 154 */
152 err = lan88xx_TR_reg_set(phydev, 0x17A2, 0x620); 155 err = lan88xx_TR_reg_set(phydev, 0x17A2, 0x620);
153 if (err < 0) 156 if (err < 0)
154 pr_warn("Failed to Set Register[0x17A2]\n"); 157 phydev_warn(phydev, "Failed to Set Register[0x17A2]\n");
155 158
156 /* Get access to Channel b'10, Node b'1101, Register 0x10. 159 /* Get access to Channel b'10, Node b'1101, Register 0x10.
157 * Write 24-bit value 0xEEFFDD to register. Setting 160 * Write 24-bit value 0xEEFFDD to register. Setting
@@ -160,7 +163,7 @@ static void lan88xx_config_TR_regs(struct phy_device *phydev)
160 */ 163 */
161 err = lan88xx_TR_reg_set(phydev, 0x16A0, 0xEEFFDD); 164 err = lan88xx_TR_reg_set(phydev, 0x16A0, 0xEEFFDD);
162 if (err < 0) 165 if (err < 0)
163 pr_warn("Failed to Set Register[0x16A0]\n"); 166 phydev_warn(phydev, "Failed to Set Register[0x16A0]\n");
164 167
165 /* Get access to Channel b'10, Node b'1101, Register 0x13. 168 /* Get access to Channel b'10, Node b'1101, Register 0x13.
166 * Write 24-bit value 0x071448 to register. Setting 169 * Write 24-bit value 0x071448 to register. Setting
@@ -168,7 +171,7 @@ static void lan88xx_config_TR_regs(struct phy_device *phydev)
168 */ 171 */
169 err = lan88xx_TR_reg_set(phydev, 0x16A6, 0x071448); 172 err = lan88xx_TR_reg_set(phydev, 0x16A6, 0x071448);
170 if (err < 0) 173 if (err < 0)
171 pr_warn("Failed to Set Register[0x16A6]\n"); 174 phydev_warn(phydev, "Failed to Set Register[0x16A6]\n");
172 175
173 /* Get access to Channel b'10, Node b'1101, Register 0x12. 176 /* Get access to Channel b'10, Node b'1101, Register 0x12.
174 * Write 24-bit value 0x13132F to register. Setting 177 * Write 24-bit value 0x13132F to register. Setting
@@ -176,7 +179,7 @@ static void lan88xx_config_TR_regs(struct phy_device *phydev)
176 */ 179 */
177 err = lan88xx_TR_reg_set(phydev, 0x16A4, 0x13132F); 180 err = lan88xx_TR_reg_set(phydev, 0x16A4, 0x13132F);
178 if (err < 0) 181 if (err < 0)
179 pr_warn("Failed to Set Register[0x16A4]\n"); 182 phydev_warn(phydev, "Failed to Set Register[0x16A4]\n");
180 183
181 /* Get access to Channel b'10, Node b'1101, Register 0x14. 184 /* Get access to Channel b'10, Node b'1101, Register 0x14.
182 * Write 24-bit value 0x0 to register. Setting eee_3level_delay, 185 * Write 24-bit value 0x0 to register. Setting eee_3level_delay,
@@ -184,7 +187,7 @@ static void lan88xx_config_TR_regs(struct phy_device *phydev)
184 */ 187 */
185 err = lan88xx_TR_reg_set(phydev, 0x16A8, 0x0); 188 err = lan88xx_TR_reg_set(phydev, 0x16A8, 0x0);
186 if (err < 0) 189 if (err < 0)
187 pr_warn("Failed to Set Register[0x16A8]\n"); 190 phydev_warn(phydev, "Failed to Set Register[0x16A8]\n");
188 191
189 /* Get access to Channel b'01, Node b'1111, Register 0x34. 192 /* Get access to Channel b'01, Node b'1111, Register 0x34.
190 * Write 24-bit value 0x91B06C to register. Setting 193 * Write 24-bit value 0x91B06C to register. Setting
@@ -193,7 +196,7 @@ static void lan88xx_config_TR_regs(struct phy_device *phydev)
193 */ 196 */
194 err = lan88xx_TR_reg_set(phydev, 0x0FE8, 0x91B06C); 197 err = lan88xx_TR_reg_set(phydev, 0x0FE8, 0x91B06C);
195 if (err < 0) 198 if (err < 0)
196 pr_warn("Failed to Set Register[0x0FE8]\n"); 199 phydev_warn(phydev, "Failed to Set Register[0x0FE8]\n");
197 200
198 /* Get access to Channel b'01, Node b'1111, Register 0x3E. 201 /* Get access to Channel b'01, Node b'1111, Register 0x3E.
199 * Write 24-bit value 0xC0A028 to register. Setting 202 * Write 24-bit value 0xC0A028 to register. Setting
@@ -202,7 +205,7 @@ static void lan88xx_config_TR_regs(struct phy_device *phydev)
202 */ 205 */
203 err = lan88xx_TR_reg_set(phydev, 0x0FFC, 0xC0A028); 206 err = lan88xx_TR_reg_set(phydev, 0x0FFC, 0xC0A028);
204 if (err < 0) 207 if (err < 0)
205 pr_warn("Failed to Set Register[0x0FFC]\n"); 208 phydev_warn(phydev, "Failed to Set Register[0x0FFC]\n");
206 209
207 /* Get access to Channel b'01, Node b'1111, Register 0x35. 210 /* Get access to Channel b'01, Node b'1111, Register 0x35.
208 * Write 24-bit value 0x041600 to register. Setting 211 * Write 24-bit value 0x041600 to register. Setting
@@ -211,20 +214,22 @@ static void lan88xx_config_TR_regs(struct phy_device *phydev)
211 */ 214 */
212 err = lan88xx_TR_reg_set(phydev, 0x0FEA, 0x041600); 215 err = lan88xx_TR_reg_set(phydev, 0x0FEA, 0x041600);
213 if (err < 0) 216 if (err < 0)
214 pr_warn("Failed to Set Register[0x0FEA]\n"); 217 phydev_warn(phydev, "Failed to Set Register[0x0FEA]\n");
215 218
216 /* Get access to Channel b'10, Node b'1101, Register 0x03. 219 /* Get access to Channel b'10, Node b'1101, Register 0x03.
217 * Write 24-bit value 0x000004 to register. Setting TrFreeze bits. 220 * Write 24-bit value 0x000004 to register. Setting TrFreeze bits.
218 */ 221 */
219 err = lan88xx_TR_reg_set(phydev, 0x1686, 0x000004); 222 err = lan88xx_TR_reg_set(phydev, 0x1686, 0x000004);
220 if (err < 0) 223 if (err < 0)
221 pr_warn("Failed to Set Register[0x1686]\n"); 224 phydev_warn(phydev, "Failed to Set Register[0x1686]\n");
222} 225}
223 226
224static int lan88xx_probe(struct phy_device *phydev) 227static int lan88xx_probe(struct phy_device *phydev)
225{ 228{
226 struct device *dev = &phydev->mdio.dev; 229 struct device *dev = &phydev->mdio.dev;
227 struct lan88xx_priv *priv; 230 struct lan88xx_priv *priv;
231 u32 led_modes[4];
232 int len;
228 233
229 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 234 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
230 if (!priv) 235 if (!priv)
@@ -232,6 +237,27 @@ static int lan88xx_probe(struct phy_device *phydev)
232 237
233 priv->wolopts = 0; 238 priv->wolopts = 0;
234 239
240 len = of_property_read_variable_u32_array(dev->of_node,
241 "microchip,led-modes",
242 led_modes,
243 0,
244 ARRAY_SIZE(led_modes));
245 if (len >= 0) {
246 u32 reg = 0;
247 int i;
248
249 for (i = 0; i < len; i++) {
250 if (led_modes[i] > 15)
251 return -EINVAL;
252 reg |= led_modes[i] << (i * 4);
253 }
254 for (; i < ARRAY_SIZE(led_modes); i++)
255 reg |= LAN78XX_FORCE_LED_OFF << (i * 4);
256 (void)phy_write(phydev, LAN78XX_PHY_LED_MODE_SELECT, reg);
257 } else if (len == -EOVERFLOW) {
258 return -EINVAL;
259 }
260
235 /* these values can be used to identify internal PHY */ 261 /* these values can be used to identify internal PHY */
236 priv->chip_id = phy_read_mmd(phydev, 3, LAN88XX_MMD3_CHIP_ID); 262 priv->chip_id = phy_read_mmd(phydev, 3, LAN88XX_MMD3_CHIP_ID);
237 priv->chip_rev = phy_read_mmd(phydev, 3, LAN88XX_MMD3_CHIP_REV); 263 priv->chip_rev = phy_read_mmd(phydev, 3, LAN88XX_MMD3_CHIP_REV);