diff options
Diffstat (limited to 'drivers/net/ixgb/ixgb_ee.c')
-rw-r--r-- | drivers/net/ixgb/ixgb_ee.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/net/ixgb/ixgb_ee.c b/drivers/net/ixgb/ixgb_ee.c index c982ab9f9005..38b362b67857 100644 --- a/drivers/net/ixgb/ixgb_ee.c +++ b/drivers/net/ixgb/ixgb_ee.c | |||
@@ -57,6 +57,7 @@ ixgb_raise_clock(struct ixgb_hw *hw, | |||
57 | */ | 57 | */ |
58 | *eecd_reg = *eecd_reg | IXGB_EECD_SK; | 58 | *eecd_reg = *eecd_reg | IXGB_EECD_SK; |
59 | IXGB_WRITE_REG(hw, EECD, *eecd_reg); | 59 | IXGB_WRITE_REG(hw, EECD, *eecd_reg); |
60 | IXGB_WRITE_FLUSH(hw); | ||
60 | udelay(50); | 61 | udelay(50); |
61 | } | 62 | } |
62 | 63 | ||
@@ -75,6 +76,7 @@ ixgb_lower_clock(struct ixgb_hw *hw, | |||
75 | */ | 76 | */ |
76 | *eecd_reg = *eecd_reg & ~IXGB_EECD_SK; | 77 | *eecd_reg = *eecd_reg & ~IXGB_EECD_SK; |
77 | IXGB_WRITE_REG(hw, EECD, *eecd_reg); | 78 | IXGB_WRITE_REG(hw, EECD, *eecd_reg); |
79 | IXGB_WRITE_FLUSH(hw); | ||
78 | udelay(50); | 80 | udelay(50); |
79 | } | 81 | } |
80 | 82 | ||
@@ -112,6 +114,7 @@ ixgb_shift_out_bits(struct ixgb_hw *hw, | |||
112 | eecd_reg |= IXGB_EECD_DI; | 114 | eecd_reg |= IXGB_EECD_DI; |
113 | 115 | ||
114 | IXGB_WRITE_REG(hw, EECD, eecd_reg); | 116 | IXGB_WRITE_REG(hw, EECD, eecd_reg); |
117 | IXGB_WRITE_FLUSH(hw); | ||
115 | 118 | ||
116 | udelay(50); | 119 | udelay(50); |
117 | 120 | ||
@@ -206,21 +209,25 @@ ixgb_standby_eeprom(struct ixgb_hw *hw) | |||
206 | /* Deselect EEPROM */ | 209 | /* Deselect EEPROM */ |
207 | eecd_reg &= ~(IXGB_EECD_CS | IXGB_EECD_SK); | 210 | eecd_reg &= ~(IXGB_EECD_CS | IXGB_EECD_SK); |
208 | IXGB_WRITE_REG(hw, EECD, eecd_reg); | 211 | IXGB_WRITE_REG(hw, EECD, eecd_reg); |
212 | IXGB_WRITE_FLUSH(hw); | ||
209 | udelay(50); | 213 | udelay(50); |
210 | 214 | ||
211 | /* Clock high */ | 215 | /* Clock high */ |
212 | eecd_reg |= IXGB_EECD_SK; | 216 | eecd_reg |= IXGB_EECD_SK; |
213 | IXGB_WRITE_REG(hw, EECD, eecd_reg); | 217 | IXGB_WRITE_REG(hw, EECD, eecd_reg); |
218 | IXGB_WRITE_FLUSH(hw); | ||
214 | udelay(50); | 219 | udelay(50); |
215 | 220 | ||
216 | /* Select EEPROM */ | 221 | /* Select EEPROM */ |
217 | eecd_reg |= IXGB_EECD_CS; | 222 | eecd_reg |= IXGB_EECD_CS; |
218 | IXGB_WRITE_REG(hw, EECD, eecd_reg); | 223 | IXGB_WRITE_REG(hw, EECD, eecd_reg); |
224 | IXGB_WRITE_FLUSH(hw); | ||
219 | udelay(50); | 225 | udelay(50); |
220 | 226 | ||
221 | /* Clock low */ | 227 | /* Clock low */ |
222 | eecd_reg &= ~IXGB_EECD_SK; | 228 | eecd_reg &= ~IXGB_EECD_SK; |
223 | IXGB_WRITE_REG(hw, EECD, eecd_reg); | 229 | IXGB_WRITE_REG(hw, EECD, eecd_reg); |
230 | IXGB_WRITE_FLUSH(hw); | ||
224 | udelay(50); | 231 | udelay(50); |
225 | } | 232 | } |
226 | 233 | ||
@@ -239,11 +246,13 @@ ixgb_clock_eeprom(struct ixgb_hw *hw) | |||
239 | /* Rising edge of clock */ | 246 | /* Rising edge of clock */ |
240 | eecd_reg |= IXGB_EECD_SK; | 247 | eecd_reg |= IXGB_EECD_SK; |
241 | IXGB_WRITE_REG(hw, EECD, eecd_reg); | 248 | IXGB_WRITE_REG(hw, EECD, eecd_reg); |
249 | IXGB_WRITE_FLUSH(hw); | ||
242 | udelay(50); | 250 | udelay(50); |
243 | 251 | ||
244 | /* Falling edge of clock */ | 252 | /* Falling edge of clock */ |
245 | eecd_reg &= ~IXGB_EECD_SK; | 253 | eecd_reg &= ~IXGB_EECD_SK; |
246 | IXGB_WRITE_REG(hw, EECD, eecd_reg); | 254 | IXGB_WRITE_REG(hw, EECD, eecd_reg); |
255 | IXGB_WRITE_FLUSH(hw); | ||
247 | udelay(50); | 256 | udelay(50); |
248 | } | 257 | } |
249 | 258 | ||