diff options
Diffstat (limited to 'drivers/net/ethernet/mellanox/mlx4/main.c')
-rw-r--r-- | drivers/net/ethernet/mellanox/mlx4/main.c | 160 |
1 files changed, 129 insertions, 31 deletions
diff --git a/drivers/net/ethernet/mellanox/mlx4/main.c b/drivers/net/ethernet/mellanox/mlx4/main.c index 2aa80afd98d2..e1bafffbc3b1 100644 --- a/drivers/net/ethernet/mellanox/mlx4/main.c +++ b/drivers/net/ethernet/mellanox/mlx4/main.c | |||
@@ -85,20 +85,26 @@ static int probe_vf; | |||
85 | module_param(probe_vf, int, 0644); | 85 | module_param(probe_vf, int, 0644); |
86 | MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)"); | 86 | MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)"); |
87 | 87 | ||
88 | int mlx4_log_num_mgm_entry_size = 10; | 88 | int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE; |
89 | module_param_named(log_num_mgm_entry_size, | 89 | module_param_named(log_num_mgm_entry_size, |
90 | mlx4_log_num_mgm_entry_size, int, 0444); | 90 | mlx4_log_num_mgm_entry_size, int, 0444); |
91 | MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num" | 91 | MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num" |
92 | " of qp per mcg, for example:" | 92 | " of qp per mcg, for example:" |
93 | " 10 gives 248.range: 9<=" | 93 | " 10 gives 248.range: 7 <=" |
94 | " log_num_mgm_entry_size <= 12." | 94 | " log_num_mgm_entry_size <= 12." |
95 | " Not in use with device managed" | 95 | " To activate device managed" |
96 | " flow steering"); | 96 | " flow steering when available, set to -1"); |
97 | |||
98 | static bool enable_64b_cqe_eqe; | ||
99 | module_param(enable_64b_cqe_eqe, bool, 0444); | ||
100 | MODULE_PARM_DESC(enable_64b_cqe_eqe, | ||
101 | "Enable 64 byte CQEs/EQEs when the the FW supports this"); | ||
97 | 102 | ||
98 | #define HCA_GLOBAL_CAP_MASK 0 | 103 | #define HCA_GLOBAL_CAP_MASK 0 |
99 | #define PF_CONTEXT_BEHAVIOUR_MASK 0 | ||
100 | 104 | ||
101 | static char mlx4_version[] __devinitdata = | 105 | #define PF_CONTEXT_BEHAVIOUR_MASK MLX4_FUNC_CAP_64B_EQE_CQE |
106 | |||
107 | static char mlx4_version[] = | ||
102 | DRV_NAME ": Mellanox ConnectX core driver v" | 108 | DRV_NAME ": Mellanox ConnectX core driver v" |
103 | DRV_VERSION " (" DRV_RELDATE ")\n"; | 109 | DRV_VERSION " (" DRV_RELDATE ")\n"; |
104 | 110 | ||
@@ -275,28 +281,6 @@ static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) | |||
275 | dev->caps.max_gso_sz = dev_cap->max_gso_sz; | 281 | dev->caps.max_gso_sz = dev_cap->max_gso_sz; |
276 | dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz; | 282 | dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz; |
277 | 283 | ||
278 | if (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) { | ||
279 | dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED; | ||
280 | dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry; | ||
281 | dev->caps.fs_log_max_ucast_qp_range_size = | ||
282 | dev_cap->fs_log_max_ucast_qp_range_size; | ||
283 | } else { | ||
284 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER && | ||
285 | dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) { | ||
286 | dev->caps.steering_mode = MLX4_STEERING_MODE_B0; | ||
287 | } else { | ||
288 | dev->caps.steering_mode = MLX4_STEERING_MODE_A0; | ||
289 | |||
290 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER || | ||
291 | dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) | ||
292 | mlx4_warn(dev, "Must have UC_STEER and MC_STEER flags " | ||
293 | "set to use B0 steering. Falling back to A0 steering mode.\n"); | ||
294 | } | ||
295 | dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev); | ||
296 | } | ||
297 | mlx4_dbg(dev, "Steering mode is: %s\n", | ||
298 | mlx4_steering_mode_str(dev->caps.steering_mode)); | ||
299 | |||
300 | /* Sense port always allowed on supported devices for ConnectX-1 and -2 */ | 284 | /* Sense port always allowed on supported devices for ConnectX-1 and -2 */ |
301 | if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT) | 285 | if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT) |
302 | dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; | 286 | dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; |
@@ -386,6 +370,21 @@ static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) | |||
386 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH]; | 370 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH]; |
387 | 371 | ||
388 | dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0; | 372 | dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0; |
373 | |||
374 | if (!enable_64b_cqe_eqe) { | ||
375 | if (dev_cap->flags & | ||
376 | (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) { | ||
377 | mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n"); | ||
378 | dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE; | ||
379 | dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE; | ||
380 | } | ||
381 | } | ||
382 | |||
383 | if ((dev_cap->flags & | ||
384 | (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) && | ||
385 | mlx4_is_master(dev)) | ||
386 | dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE; | ||
387 | |||
389 | return 0; | 388 | return 0; |
390 | } | 389 | } |
391 | /*The function checks if there are live vf, return the num of them*/ | 390 | /*The function checks if there are live vf, return the num of them*/ |
@@ -472,6 +471,23 @@ int mlx4_is_slave_active(struct mlx4_dev *dev, int slave) | |||
472 | } | 471 | } |
473 | EXPORT_SYMBOL(mlx4_is_slave_active); | 472 | EXPORT_SYMBOL(mlx4_is_slave_active); |
474 | 473 | ||
474 | static void slave_adjust_steering_mode(struct mlx4_dev *dev, | ||
475 | struct mlx4_dev_cap *dev_cap, | ||
476 | struct mlx4_init_hca_param *hca_param) | ||
477 | { | ||
478 | dev->caps.steering_mode = hca_param->steering_mode; | ||
479 | if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) { | ||
480 | dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry; | ||
481 | dev->caps.fs_log_max_ucast_qp_range_size = | ||
482 | dev_cap->fs_log_max_ucast_qp_range_size; | ||
483 | } else | ||
484 | dev->caps.num_qp_per_mgm = | ||
485 | 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2); | ||
486 | |||
487 | mlx4_dbg(dev, "Steering mode is: %s\n", | ||
488 | mlx4_steering_mode_str(dev->caps.steering_mode)); | ||
489 | } | ||
490 | |||
475 | static int mlx4_slave_cap(struct mlx4_dev *dev) | 491 | static int mlx4_slave_cap(struct mlx4_dev *dev) |
476 | { | 492 | { |
477 | int err; | 493 | int err; |
@@ -599,6 +615,23 @@ static int mlx4_slave_cap(struct mlx4_dev *dev) | |||
599 | goto err_mem; | 615 | goto err_mem; |
600 | } | 616 | } |
601 | 617 | ||
618 | if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) { | ||
619 | dev->caps.eqe_size = 64; | ||
620 | dev->caps.eqe_factor = 1; | ||
621 | } else { | ||
622 | dev->caps.eqe_size = 32; | ||
623 | dev->caps.eqe_factor = 0; | ||
624 | } | ||
625 | |||
626 | if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) { | ||
627 | dev->caps.cqe_size = 64; | ||
628 | dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_64B_CQE; | ||
629 | } else { | ||
630 | dev->caps.cqe_size = 32; | ||
631 | } | ||
632 | |||
633 | slave_adjust_steering_mode(dev, &dev_cap, &hca_param); | ||
634 | |||
602 | return 0; | 635 | return 0; |
603 | 636 | ||
604 | err_mem: | 637 | err_mem: |
@@ -1285,6 +1318,59 @@ static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev) | |||
1285 | } | 1318 | } |
1286 | } | 1319 | } |
1287 | 1320 | ||
1321 | static int choose_log_fs_mgm_entry_size(int qp_per_entry) | ||
1322 | { | ||
1323 | int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; | ||
1324 | |||
1325 | for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE; | ||
1326 | i++) { | ||
1327 | if (qp_per_entry <= 4 * ((1 << i) / 16 - 2)) | ||
1328 | break; | ||
1329 | } | ||
1330 | |||
1331 | return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1; | ||
1332 | } | ||
1333 | |||
1334 | static void choose_steering_mode(struct mlx4_dev *dev, | ||
1335 | struct mlx4_dev_cap *dev_cap) | ||
1336 | { | ||
1337 | if (mlx4_log_num_mgm_entry_size == -1 && | ||
1338 | dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN && | ||
1339 | (!mlx4_is_mfunc(dev) || | ||
1340 | (dev_cap->fs_max_num_qp_per_entry >= (num_vfs + 1))) && | ||
1341 | choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >= | ||
1342 | MLX4_MIN_MGM_LOG_ENTRY_SIZE) { | ||
1343 | dev->oper_log_mgm_entry_size = | ||
1344 | choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry); | ||
1345 | dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED; | ||
1346 | dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry; | ||
1347 | dev->caps.fs_log_max_ucast_qp_range_size = | ||
1348 | dev_cap->fs_log_max_ucast_qp_range_size; | ||
1349 | } else { | ||
1350 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER && | ||
1351 | dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) | ||
1352 | dev->caps.steering_mode = MLX4_STEERING_MODE_B0; | ||
1353 | else { | ||
1354 | dev->caps.steering_mode = MLX4_STEERING_MODE_A0; | ||
1355 | |||
1356 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER || | ||
1357 | dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) | ||
1358 | mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags " | ||
1359 | "set to use B0 steering. Falling back to A0 steering mode.\n"); | ||
1360 | } | ||
1361 | dev->oper_log_mgm_entry_size = | ||
1362 | mlx4_log_num_mgm_entry_size > 0 ? | ||
1363 | mlx4_log_num_mgm_entry_size : | ||
1364 | MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE; | ||
1365 | dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev); | ||
1366 | } | ||
1367 | mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, " | ||
1368 | "modparam log_num_mgm_entry_size = %d\n", | ||
1369 | mlx4_steering_mode_str(dev->caps.steering_mode), | ||
1370 | dev->oper_log_mgm_entry_size, | ||
1371 | mlx4_log_num_mgm_entry_size); | ||
1372 | } | ||
1373 | |||
1288 | static int mlx4_init_hca(struct mlx4_dev *dev) | 1374 | static int mlx4_init_hca(struct mlx4_dev *dev) |
1289 | { | 1375 | { |
1290 | struct mlx4_priv *priv = mlx4_priv(dev); | 1376 | struct mlx4_priv *priv = mlx4_priv(dev); |
@@ -1324,6 +1410,8 @@ static int mlx4_init_hca(struct mlx4_dev *dev) | |||
1324 | goto err_stop_fw; | 1410 | goto err_stop_fw; |
1325 | } | 1411 | } |
1326 | 1412 | ||
1413 | choose_steering_mode(dev, &dev_cap); | ||
1414 | |||
1327 | if (mlx4_is_master(dev)) | 1415 | if (mlx4_is_master(dev)) |
1328 | mlx4_parav_master_pf_caps(dev); | 1416 | mlx4_parav_master_pf_caps(dev); |
1329 | 1417 | ||
@@ -2224,8 +2312,7 @@ err_disable_pdev: | |||
2224 | return err; | 2312 | return err; |
2225 | } | 2313 | } |
2226 | 2314 | ||
2227 | static int __devinit mlx4_init_one(struct pci_dev *pdev, | 2315 | static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id) |
2228 | const struct pci_device_id *id) | ||
2229 | { | 2316 | { |
2230 | printk_once(KERN_INFO "%s", mlx4_version); | 2317 | printk_once(KERN_INFO "%s", mlx4_version); |
2231 | 2318 | ||
@@ -2391,7 +2478,7 @@ static struct pci_driver mlx4_driver = { | |||
2391 | .name = DRV_NAME, | 2478 | .name = DRV_NAME, |
2392 | .id_table = mlx4_pci_table, | 2479 | .id_table = mlx4_pci_table, |
2393 | .probe = mlx4_init_one, | 2480 | .probe = mlx4_init_one, |
2394 | .remove = __devexit_p(mlx4_remove_one), | 2481 | .remove = mlx4_remove_one, |
2395 | .err_handler = &mlx4_err_handler, | 2482 | .err_handler = &mlx4_err_handler, |
2396 | }; | 2483 | }; |
2397 | 2484 | ||
@@ -2417,6 +2504,17 @@ static int __init mlx4_verify_params(void) | |||
2417 | port_type_array[0] = true; | 2504 | port_type_array[0] = true; |
2418 | } | 2505 | } |
2419 | 2506 | ||
2507 | if (mlx4_log_num_mgm_entry_size != -1 && | ||
2508 | (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE || | ||
2509 | mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE)) { | ||
2510 | pr_warning("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not " | ||
2511 | "in legal range (-1 or %d..%d)\n", | ||
2512 | mlx4_log_num_mgm_entry_size, | ||
2513 | MLX4_MIN_MGM_LOG_ENTRY_SIZE, | ||
2514 | MLX4_MAX_MGM_LOG_ENTRY_SIZE); | ||
2515 | return -1; | ||
2516 | } | ||
2517 | |||
2420 | return 0; | 2518 | return 0; |
2421 | } | 2519 | } |
2422 | 2520 | ||