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path: root/drivers/net/ethernet/mellanox/mlx4/fw.c
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Diffstat (limited to 'drivers/net/ethernet/mellanox/mlx4/fw.c')
-rw-r--r--drivers/net/ethernet/mellanox/mlx4/fw.c17
1 files changed, 16 insertions, 1 deletions
diff --git a/drivers/net/ethernet/mellanox/mlx4/fw.c b/drivers/net/ethernet/mellanox/mlx4/fw.c
index de6b3d416148..babcfd9c0571 100644
--- a/drivers/net/ethernet/mellanox/mlx4/fw.c
+++ b/drivers/net/ethernet/mellanox/mlx4/fw.c
@@ -165,6 +165,7 @@ static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags)
165 [36] = "QinQ VST mode support", 165 [36] = "QinQ VST mode support",
166 [37] = "sl to vl mapping table change event support", 166 [37] = "sl to vl mapping table change event support",
167 [38] = "user MAC support", 167 [38] = "user MAC support",
168 [39] = "Report driver version to FW support",
168 }; 169 };
169 int i; 170 int i;
170 171
@@ -824,7 +825,7 @@ int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
824#define QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET 0xcc 825#define QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET 0xcc
825#define QUERY_DEV_CAP_QP_RATE_LIMIT_MAX_OFFSET 0xd0 826#define QUERY_DEV_CAP_QP_RATE_LIMIT_MAX_OFFSET 0xd0
826#define QUERY_DEV_CAP_QP_RATE_LIMIT_MIN_OFFSET 0xd2 827#define QUERY_DEV_CAP_QP_RATE_LIMIT_MIN_OFFSET 0xd2
827 828#define QUERY_DEV_CAP_HEALTH_BUFFER_ADDRESS_OFFSET 0xe4
828 829
829 dev_cap->flags2 = 0; 830 dev_cap->flags2 = 0;
830 mailbox = mlx4_alloc_cmd_mailbox(dev); 831 mailbox = mlx4_alloc_cmd_mailbox(dev);
@@ -1038,6 +1039,8 @@ int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
1038 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP; 1039 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP;
1039 if (field32 & (1 << 7)) 1040 if (field32 & (1 << 7))
1040 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT; 1041 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT;
1042 if (field32 & (1 << 8))
1043 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DRIVER_VERSION_TO_FW;
1041 MLX4_GET(field32, outbox, QUERY_DEV_CAP_DIAG_RPRT_PER_PORT); 1044 MLX4_GET(field32, outbox, QUERY_DEV_CAP_DIAG_RPRT_PER_PORT);
1042 if (field32 & (1 << 17)) 1045 if (field32 & (1 << 17))
1043 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT; 1046 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT;
@@ -1079,6 +1082,9 @@ int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
1079 dev_cap->rl_caps.min_unit = size >> 14; 1082 dev_cap->rl_caps.min_unit = size >> 14;
1080 } 1083 }
1081 1084
1085 MLX4_GET(dev_cap->health_buffer_addrs, outbox,
1086 QUERY_DEV_CAP_HEALTH_BUFFER_ADDRESS_OFFSET);
1087
1082 MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); 1088 MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
1083 if (field32 & (1 << 16)) 1089 if (field32 & (1 << 16))
1084 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP; 1090 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP;
@@ -1860,6 +1866,8 @@ int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
1860#define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18) 1866#define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18)
1861#define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b) 1867#define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
1862#define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6 1868#define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6
1869#define INIT_HCA_DRIVER_VERSION_OFFSET 0x140
1870#define INIT_HCA_DRIVER_VERSION_SZ 0x40
1863#define INIT_HCA_FS_PARAM_OFFSET 0x1d0 1871#define INIT_HCA_FS_PARAM_OFFSET 0x1d0
1864#define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00) 1872#define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00)
1865#define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12) 1873#define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12)
@@ -1950,6 +1958,13 @@ int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
1950 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT) 1958 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT)
1951 *(inbox + INIT_HCA_RECOVERABLE_ERROR_EVENT_OFFSET / 4) |= cpu_to_be32(1 << 31); 1959 *(inbox + INIT_HCA_RECOVERABLE_ERROR_EVENT_OFFSET / 4) |= cpu_to_be32(1 << 31);
1952 1960
1961 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DRIVER_VERSION_TO_FW) {
1962 u8 *dst = (u8 *)(inbox + INIT_HCA_DRIVER_VERSION_OFFSET / 4);
1963
1964 strncpy(dst, DRV_NAME_FOR_FW, INIT_HCA_DRIVER_VERSION_SZ - 1);
1965 mlx4_dbg(dev, "Reporting Driver Version to FW: %s\n", dst);
1966 }
1967
1953 /* QPC/EEC/CQC/EQC/RDMARC attributes */ 1968 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1954 1969
1955 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET); 1970 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);