1 files changed, 45 insertions, 0 deletions

diff --git a/drivers/net/ethernet/intel/igc/igc_defines.h b/drivers/net/ethernet/intel/igc/igc_defines.h
index dbc30dead461..c8a321358cf6 100644
--- a/drivers/net/ethernet/intel/igc/igc_defines.h
+++ b/drivers/net/ethernet/intel/igc/igc_defines.h
@@ -84,6 +84,29 @@
 #define IGC_GPIE_EIAME          0x40000000
 #define IGC_GPIE_PBA            0x80000000
 
+/* Transmit Descriptor bit definitions */
+#define IGC_TXD_DTYP_D          0x00100000 /* Data Descriptor */
+#define IGC_TXD_DTYP_C          0x00000000 /* Context Descriptor */
+#define IGC_TXD_POPTS_IXSM      0x01       /* Insert IP checksum */
+#define IGC_TXD_POPTS_TXSM      0x02       /* Insert TCP/UDP checksum */
+#define IGC_TXD_CMD_EOP         0x01000000 /* End of Packet */
+#define IGC_TXD_CMD_IFCS        0x02000000 /* Insert FCS (Ethernet CRC) */
+#define IGC_TXD_CMD_IC          0x04000000 /* Insert Checksum */
+#define IGC_TXD_CMD_RS          0x08000000 /* Report Status */
+#define IGC_TXD_CMD_RPS         0x10000000 /* Report Packet Sent */
+#define IGC_TXD_CMD_DEXT        0x20000000 /* Desc extension (0 = legacy) */
+#define IGC_TXD_CMD_VLE         0x40000000 /* Add VLAN tag */
+#define IGC_TXD_CMD_IDE         0x80000000 /* Enable Tidv register */
+#define IGC_TXD_STAT_DD         0x00000001 /* Descriptor Done */
+#define IGC_TXD_STAT_EC         0x00000002 /* Excess Collisions */
+#define IGC_TXD_STAT_LC         0x00000004 /* Late Collisions */
+#define IGC_TXD_STAT_TU         0x00000008 /* Transmit underrun */
+#define IGC_TXD_CMD_TCP         0x01000000 /* TCP packet */
+#define IGC_TXD_CMD_IP          0x02000000 /* IP packet */
+#define IGC_TXD_CMD_TSE         0x04000000 /* TCP Seg enable */
+#define IGC_TXD_STAT_TC         0x00000004 /* Tx Underrun */
+#define IGC_TXD_EXTCMD_TSTAMP   0x00000010 /* IEEE1588 Timestamp packet */
+
 /* Transmit Control */
 #define IGC_TCTL_EN             0x00000002 /* enable Tx */
 #define IGC_TCTL_PSP            0x00000008 /* pad short packets */
@@ -111,6 +134,25 @@
 #define IGC_RCTL_RDMTS_HALF     0x00000000 /* Rx desc min thresh size */
 #define IGC_RCTL_BAM            0x00008000 /* broadcast enable */
 
+/* Receive Descriptor bit definitions */
+#define IGC_RXD_STAT_EOP        0x02    /* End of Packet */
+
+#define IGC_RXDEXT_STATERR_CE           0x01000000
+#define IGC_RXDEXT_STATERR_SE           0x02000000
+#define IGC_RXDEXT_STATERR_SEQ          0x04000000
+#define IGC_RXDEXT_STATERR_CXE          0x10000000
+#define IGC_RXDEXT_STATERR_TCPE         0x20000000
+#define IGC_RXDEXT_STATERR_IPE          0x40000000
+#define IGC_RXDEXT_STATERR_RXE          0x80000000
+
+/* Same mask, but for extended and packet split descriptors */
+#define IGC_RXDEXT_ERR_FRAME_ERR_MASK ( \
+        IGC_RXDEXT_STATERR_CE  |        \
+        IGC_RXDEXT_STATERR_SE  |        \
+        IGC_RXDEXT_STATERR_SEQ |        \
+        IGC_RXDEXT_STATERR_CXE |        \
+        IGC_RXDEXT_STATERR_RXE)
+
 /* Header split receive */
 #define IGC_RFCTL_IPV6_EX_DIS   0x00010000
 #define IGC_RFCTL_LEF           0x00040000
@@ -123,6 +165,9 @@
 #define IGC_RCTL_PMCF           0x00800000 /* pass MAC control frames */
 #define IGC_RCTL_SECRC          0x04000000 /* Strip Ethernet CRC */
 
+#define I225_RXPBSIZE_DEFAULT   0x000000A2 /* RXPBSIZE default */
+#define I225_TXPBSIZE_DEFAULT   0x04000014 /* TXPBSIZE default */
+
 #define IGC_N0_QUEUE -1
 
 #endif /* _IGC_DEFINES_H_ */