diff options
Diffstat (limited to 'drivers/net/ethernet/intel/igc/igc_base.h')
-rw-r--r-- | drivers/net/ethernet/intel/igc/igc_base.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/net/ethernet/intel/igc/igc_base.h b/drivers/net/ethernet/intel/igc/igc_base.h index 4bdb4ecf3bc8..3078a18f70a9 100644 --- a/drivers/net/ethernet/intel/igc/igc_base.h +++ b/drivers/net/ethernet/intel/igc/igc_base.h | |||
@@ -21,6 +21,18 @@ union igc_adv_tx_desc { | |||
21 | } wb; | 21 | } wb; |
22 | }; | 22 | }; |
23 | 23 | ||
24 | /* Adv Transmit Descriptor Config Masks */ | ||
25 | #define IGC_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 Timestamp packet */ | ||
26 | #define IGC_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */ | ||
27 | #define IGC_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ | ||
28 | #define IGC_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */ | ||
29 | #define IGC_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ | ||
30 | #define IGC_ADVTXD_DCMD_RS 0x08000000 /* Report Status */ | ||
31 | #define IGC_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */ | ||
32 | #define IGC_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */ | ||
33 | #define IGC_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ | ||
34 | #define IGC_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ | ||
35 | |||
24 | struct igc_adv_data_desc { | 36 | struct igc_adv_data_desc { |
25 | __le64 buffer_addr; /* Address of the descriptor's data buffer */ | 37 | __le64 buffer_addr; /* Address of the descriptor's data buffer */ |
26 | union { | 38 | union { |
@@ -75,6 +87,9 @@ union igc_adv_rx_desc { | |||
75 | } wb; /* writeback */ | 87 | } wb; /* writeback */ |
76 | }; | 88 | }; |
77 | 89 | ||
90 | /* Adv Transmit Descriptor Config Masks */ | ||
91 | #define IGC_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ | ||
92 | |||
78 | /* Additional Transmit Descriptor Control definitions */ | 93 | /* Additional Transmit Descriptor Control definitions */ |
79 | #define IGC_TXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Tx Queue */ | 94 | #define IGC_TXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Tx Queue */ |
80 | 95 | ||