1 files changed, 312 insertions, 0 deletions
diff --git a/drivers/net/ethernet/ibm/emac/emac.h b/drivers/net/ethernet/ibm/emac/emac.h
new file mode 100644
index 000000000000..1568278d759a
--- /dev/null
+++ b/drivers/net/ethernet/ibm/emac/emac.h
@@ -0,0 +1,312 @@
+/*
+ * drivers/net/ibm_newemac/emac.h
+ *
+ * Register definitions for PowerPC 4xx on-chip ethernet contoller
+ *
+ * Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
+ *                <benh@kernel.crashing.org>
+ *
+ * Based on the arch/ppc version of the driver:
+ *
+ * Copyright (c) 2004, 2005 Zultys Technologies.
+ * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
+ *
+ * Based on original work by
+ *      Matt Porter <mporter@kernel.crashing.org>
+ *      Armin Kuster <akuster@mvista.com>
+ *      Copyright 2002-2004 MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+#ifndef __IBM_NEWEMAC_H
+#define __IBM_NEWEMAC_H
+#include <linux/types.h>
+#include <linux/phy.h>
+/* EMAC registers                       Write Access rules */
+struct emac_regs {
+        /* Common registers across all EMAC implementations. */
+        u32 mr0;                        /* Special      */
+        u32 mr1;                        /* Reset        */
+        u32 tmr0;                       /* Special      */
+        u32 tmr1;                       /* Special      */
+        u32 rmr;                        /* Reset        */
+        u32 isr;                        /* Always       */
+        u32 iser;                       /* Reset        */
+        u32 iahr;                       /* Reset, R, T  */
+        u32 ialr;                       /* Reset, R, T  */
+        u32 vtpid;                      /* Reset, R, T  */
+        u32 vtci;                       /* Reset, R, T  */
+        u32 ptr;                        /* Reset,    T  */
+        union {
+                /* Registers unique to EMAC4 implementations */
+                struct {
+                        u32 iaht1;      /* Reset, R     */
+                        u32 iaht2;      /* Reset, R     */
+                        u32 iaht3;      /* Reset, R     */
+                        u32 iaht4;      /* Reset, R     */
+                        u32 gaht1;      /* Reset, R     */
+                        u32 gaht2;      /* Reset, R     */
+                        u32 gaht3;      /* Reset, R     */
+                        u32 gaht4;      /* Reset, R     */
+                } emac4;
+                /* Registers unique to EMAC4SYNC implementations */
+                struct {
+                        u32 mahr;       /* Reset, R, T  */
+                        u32 malr;       /* Reset, R, T  */
+                        u32 mmahr;      /* Reset, R, T  */
+                        u32 mmalr;      /* Reset, R, T  */
+                        u32 rsvd0[4];
+                } emac4sync;
+        } u0;
+        /* Common registers across all EMAC implementations. */
+        u32 lsah;
+        u32 lsal;
+        u32 ipgvr;                      /* Reset,    T  */
+        u32 stacr;                      /* Special      */
+        u32 trtr;                       /* Special      */
+        u32 rwmr;                       /* Reset        */
+        u32 octx;
+        u32 ocrx;
+        union {
+                /* Registers unique to EMAC4 implementations */
+                struct {
+                        u32 ipcr;
+                } emac4;
+                /* Registers unique to EMAC4SYNC implementations */
+                struct {
+                        u32 rsvd1;
+                        u32 revid;
+                        u32 rsvd2[2];
+                        u32 iaht1;      /* Reset, R     */
+                        u32 iaht2;      /* Reset, R     */
+                        u32 iaht3;      /* Reset, R     */
+                        u32 iaht4;      /* Reset, R     */
+                        u32 iaht5;      /* Reset, R     */
+                        u32 iaht6;      /* Reset, R     */
+                        u32 iaht7;      /* Reset, R     */
+                        u32 iaht8;      /* Reset, R     */
+                        u32 gaht1;      /* Reset, R     */
+                        u32 gaht2;      /* Reset, R     */
+                        u32 gaht3;      /* Reset, R     */
+                        u32 gaht4;      /* Reset, R     */
+                        u32 gaht5;      /* Reset, R     */
+                        u32 gaht6;      /* Reset, R     */
+                        u32 gaht7;      /* Reset, R     */
+                        u32 gaht8;      /* Reset, R     */
+                        u32 tpc;        /* Reset, T     */
+                } emac4sync;
+        } u1;
+};
+/*
+ * PHY mode settings (EMAC <-> ZMII/RGMII bridge <-> PHY)
+ */
+#define PHY_MODE_NA     PHY_INTERFACE_MODE_NA
+#define PHY_MODE_MII    PHY_INTERFACE_MODE_MII
+#define PHY_MODE_RMII   PHY_INTERFACE_MODE_RMII
+#define PHY_MODE_SMII   PHY_INTERFACE_MODE_SMII
+#define PHY_MODE_RGMII  PHY_INTERFACE_MODE_RGMII
+#define PHY_MODE_TBI    PHY_INTERFACE_MODE_TBI
+#define PHY_MODE_GMII   PHY_INTERFACE_MODE_GMII
+#define PHY_MODE_RTBI   PHY_INTERFACE_MODE_RTBI
+#define PHY_MODE_SGMII  PHY_INTERFACE_MODE_SGMII
+/* EMACx_MR0 */
+#define EMAC_MR0_RXI                    0x80000000
+#define EMAC_MR0_TXI                    0x40000000
+#define EMAC_MR0_SRST                   0x20000000
+#define EMAC_MR0_TXE                    0x10000000
+#define EMAC_MR0_RXE                    0x08000000
+#define EMAC_MR0_WKE                    0x04000000
+/* EMACx_MR1 */
+#define EMAC_MR1_FDE                    0x80000000
+#define EMAC_MR1_ILE                    0x40000000
+#define EMAC_MR1_VLE                    0x20000000
+#define EMAC_MR1_EIFC                   0x10000000
+#define EMAC_MR1_APP                    0x08000000
+#define EMAC_MR1_IST                    0x01000000
+#define EMAC_MR1_MF_MASK                0x00c00000
+#define EMAC_MR1_MF_10                  0x00000000
+#define EMAC_MR1_MF_100                 0x00400000
+#define EMAC_MR1_MF_1000                0x00800000
+#define EMAC_MR1_MF_1000GPCS            0x00c00000
+#define EMAC_MR1_MF_IPPA(id)            (((id) & 0x1f) << 6)
+#define EMAC_MR1_RFS_4K                 0x00300000
+#define EMAC_MR1_RFS_16K                0x00000000
+#define EMAC_MR1_TFS_2K                 0x00080000
+#define EMAC_MR1_TR0_MULT               0x00008000
+#define EMAC_MR1_JPSM                   0x00000000
+#define EMAC_MR1_MWSW_001               0x00000000
+#define EMAC_MR1_BASE(opb)              (EMAC_MR1_TFS_2K | EMAC_MR1_TR0_MULT)
+#define EMAC4_MR1_RFS_2K                0x00100000
+#define EMAC4_MR1_RFS_4K                0x00180000
+#define EMAC4_MR1_RFS_16K               0x00280000
+#define EMAC4_MR1_TFS_2K                0x00020000
+#define EMAC4_MR1_TFS_4K                0x00030000
+#define EMAC4_MR1_TFS_16K               0x00050000
+#define EMAC4_MR1_TR                    0x00008000
+#define EMAC4_MR1_MWSW_001              0x00001000
+#define EMAC4_MR1_JPSM                  0x00000800
+#define EMAC4_MR1_OBCI_MASK             0x00000038
+#define EMAC4_MR1_OBCI_50               0x00000000
+#define EMAC4_MR1_OBCI_66               0x00000008
+#define EMAC4_MR1_OBCI_83               0x00000010
+#define EMAC4_MR1_OBCI_100              0x00000018
+#define EMAC4_MR1_OBCI_100P             0x00000020
+#define EMAC4_MR1_OBCI(freq)            ((freq) <= 50  ? EMAC4_MR1_OBCI_50 : \
+                                         (freq) <= 66  ? EMAC4_MR1_OBCI_66 : \
+                                         (freq) <= 83  ? EMAC4_MR1_OBCI_83 : \
+                                         (freq) <= 100 ? EMAC4_MR1_OBCI_100 : \
+                                                EMAC4_MR1_OBCI_100P)
+/* EMACx_TMR0 */
+#define EMAC_TMR0_GNP                   0x80000000
+#define EMAC_TMR0_DEFAULT               0x00000000
+#define EMAC4_TMR0_TFAE_2_32            0x00000001
+#define EMAC4_TMR0_TFAE_4_64            0x00000002
+#define EMAC4_TMR0_TFAE_8_128           0x00000003
+#define EMAC4_TMR0_TFAE_16_256          0x00000004
+#define EMAC4_TMR0_TFAE_32_512          0x00000005
+#define EMAC4_TMR0_TFAE_64_1024         0x00000006
+#define EMAC4_TMR0_TFAE_128_2048        0x00000007
+#define EMAC4_TMR0_DEFAULT              EMAC4_TMR0_TFAE_2_32
+#define EMAC_TMR0_XMIT                  (EMAC_TMR0_GNP | EMAC_TMR0_DEFAULT)
+#define EMAC4_TMR0_XMIT                 (EMAC_TMR0_GNP | EMAC4_TMR0_DEFAULT)
+/* EMACx_TMR1 */
+#define EMAC_TMR1(l,h)                  (((l) << 27) | (((h) & 0xff) << 16))
+#define EMAC4_TMR1(l,h)                 (((l) << 27) | (((h) & 0x3ff) << 14))
+/* EMACx_RMR */
+#define EMAC_RMR_SP                     0x80000000
+#define EMAC_RMR_SFCS                   0x40000000
+#define EMAC_RMR_RRP                    0x20000000
+#define EMAC_RMR_RFP                    0x10000000
+#define EMAC_RMR_ROP                    0x08000000
+#define EMAC_RMR_RPIR                   0x04000000
+#define EMAC_RMR_PPP                    0x02000000
+#define EMAC_RMR_PME                    0x01000000
+#define EMAC_RMR_PMME                   0x00800000
+#define EMAC_RMR_IAE                    0x00400000
+#define EMAC_RMR_MIAE                   0x00200000
+#define EMAC_RMR_BAE                    0x00100000
+#define EMAC_RMR_MAE                    0x00080000
+#define EMAC_RMR_BASE                   0x00000000
+#define EMAC4_RMR_RFAF_2_32             0x00000001
+#define EMAC4_RMR_RFAF_4_64             0x00000002
+#define EMAC4_RMR_RFAF_8_128            0x00000003
+#define EMAC4_RMR_RFAF_16_256           0x00000004
+#define EMAC4_RMR_RFAF_32_512           0x00000005
+#define EMAC4_RMR_RFAF_64_1024          0x00000006
+#define EMAC4_RMR_RFAF_128_2048         0x00000007
+#define EMAC4_RMR_BASE                  EMAC4_RMR_RFAF_128_2048
+/* EMACx_ISR & EMACx_ISER */
+#define EMAC4_ISR_TXPE                  0x20000000
+#define EMAC4_ISR_RXPE                  0x10000000
+#define EMAC4_ISR_TXUE                  0x08000000
+#define EMAC4_ISR_RXOE                  0x04000000
+#define EMAC_ISR_OVR                    0x02000000
+#define EMAC_ISR_PP                     0x01000000
+#define EMAC_ISR_BP                     0x00800000
+#define EMAC_ISR_RP                     0x00400000
+#define EMAC_ISR_SE                     0x00200000
+#define EMAC_ISR_ALE                    0x00100000
+#define EMAC_ISR_BFCS                   0x00080000
+#define EMAC_ISR_PTLE                   0x00040000
+#define EMAC_ISR_ORE                    0x00020000
+#define EMAC_ISR_IRE                    0x00010000
+#define EMAC_ISR_SQE                    0x00000080
+#define EMAC_ISR_TE                     0x00000040
+#define EMAC_ISR_MOS                    0x00000002
+#define EMAC_ISR_MOF                    0x00000001
+/* EMACx_STACR */
+#define EMAC_STACR_PHYD_MASK            0xffff
+#define EMAC_STACR_PHYD_SHIFT           16
+#define EMAC_STACR_OC                   0x00008000
+#define EMAC_STACR_PHYE                 0x00004000
+#define EMAC_STACR_STAC_MASK            0x00003000
+#define EMAC_STACR_STAC_READ            0x00001000
+#define EMAC_STACR_STAC_WRITE           0x00002000
+#define EMAC_STACR_OPBC_MASK            0x00000C00
+#define EMAC_STACR_OPBC_50              0x00000000
+#define EMAC_STACR_OPBC_66              0x00000400
+#define EMAC_STACR_OPBC_83              0x00000800
+#define EMAC_STACR_OPBC_100             0x00000C00
+#define EMAC_STACR_OPBC(freq)           ((freq) <= 50 ? EMAC_STACR_OPBC_50 : \
+                                         (freq) <= 66 ? EMAC_STACR_OPBC_66 : \
+                                         (freq) <= 83 ? EMAC_STACR_OPBC_83 : EMAC_STACR_OPBC_100)
+#define EMAC_STACR_BASE(opb)            EMAC_STACR_OPBC(opb)
+#define EMAC4_STACR_BASE(opb)           0x00000000
+#define EMAC_STACR_PCDA_MASK            0x1f
+#define EMAC_STACR_PCDA_SHIFT           5
+#define EMAC_STACR_PRA_MASK             0x1f
+#define EMACX_STACR_STAC_MASK           0x00003800
+#define EMACX_STACR_STAC_READ           0x00001000
+#define EMACX_STACR_STAC_WRITE          0x00000800
+#define EMACX_STACR_STAC_IND_ADDR       0x00002000
+#define EMACX_STACR_STAC_IND_READ       0x00003800
+#define EMACX_STACR_STAC_IND_READINC    0x00003000
+#define EMACX_STACR_STAC_IND_WRITE      0x00002800
+/* EMACx_TRTR */
+#define EMAC_TRTR_SHIFT_EMAC4           24
+#define EMAC_TRTR_SHIFT         27
+/* EMAC specific TX descriptor control fields (write access) */
+#define EMAC_TX_CTRL_GFCS               0x0200
+#define EMAC_TX_CTRL_GP                 0x0100
+#define EMAC_TX_CTRL_ISA                0x0080
+#define EMAC_TX_CTRL_RSA                0x0040
+#define EMAC_TX_CTRL_IVT                0x0020
+#define EMAC_TX_CTRL_RVT                0x0010
+#define EMAC_TX_CTRL_TAH_CSUM           0x000e
+/* EMAC specific TX descriptor status fields (read access) */
+#define EMAC_TX_ST_BFCS                 0x0200
+#define EMAC_TX_ST_LCS                  0x0080
+#define EMAC_TX_ST_ED                   0x0040
+#define EMAC_TX_ST_EC                   0x0020
+#define EMAC_TX_ST_LC                   0x0010
+#define EMAC_TX_ST_MC                   0x0008
+#define EMAC_TX_ST_SC                   0x0004
+#define EMAC_TX_ST_UR                   0x0002
+#define EMAC_TX_ST_SQE                  0x0001
+#define EMAC_IS_BAD_TX                  (EMAC_TX_ST_LCS | EMAC_TX_ST_ED | \
+                                         EMAC_TX_ST_EC | EMAC_TX_ST_LC | \
+                                         EMAC_TX_ST_MC | EMAC_TX_ST_UR)
+#define EMAC_IS_BAD_TX_TAH              (EMAC_TX_ST_LCS | EMAC_TX_ST_ED | \
+                                         EMAC_TX_ST_EC | EMAC_TX_ST_LC)
+/* EMAC specific RX descriptor status fields (read access) */
+#define EMAC_RX_ST_OE                   0x0200
+#define EMAC_RX_ST_PP                   0x0100
+#define EMAC_RX_ST_BP                   0x0080
+#define EMAC_RX_ST_RP                   0x0040
+#define EMAC_RX_ST_SE                   0x0020
+#define EMAC_RX_ST_AE                   0x0010
+#define EMAC_RX_ST_BFCS                 0x0008
+#define EMAC_RX_ST_PTL                  0x0004
+#define EMAC_RX_ST_ORE                  0x0002
+#define EMAC_RX_ST_IRE                  0x0001
+#define EMAC_RX_TAH_BAD_CSUM            0x0003
+#define EMAC_BAD_RX_MASK                (EMAC_RX_ST_OE | EMAC_RX_ST_BP | \
+                                         EMAC_RX_ST_RP | EMAC_RX_ST_SE | \
+                                         EMAC_RX_ST_AE | EMAC_RX_ST_BFCS | \
+                                         EMAC_RX_ST_PTL | EMAC_RX_ST_ORE | \
+                                         EMAC_RX_ST_IRE )
+#endif /* __IBM_NEWEMAC_H */

diff --git a/drivers/net/ethernet/ibm/emac/emac.h b/drivers/net/ethernet/ibm/emac/emac.h new file mode 100644 index 000000000000..1568278d759a --- /dev/null +++ b/drivers/net/ethernet/ibm/emac/emac.h
@@ -0,0 +1,312 @@
	1	/*
	2	* drivers/net/ibm_newemac/emac.h
	3	*
	4	* Register definitions for PowerPC 4xx on-chip ethernet contoller
	5	*
	6	* Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
	7	* <benh@kernel.crashing.org>
	8	*
	9	* Based on the arch/ppc version of the driver:
	10	*
	11	* Copyright (c) 2004, 2005 Zultys Technologies.
	12	* Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
	13	*
	14	* Based on original work by
	15	* Matt Porter <mporter@kernel.crashing.org>
	16	* Armin Kuster <akuster@mvista.com>
	17	* Copyright 2002-2004 MontaVista Software Inc.
	18	*
	19	* This program is free software; you can redistribute it and/or modify it
	20	* under the terms of the GNU General Public License as published by the
	21	* Free Software Foundation; either version 2 of the License, or (at your
	22	* option) any later version.
	23	*
	24	*/
	25	#ifndef __IBM_NEWEMAC_H
	26	#define __IBM_NEWEMAC_H
	27
	28	#include <linux/types.h>
	29	#include <linux/phy.h>
	30
	31	/* EMAC registers Write Access rules */
	32	struct emac_regs {
	33	/* Common registers across all EMAC implementations. */
	34	u32 mr0; /* Special */
	35	u32 mr1; /* Reset */
	36	u32 tmr0; /* Special */
	37	u32 tmr1; /* Special */
	38	u32 rmr; /* Reset */
	39	u32 isr; /* Always */
	40	u32 iser; /* Reset */
	41	u32 iahr; /* Reset, R, T */
	42	u32 ialr; /* Reset, R, T */
	43	u32 vtpid; /* Reset, R, T */
	44	u32 vtci; /* Reset, R, T */
	45	u32 ptr; /* Reset, T */
	46	union {
	47	/* Registers unique to EMAC4 implementations */
	48	struct {
	49	u32 iaht1; /* Reset, R */
	50	u32 iaht2; /* Reset, R */
	51	u32 iaht3; /* Reset, R */
	52	u32 iaht4; /* Reset, R */
	53	u32 gaht1; /* Reset, R */
	54	u32 gaht2; /* Reset, R */
	55	u32 gaht3; /* Reset, R */
	56	u32 gaht4; /* Reset, R */
	57	} emac4;
	58	/* Registers unique to EMAC4SYNC implementations */
	59	struct {
	60	u32 mahr; /* Reset, R, T */
	61	u32 malr; /* Reset, R, T */
	62	u32 mmahr; /* Reset, R, T */
	63	u32 mmalr; /* Reset, R, T */
	64	u32 rsvd0[4];
	65	} emac4sync;
	66	} u0;
	67	/* Common registers across all EMAC implementations. */
	68	u32 lsah;
	69	u32 lsal;
	70	u32 ipgvr; /* Reset, T */
	71	u32 stacr; /* Special */
	72	u32 trtr; /* Special */
	73	u32 rwmr; /* Reset */
	74	u32 octx;
	75	u32 ocrx;
	76	union {
	77	/* Registers unique to EMAC4 implementations */
	78	struct {
	79	u32 ipcr;
	80	} emac4;
	81	/* Registers unique to EMAC4SYNC implementations */
	82	struct {
	83	u32 rsvd1;
	84	u32 revid;
	85	u32 rsvd2[2];
	86	u32 iaht1; /* Reset, R */
	87	u32 iaht2; /* Reset, R */
	88	u32 iaht3; /* Reset, R */
	89	u32 iaht4; /* Reset, R */
	90	u32 iaht5; /* Reset, R */
	91	u32 iaht6; /* Reset, R */
	92	u32 iaht7; /* Reset, R */
	93	u32 iaht8; /* Reset, R */
	94	u32 gaht1; /* Reset, R */
	95	u32 gaht2; /* Reset, R */
	96	u32 gaht3; /* Reset, R */
	97	u32 gaht4; /* Reset, R */
	98	u32 gaht5; /* Reset, R */
	99	u32 gaht6; /* Reset, R */
	100	u32 gaht7; /* Reset, R */
	101	u32 gaht8; /* Reset, R */
	102	u32 tpc; /* Reset, T */
	103	} emac4sync;
	104	} u1;
	105	};
	106
	107	/*
	108	* PHY mode settings (EMAC <-> ZMII/RGMII bridge <-> PHY)
	109	*/
	110	#define PHY_MODE_NA PHY_INTERFACE_MODE_NA
	111	#define PHY_MODE_MII PHY_INTERFACE_MODE_MII
	112	#define PHY_MODE_RMII PHY_INTERFACE_MODE_RMII
	113	#define PHY_MODE_SMII PHY_INTERFACE_MODE_SMII
	114	#define PHY_MODE_RGMII PHY_INTERFACE_MODE_RGMII
	115	#define PHY_MODE_TBI PHY_INTERFACE_MODE_TBI
	116	#define PHY_MODE_GMII PHY_INTERFACE_MODE_GMII
	117	#define PHY_MODE_RTBI PHY_INTERFACE_MODE_RTBI
	118	#define PHY_MODE_SGMII PHY_INTERFACE_MODE_SGMII
	119
	120	/* EMACx_MR0 */
	121	#define EMAC_MR0_RXI 0x80000000
	122	#define EMAC_MR0_TXI 0x40000000
	123	#define EMAC_MR0_SRST 0x20000000
	124	#define EMAC_MR0_TXE 0x10000000
	125	#define EMAC_MR0_RXE 0x08000000
	126	#define EMAC_MR0_WKE 0x04000000
	127
	128	/* EMACx_MR1 */
	129	#define EMAC_MR1_FDE 0x80000000
	130	#define EMAC_MR1_ILE 0x40000000
	131	#define EMAC_MR1_VLE 0x20000000
	132	#define EMAC_MR1_EIFC 0x10000000
	133	#define EMAC_MR1_APP 0x08000000
	134	#define EMAC_MR1_IST 0x01000000
	135
	136	#define EMAC_MR1_MF_MASK 0x00c00000
	137	#define EMAC_MR1_MF_10 0x00000000
	138	#define EMAC_MR1_MF_100 0x00400000
	139	#define EMAC_MR1_MF_1000 0x00800000
	140	#define EMAC_MR1_MF_1000GPCS 0x00c00000
	141	#define EMAC_MR1_MF_IPPA(id) (((id) & 0x1f) << 6)
	142
	143	#define EMAC_MR1_RFS_4K 0x00300000
	144	#define EMAC_MR1_RFS_16K 0x00000000
	145	#define EMAC_MR1_TFS_2K 0x00080000
	146	#define EMAC_MR1_TR0_MULT 0x00008000
	147	#define EMAC_MR1_JPSM 0x00000000
	148	#define EMAC_MR1_MWSW_001 0x00000000
	149	#define EMAC_MR1_BASE(opb) (EMAC_MR1_TFS_2K \| EMAC_MR1_TR0_MULT)
	150
	151
	152	#define EMAC4_MR1_RFS_2K 0x00100000
	153	#define EMAC4_MR1_RFS_4K 0x00180000
	154	#define EMAC4_MR1_RFS_16K 0x00280000
	155	#define EMAC4_MR1_TFS_2K 0x00020000
	156	#define EMAC4_MR1_TFS_4K 0x00030000
	157	#define EMAC4_MR1_TFS_16K 0x00050000
	158	#define EMAC4_MR1_TR 0x00008000
	159	#define EMAC4_MR1_MWSW_001 0x00001000
	160	#define EMAC4_MR1_JPSM 0x00000800
	161	#define EMAC4_MR1_OBCI_MASK 0x00000038
	162	#define EMAC4_MR1_OBCI_50 0x00000000
	163	#define EMAC4_MR1_OBCI_66 0x00000008
	164	#define EMAC4_MR1_OBCI_83 0x00000010
	165	#define EMAC4_MR1_OBCI_100 0x00000018
	166	#define EMAC4_MR1_OBCI_100P 0x00000020
	167	#define EMAC4_MR1_OBCI(freq) ((freq) <= 50 ? EMAC4_MR1_OBCI_50 : \
	168	(freq) <= 66 ? EMAC4_MR1_OBCI_66 : \
	169	(freq) <= 83 ? EMAC4_MR1_OBCI_83 : \
	170	(freq) <= 100 ? EMAC4_MR1_OBCI_100 : \
	171	EMAC4_MR1_OBCI_100P)
	172
	173	/* EMACx_TMR0 */
	174	#define EMAC_TMR0_GNP 0x80000000
	175	#define EMAC_TMR0_DEFAULT 0x00000000
	176	#define EMAC4_TMR0_TFAE_2_32 0x00000001
	177	#define EMAC4_TMR0_TFAE_4_64 0x00000002
	178	#define EMAC4_TMR0_TFAE_8_128 0x00000003
	179	#define EMAC4_TMR0_TFAE_16_256 0x00000004
	180	#define EMAC4_TMR0_TFAE_32_512 0x00000005
	181	#define EMAC4_TMR0_TFAE_64_1024 0x00000006
	182	#define EMAC4_TMR0_TFAE_128_2048 0x00000007
	183	#define EMAC4_TMR0_DEFAULT EMAC4_TMR0_TFAE_2_32
	184	#define EMAC_TMR0_XMIT (EMAC_TMR0_GNP \| EMAC_TMR0_DEFAULT)
	185	#define EMAC4_TMR0_XMIT (EMAC_TMR0_GNP \| EMAC4_TMR0_DEFAULT)
	186
	187	/* EMACx_TMR1 */
	188
	189	#define EMAC_TMR1(l,h) (((l) << 27) \| (((h) & 0xff) << 16))
	190	#define EMAC4_TMR1(l,h) (((l) << 27) \| (((h) & 0x3ff) << 14))
	191
	192	/* EMACx_RMR */
	193	#define EMAC_RMR_SP 0x80000000
	194	#define EMAC_RMR_SFCS 0x40000000
	195	#define EMAC_RMR_RRP 0x20000000
	196	#define EMAC_RMR_RFP 0x10000000
	197	#define EMAC_RMR_ROP 0x08000000
	198	#define EMAC_RMR_RPIR 0x04000000
	199	#define EMAC_RMR_PPP 0x02000000
	200	#define EMAC_RMR_PME 0x01000000
	201	#define EMAC_RMR_PMME 0x00800000
	202	#define EMAC_RMR_IAE 0x00400000
	203	#define EMAC_RMR_MIAE 0x00200000
	204	#define EMAC_RMR_BAE 0x00100000
	205	#define EMAC_RMR_MAE 0x00080000
	206	#define EMAC_RMR_BASE 0x00000000
	207	#define EMAC4_RMR_RFAF_2_32 0x00000001
	208	#define EMAC4_RMR_RFAF_4_64 0x00000002
	209	#define EMAC4_RMR_RFAF_8_128 0x00000003
	210	#define EMAC4_RMR_RFAF_16_256 0x00000004
	211	#define EMAC4_RMR_RFAF_32_512 0x00000005
	212	#define EMAC4_RMR_RFAF_64_1024 0x00000006
	213	#define EMAC4_RMR_RFAF_128_2048 0x00000007
	214	#define EMAC4_RMR_BASE EMAC4_RMR_RFAF_128_2048
	215
	216	/* EMACx_ISR & EMACx_ISER */
	217	#define EMAC4_ISR_TXPE 0x20000000
	218	#define EMAC4_ISR_RXPE 0x10000000
	219	#define EMAC4_ISR_TXUE 0x08000000
	220	#define EMAC4_ISR_RXOE 0x04000000
	221	#define EMAC_ISR_OVR 0x02000000
	222	#define EMAC_ISR_PP 0x01000000
	223	#define EMAC_ISR_BP 0x00800000
	224	#define EMAC_ISR_RP 0x00400000
	225	#define EMAC_ISR_SE 0x00200000
	226	#define EMAC_ISR_ALE 0x00100000
	227	#define EMAC_ISR_BFCS 0x00080000
	228	#define EMAC_ISR_PTLE 0x00040000
	229	#define EMAC_ISR_ORE 0x00020000
	230	#define EMAC_ISR_IRE 0x00010000
	231	#define EMAC_ISR_SQE 0x00000080
	232	#define EMAC_ISR_TE 0x00000040
	233	#define EMAC_ISR_MOS 0x00000002
	234	#define EMAC_ISR_MOF 0x00000001
	235
	236	/* EMACx_STACR */
	237	#define EMAC_STACR_PHYD_MASK 0xffff
	238	#define EMAC_STACR_PHYD_SHIFT 16
	239	#define EMAC_STACR_OC 0x00008000
	240	#define EMAC_STACR_PHYE 0x00004000
	241	#define EMAC_STACR_STAC_MASK 0x00003000
	242	#define EMAC_STACR_STAC_READ 0x00001000
	243	#define EMAC_STACR_STAC_WRITE 0x00002000
	244	#define EMAC_STACR_OPBC_MASK 0x00000C00
	245	#define EMAC_STACR_OPBC_50 0x00000000
	246	#define EMAC_STACR_OPBC_66 0x00000400
	247	#define EMAC_STACR_OPBC_83 0x00000800
	248	#define EMAC_STACR_OPBC_100 0x00000C00
	249	#define EMAC_STACR_OPBC(freq) ((freq) <= 50 ? EMAC_STACR_OPBC_50 : \
	250	(freq) <= 66 ? EMAC_STACR_OPBC_66 : \
	251	(freq) <= 83 ? EMAC_STACR_OPBC_83 : EMAC_STACR_OPBC_100)
	252	#define EMAC_STACR_BASE(opb) EMAC_STACR_OPBC(opb)
	253	#define EMAC4_STACR_BASE(opb) 0x00000000
	254	#define EMAC_STACR_PCDA_MASK 0x1f
	255	#define EMAC_STACR_PCDA_SHIFT 5
	256	#define EMAC_STACR_PRA_MASK 0x1f
	257	#define EMACX_STACR_STAC_MASK 0x00003800
	258	#define EMACX_STACR_STAC_READ 0x00001000
	259	#define EMACX_STACR_STAC_WRITE 0x00000800
	260	#define EMACX_STACR_STAC_IND_ADDR 0x00002000
	261	#define EMACX_STACR_STAC_IND_READ 0x00003800
	262	#define EMACX_STACR_STAC_IND_READINC 0x00003000
	263	#define EMACX_STACR_STAC_IND_WRITE 0x00002800
	264
	265
	266	/* EMACx_TRTR */
	267	#define EMAC_TRTR_SHIFT_EMAC4 24
	268	#define EMAC_TRTR_SHIFT 27
	269
	270	/* EMAC specific TX descriptor control fields (write access) */
	271	#define EMAC_TX_CTRL_GFCS 0x0200
	272	#define EMAC_TX_CTRL_GP 0x0100
	273	#define EMAC_TX_CTRL_ISA 0x0080
	274	#define EMAC_TX_CTRL_RSA 0x0040
	275	#define EMAC_TX_CTRL_IVT 0x0020
	276	#define EMAC_TX_CTRL_RVT 0x0010
	277	#define EMAC_TX_CTRL_TAH_CSUM 0x000e
	278
	279	/* EMAC specific TX descriptor status fields (read access) */
	280	#define EMAC_TX_ST_BFCS 0x0200
	281	#define EMAC_TX_ST_LCS 0x0080
	282	#define EMAC_TX_ST_ED 0x0040
	283	#define EMAC_TX_ST_EC 0x0020
	284	#define EMAC_TX_ST_LC 0x0010
	285	#define EMAC_TX_ST_MC 0x0008
	286	#define EMAC_TX_ST_SC 0x0004
	287	#define EMAC_TX_ST_UR 0x0002
	288	#define EMAC_TX_ST_SQE 0x0001
	289	#define EMAC_IS_BAD_TX (EMAC_TX_ST_LCS \| EMAC_TX_ST_ED \| \
	290	EMAC_TX_ST_EC \| EMAC_TX_ST_LC \| \
	291	EMAC_TX_ST_MC \| EMAC_TX_ST_UR)
	292	#define EMAC_IS_BAD_TX_TAH (EMAC_TX_ST_LCS \| EMAC_TX_ST_ED \| \
	293	EMAC_TX_ST_EC \| EMAC_TX_ST_LC)
	294
	295	/* EMAC specific RX descriptor status fields (read access) */
	296	#define EMAC_RX_ST_OE 0x0200
	297	#define EMAC_RX_ST_PP 0x0100
	298	#define EMAC_RX_ST_BP 0x0080
	299	#define EMAC_RX_ST_RP 0x0040
	300	#define EMAC_RX_ST_SE 0x0020
	301	#define EMAC_RX_ST_AE 0x0010
	302	#define EMAC_RX_ST_BFCS 0x0008
	303	#define EMAC_RX_ST_PTL 0x0004
	304	#define EMAC_RX_ST_ORE 0x0002
	305	#define EMAC_RX_ST_IRE 0x0001
	306	#define EMAC_RX_TAH_BAD_CSUM 0x0003
	307	#define EMAC_BAD_RX_MASK (EMAC_RX_ST_OE \| EMAC_RX_ST_BP \| \
	308	EMAC_RX_ST_RP \| EMAC_RX_ST_SE \| \
	309	EMAC_RX_ST_AE \| EMAC_RX_ST_BFCS \| \
	310	EMAC_RX_ST_PTL \| EMAC_RX_ST_ORE \| \
	311	EMAC_RX_ST_IRE )
	312	#endif /* __IBM_NEWEMAC_H */