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path: root/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
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Diffstat (limited to 'drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c')
-rw-r--r--drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c3522
1 files changed, 2322 insertions, 1200 deletions
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
index 2066dd734444..ffdd96020860 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
@@ -1,11 +1,5 @@
1/* 1// SPDX-License-Identifier: GPL-2.0+
2 * Copyright (c) 2016-2017 Hisilicon Limited. 2// Copyright (c) 2016-2017 Hisilicon Limited.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9 3
10#include <linux/acpi.h> 4#include <linux/acpi.h>
11#include <linux/device.h> 5#include <linux/device.h>
@@ -25,21 +19,18 @@
25#include "hclge_mbx.h" 19#include "hclge_mbx.h"
26#include "hclge_mdio.h" 20#include "hclge_mdio.h"
27#include "hclge_tm.h" 21#include "hclge_tm.h"
22#include "hclge_err.h"
28#include "hnae3.h" 23#include "hnae3.h"
29 24
30#define HCLGE_NAME "hclge" 25#define HCLGE_NAME "hclge"
31#define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset)))) 26#define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
32#define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f)) 27#define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
33#define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))
34#define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))
35 28
36static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
37 enum hclge_mta_dmac_sel_type mta_mac_sel,
38 bool enable);
39static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu); 29static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu);
40static int hclge_init_vlan_config(struct hclge_dev *hdev); 30static int hclge_init_vlan_config(struct hclge_dev *hdev);
41static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev); 31static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev);
42static int hclge_update_led_status(struct hclge_dev *hdev); 32static int hclge_set_umv_space(struct hclge_dev *hdev, u16 space_size,
33 u16 *allocated_size, bool is_alloc);
43 34
44static struct hnae3_ae_algo ae_algo; 35static struct hnae3_ae_algo ae_algo;
45 36
@@ -58,175 +49,12 @@ static const struct pci_device_id ae_algo_pci_tbl[] = {
58MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl); 49MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl);
59 50
60static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = { 51static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
61 "Mac Loopback test", 52 "App Loopback test",
62 "Serdes Loopback test", 53 "Serdes serial Loopback test",
54 "Serdes parallel Loopback test",
63 "Phy Loopback test" 55 "Phy Loopback test"
64}; 56};
65 57
66static const struct hclge_comm_stats_str g_all_64bit_stats_string[] = {
67 {"igu_rx_oversize_pkt",
68 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt)},
69 {"igu_rx_undersize_pkt",
70 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt)},
71 {"igu_rx_out_all_pkt",
72 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt)},
73 {"igu_rx_uni_pkt",
74 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt)},
75 {"igu_rx_multi_pkt",
76 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt)},
77 {"igu_rx_broad_pkt",
78 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt)},
79 {"egu_tx_out_all_pkt",
80 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt)},
81 {"egu_tx_uni_pkt",
82 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt)},
83 {"egu_tx_multi_pkt",
84 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt)},
85 {"egu_tx_broad_pkt",
86 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt)},
87 {"ssu_ppp_mac_key_num",
88 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num)},
89 {"ssu_ppp_host_key_num",
90 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num)},
91 {"ppp_ssu_mac_rlt_num",
92 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num)},
93 {"ppp_ssu_host_rlt_num",
94 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num)},
95 {"ssu_tx_in_num",
96 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num)},
97 {"ssu_tx_out_num",
98 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num)},
99 {"ssu_rx_in_num",
100 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num)},
101 {"ssu_rx_out_num",
102 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num)}
103};
104
105static const struct hclge_comm_stats_str g_all_32bit_stats_string[] = {
106 {"igu_rx_err_pkt",
107 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt)},
108 {"igu_rx_no_eof_pkt",
109 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt)},
110 {"igu_rx_no_sof_pkt",
111 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt)},
112 {"egu_tx_1588_pkt",
113 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt)},
114 {"ssu_full_drop_num",
115 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num)},
116 {"ssu_part_drop_num",
117 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num)},
118 {"ppp_key_drop_num",
119 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num)},
120 {"ppp_rlt_drop_num",
121 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num)},
122 {"ssu_key_drop_num",
123 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num)},
124 {"pkt_curr_buf_cnt",
125 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt)},
126 {"qcn_fb_rcv_cnt",
127 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt)},
128 {"qcn_fb_drop_cnt",
129 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt)},
130 {"qcn_fb_invaild_cnt",
131 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt)},
132 {"rx_packet_tc0_in_cnt",
133 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt)},
134 {"rx_packet_tc1_in_cnt",
135 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt)},
136 {"rx_packet_tc2_in_cnt",
137 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt)},
138 {"rx_packet_tc3_in_cnt",
139 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt)},
140 {"rx_packet_tc4_in_cnt",
141 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt)},
142 {"rx_packet_tc5_in_cnt",
143 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt)},
144 {"rx_packet_tc6_in_cnt",
145 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt)},
146 {"rx_packet_tc7_in_cnt",
147 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt)},
148 {"rx_packet_tc0_out_cnt",
149 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt)},
150 {"rx_packet_tc1_out_cnt",
151 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt)},
152 {"rx_packet_tc2_out_cnt",
153 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt)},
154 {"rx_packet_tc3_out_cnt",
155 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt)},
156 {"rx_packet_tc4_out_cnt",
157 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt)},
158 {"rx_packet_tc5_out_cnt",
159 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt)},
160 {"rx_packet_tc6_out_cnt",
161 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt)},
162 {"rx_packet_tc7_out_cnt",
163 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt)},
164 {"tx_packet_tc0_in_cnt",
165 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt)},
166 {"tx_packet_tc1_in_cnt",
167 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt)},
168 {"tx_packet_tc2_in_cnt",
169 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt)},
170 {"tx_packet_tc3_in_cnt",
171 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt)},
172 {"tx_packet_tc4_in_cnt",
173 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt)},
174 {"tx_packet_tc5_in_cnt",
175 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt)},
176 {"tx_packet_tc6_in_cnt",
177 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt)},
178 {"tx_packet_tc7_in_cnt",
179 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt)},
180 {"tx_packet_tc0_out_cnt",
181 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt)},
182 {"tx_packet_tc1_out_cnt",
183 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt)},
184 {"tx_packet_tc2_out_cnt",
185 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt)},
186 {"tx_packet_tc3_out_cnt",
187 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt)},
188 {"tx_packet_tc4_out_cnt",
189 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt)},
190 {"tx_packet_tc5_out_cnt",
191 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt)},
192 {"tx_packet_tc6_out_cnt",
193 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt)},
194 {"tx_packet_tc7_out_cnt",
195 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt)},
196 {"pkt_curr_buf_tc0_cnt",
197 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt)},
198 {"pkt_curr_buf_tc1_cnt",
199 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt)},
200 {"pkt_curr_buf_tc2_cnt",
201 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt)},
202 {"pkt_curr_buf_tc3_cnt",
203 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt)},
204 {"pkt_curr_buf_tc4_cnt",
205 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt)},
206 {"pkt_curr_buf_tc5_cnt",
207 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt)},
208 {"pkt_curr_buf_tc6_cnt",
209 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt)},
210 {"pkt_curr_buf_tc7_cnt",
211 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt)},
212 {"mb_uncopy_num",
213 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num)},
214 {"lo_pri_unicast_rlt_drop_num",
215 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num)},
216 {"hi_pri_multicast_rlt_drop_num",
217 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num)},
218 {"lo_pri_multicast_rlt_drop_num",
219 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num)},
220 {"rx_oq_drop_pkt_cnt",
221 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt)},
222 {"tx_oq_drop_pkt_cnt",
223 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt)},
224 {"nic_l2_err_drop_pkt_cnt",
225 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt)},
226 {"roc_l2_err_drop_pkt_cnt",
227 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt)}
228};
229
230static const struct hclge_comm_stats_str g_mac_stats_string[] = { 58static const struct hclge_comm_stats_str g_mac_stats_string[] = {
231 {"mac_tx_mac_pause_num", 59 {"mac_tx_mac_pause_num",
232 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)}, 60 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
@@ -304,8 +132,6 @@ static const struct hclge_comm_stats_str g_mac_stats_string[] = {
304 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)}, 132 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)},
305 {"mac_tx_4096_8191_oct_pkt_num", 133 {"mac_tx_4096_8191_oct_pkt_num",
306 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)}, 134 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)},
307 {"mac_tx_8192_12287_oct_pkt_num",
308 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_12287_oct_pkt_num)},
309 {"mac_tx_8192_9216_oct_pkt_num", 135 {"mac_tx_8192_9216_oct_pkt_num",
310 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)}, 136 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)},
311 {"mac_tx_9217_12287_oct_pkt_num", 137 {"mac_tx_9217_12287_oct_pkt_num",
@@ -356,8 +182,6 @@ static const struct hclge_comm_stats_str g_mac_stats_string[] = {
356 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)}, 182 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)},
357 {"mac_rx_4096_8191_oct_pkt_num", 183 {"mac_rx_4096_8191_oct_pkt_num",
358 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)}, 184 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)},
359 {"mac_rx_8192_12287_oct_pkt_num",
360 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_12287_oct_pkt_num)},
361 {"mac_rx_8192_9216_oct_pkt_num", 185 {"mac_rx_8192_9216_oct_pkt_num",
362 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)}, 186 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)},
363 {"mac_rx_9217_12287_oct_pkt_num", 187 {"mac_rx_9217_12287_oct_pkt_num",
@@ -405,141 +229,6 @@ static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = {
405 }, 229 },
406}; 230};
407 231
408static int hclge_64_bit_update_stats(struct hclge_dev *hdev)
409{
410#define HCLGE_64_BIT_CMD_NUM 5
411#define HCLGE_64_BIT_RTN_DATANUM 4
412 u64 *data = (u64 *)(&hdev->hw_stats.all_64_bit_stats);
413 struct hclge_desc desc[HCLGE_64_BIT_CMD_NUM];
414 __le64 *desc_data;
415 int i, k, n;
416 int ret;
417
418 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_64_BIT, true);
419 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_64_BIT_CMD_NUM);
420 if (ret) {
421 dev_err(&hdev->pdev->dev,
422 "Get 64 bit pkt stats fail, status = %d.\n", ret);
423 return ret;
424 }
425
426 for (i = 0; i < HCLGE_64_BIT_CMD_NUM; i++) {
427 if (unlikely(i == 0)) {
428 desc_data = (__le64 *)(&desc[i].data[0]);
429 n = HCLGE_64_BIT_RTN_DATANUM - 1;
430 } else {
431 desc_data = (__le64 *)(&desc[i]);
432 n = HCLGE_64_BIT_RTN_DATANUM;
433 }
434 for (k = 0; k < n; k++) {
435 *data++ += le64_to_cpu(*desc_data);
436 desc_data++;
437 }
438 }
439
440 return 0;
441}
442
443static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats *stats)
444{
445 stats->pkt_curr_buf_cnt = 0;
446 stats->pkt_curr_buf_tc0_cnt = 0;
447 stats->pkt_curr_buf_tc1_cnt = 0;
448 stats->pkt_curr_buf_tc2_cnt = 0;
449 stats->pkt_curr_buf_tc3_cnt = 0;
450 stats->pkt_curr_buf_tc4_cnt = 0;
451 stats->pkt_curr_buf_tc5_cnt = 0;
452 stats->pkt_curr_buf_tc6_cnt = 0;
453 stats->pkt_curr_buf_tc7_cnt = 0;
454}
455
456static int hclge_32_bit_update_stats(struct hclge_dev *hdev)
457{
458#define HCLGE_32_BIT_CMD_NUM 8
459#define HCLGE_32_BIT_RTN_DATANUM 8
460
461 struct hclge_desc desc[HCLGE_32_BIT_CMD_NUM];
462 struct hclge_32_bit_stats *all_32_bit_stats;
463 __le32 *desc_data;
464 int i, k, n;
465 u64 *data;
466 int ret;
467
468 all_32_bit_stats = &hdev->hw_stats.all_32_bit_stats;
469 data = (u64 *)(&all_32_bit_stats->egu_tx_1588_pkt);
470
471 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_32_BIT, true);
472 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_32_BIT_CMD_NUM);
473 if (ret) {
474 dev_err(&hdev->pdev->dev,
475 "Get 32 bit pkt stats fail, status = %d.\n", ret);
476
477 return ret;
478 }
479
480 hclge_reset_partial_32bit_counter(all_32_bit_stats);
481 for (i = 0; i < HCLGE_32_BIT_CMD_NUM; i++) {
482 if (unlikely(i == 0)) {
483 __le16 *desc_data_16bit;
484
485 all_32_bit_stats->igu_rx_err_pkt +=
486 le32_to_cpu(desc[i].data[0]);
487
488 desc_data_16bit = (__le16 *)&desc[i].data[1];
489 all_32_bit_stats->igu_rx_no_eof_pkt +=
490 le16_to_cpu(*desc_data_16bit);
491
492 desc_data_16bit++;
493 all_32_bit_stats->igu_rx_no_sof_pkt +=
494 le16_to_cpu(*desc_data_16bit);
495
496 desc_data = &desc[i].data[2];
497 n = HCLGE_32_BIT_RTN_DATANUM - 4;
498 } else {
499 desc_data = (__le32 *)&desc[i];
500 n = HCLGE_32_BIT_RTN_DATANUM;
501 }
502 for (k = 0; k < n; k++) {
503 *data++ += le32_to_cpu(*desc_data);
504 desc_data++;
505 }
506 }
507
508 return 0;
509}
510
511static int hclge_mac_get_traffic_stats(struct hclge_dev *hdev)
512{
513 struct hclge_mac_stats *mac_stats = &hdev->hw_stats.mac_stats;
514 struct hclge_desc desc;
515 __le64 *desc_data;
516 int ret;
517
518 /* for fiber port, need to query the total rx/tx packets statstics,
519 * used for data transferring checking.
520 */
521 if (hdev->hw.mac.media_type != HNAE3_MEDIA_TYPE_FIBER)
522 return 0;
523
524 if (test_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state))
525 return 0;
526
527 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_STATS_MAC_TRAFFIC, true);
528 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
529 if (ret) {
530 dev_err(&hdev->pdev->dev,
531 "Get MAC total pkt stats fail, ret = %d\n", ret);
532
533 return ret;
534 }
535
536 desc_data = (__le64 *)(&desc.data[0]);
537 mac_stats->mac_tx_total_pkt_num += le64_to_cpu(*desc_data++);
538 mac_stats->mac_rx_total_pkt_num += le64_to_cpu(*desc_data);
539
540 return 0;
541}
542
543static int hclge_mac_update_stats(struct hclge_dev *hdev) 232static int hclge_mac_update_stats(struct hclge_dev *hdev)
544{ 233{
545#define HCLGE_MAC_CMD_NUM 21 234#define HCLGE_MAC_CMD_NUM 21
@@ -666,7 +355,7 @@ static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
666 for (i = 0; i < kinfo->num_tqps; i++) { 355 for (i = 0; i < kinfo->num_tqps; i++) {
667 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i], 356 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i],
668 struct hclge_tqp, q); 357 struct hclge_tqp, q);
669 snprintf(buff, ETH_GSTRING_LEN, "txq#%d_pktnum_rcd", 358 snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd",
670 tqp->index); 359 tqp->index);
671 buff = buff + ETH_GSTRING_LEN; 360 buff = buff + ETH_GSTRING_LEN;
672 } 361 }
@@ -674,7 +363,7 @@ static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
674 for (i = 0; i < kinfo->num_tqps; i++) { 363 for (i = 0; i < kinfo->num_tqps; i++) {
675 struct hclge_tqp *tqp = container_of(kinfo->tqp[i], 364 struct hclge_tqp *tqp = container_of(kinfo->tqp[i],
676 struct hclge_tqp, q); 365 struct hclge_tqp, q);
677 snprintf(buff, ETH_GSTRING_LEN, "rxq#%d_pktnum_rcd", 366 snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd",
678 tqp->index); 367 tqp->index);
679 buff = buff + ETH_GSTRING_LEN; 368 buff = buff + ETH_GSTRING_LEN;
680 } 369 }
@@ -718,14 +407,8 @@ static void hclge_update_netstat(struct hclge_hw_stats *hw_stats,
718 struct net_device_stats *net_stats) 407 struct net_device_stats *net_stats)
719{ 408{
720 net_stats->tx_dropped = 0; 409 net_stats->tx_dropped = 0;
721 net_stats->rx_dropped = hw_stats->all_32_bit_stats.ssu_full_drop_num;
722 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ppp_key_drop_num;
723 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ssu_key_drop_num;
724
725 net_stats->rx_errors = hw_stats->mac_stats.mac_rx_oversize_pkt_num; 410 net_stats->rx_errors = hw_stats->mac_stats.mac_rx_oversize_pkt_num;
726 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num; 411 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num;
727 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_eof_pkt;
728 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_sof_pkt;
729 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_fcs_err_pkt_num; 412 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
730 413
731 net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num; 414 net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num;
@@ -760,12 +443,6 @@ static void hclge_update_stats_for_all(struct hclge_dev *hdev)
760 dev_err(&hdev->pdev->dev, 443 dev_err(&hdev->pdev->dev,
761 "Update MAC stats fail, status = %d.\n", status); 444 "Update MAC stats fail, status = %d.\n", status);
762 445
763 status = hclge_32_bit_update_stats(hdev);
764 if (status)
765 dev_err(&hdev->pdev->dev,
766 "Update 32 bit stats fail, status = %d.\n",
767 status);
768
769 hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats); 446 hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats);
770} 447}
771 448
@@ -786,18 +463,6 @@ static void hclge_update_stats(struct hnae3_handle *handle,
786 "Update MAC stats fail, status = %d.\n", 463 "Update MAC stats fail, status = %d.\n",
787 status); 464 status);
788 465
789 status = hclge_32_bit_update_stats(hdev);
790 if (status)
791 dev_err(&hdev->pdev->dev,
792 "Update 32 bit stats fail, status = %d.\n",
793 status);
794
795 status = hclge_64_bit_update_stats(hdev);
796 if (status)
797 dev_err(&hdev->pdev->dev,
798 "Update 64 bit stats fail, status = %d.\n",
799 status);
800
801 status = hclge_tqps_update_stats(handle); 466 status = hclge_tqps_update_stats(handle);
802 if (status) 467 if (status)
803 dev_err(&hdev->pdev->dev, 468 dev_err(&hdev->pdev->dev,
@@ -811,7 +476,10 @@ static void hclge_update_stats(struct hnae3_handle *handle,
811 476
812static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset) 477static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
813{ 478{
814#define HCLGE_LOOPBACK_TEST_FLAGS 0x7 479#define HCLGE_LOOPBACK_TEST_FLAGS (HNAE3_SUPPORT_APP_LOOPBACK |\
480 HNAE3_SUPPORT_PHY_LOOPBACK |\
481 HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK |\
482 HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK)
815 483
816 struct hclge_vport *vport = hclge_get_vport(handle); 484 struct hclge_vport *vport = hclge_get_vport(handle);
817 struct hclge_dev *hdev = vport->back; 485 struct hclge_dev *hdev = vport->back;
@@ -825,18 +493,19 @@ static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
825 if (stringset == ETH_SS_TEST) { 493 if (stringset == ETH_SS_TEST) {
826 /* clear loopback bit flags at first */ 494 /* clear loopback bit flags at first */
827 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS)); 495 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
828 if (hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M || 496 if (hdev->pdev->revision >= 0x21 ||
497 hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
829 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M || 498 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
830 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) { 499 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
831 count += 1; 500 count += 1;
832 handle->flags |= HNAE3_SUPPORT_MAC_LOOPBACK; 501 handle->flags |= HNAE3_SUPPORT_APP_LOOPBACK;
833 } else {
834 count = -EOPNOTSUPP;
835 } 502 }
503
504 count += 2;
505 handle->flags |= HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK;
506 handle->flags |= HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK;
836 } else if (stringset == ETH_SS_STATS) { 507 } else if (stringset == ETH_SS_STATS) {
837 count = ARRAY_SIZE(g_mac_stats_string) + 508 count = ARRAY_SIZE(g_mac_stats_string) +
838 ARRAY_SIZE(g_all_32bit_stats_string) +
839 ARRAY_SIZE(g_all_64bit_stats_string) +
840 hclge_tqps_get_sset_count(handle, stringset); 509 hclge_tqps_get_sset_count(handle, stringset);
841 } 510 }
842 511
@@ -856,33 +525,29 @@ static void hclge_get_strings(struct hnae3_handle *handle,
856 g_mac_stats_string, 525 g_mac_stats_string,
857 size, 526 size,
858 p); 527 p);
859 size = ARRAY_SIZE(g_all_32bit_stats_string);
860 p = hclge_comm_get_strings(stringset,
861 g_all_32bit_stats_string,
862 size,
863 p);
864 size = ARRAY_SIZE(g_all_64bit_stats_string);
865 p = hclge_comm_get_strings(stringset,
866 g_all_64bit_stats_string,
867 size,
868 p);
869 p = hclge_tqps_get_strings(handle, p); 528 p = hclge_tqps_get_strings(handle, p);
870 } else if (stringset == ETH_SS_TEST) { 529 } else if (stringset == ETH_SS_TEST) {
871 if (handle->flags & HNAE3_SUPPORT_MAC_LOOPBACK) { 530 if (handle->flags & HNAE3_SUPPORT_APP_LOOPBACK) {
531 memcpy(p,
532 hns3_nic_test_strs[HNAE3_LOOP_APP],
533 ETH_GSTRING_LEN);
534 p += ETH_GSTRING_LEN;
535 }
536 if (handle->flags & HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK) {
872 memcpy(p, 537 memcpy(p,
873 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_MAC], 538 hns3_nic_test_strs[HNAE3_LOOP_SERIAL_SERDES],
874 ETH_GSTRING_LEN); 539 ETH_GSTRING_LEN);
875 p += ETH_GSTRING_LEN; 540 p += ETH_GSTRING_LEN;
876 } 541 }
877 if (handle->flags & HNAE3_SUPPORT_SERDES_LOOPBACK) { 542 if (handle->flags & HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK) {
878 memcpy(p, 543 memcpy(p,
879 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_SERDES], 544 hns3_nic_test_strs[HNAE3_LOOP_PARALLEL_SERDES],
880 ETH_GSTRING_LEN); 545 ETH_GSTRING_LEN);
881 p += ETH_GSTRING_LEN; 546 p += ETH_GSTRING_LEN;
882 } 547 }
883 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) { 548 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
884 memcpy(p, 549 memcpy(p,
885 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_PHY], 550 hns3_nic_test_strs[HNAE3_LOOP_PHY],
886 ETH_GSTRING_LEN); 551 ETH_GSTRING_LEN);
887 p += ETH_GSTRING_LEN; 552 p += ETH_GSTRING_LEN;
888 } 553 }
@@ -899,14 +564,6 @@ static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
899 g_mac_stats_string, 564 g_mac_stats_string,
900 ARRAY_SIZE(g_mac_stats_string), 565 ARRAY_SIZE(g_mac_stats_string),
901 data); 566 data);
902 p = hclge_comm_get_stats(&hdev->hw_stats.all_32_bit_stats,
903 g_all_32bit_stats_string,
904 ARRAY_SIZE(g_all_32bit_stats_string),
905 p);
906 p = hclge_comm_get_stats(&hdev->hw_stats.all_64_bit_stats,
907 g_all_64bit_stats_string,
908 ARRAY_SIZE(g_all_64bit_stats_string),
909 p);
910 p = hclge_tqps_get_stats(handle, p); 567 p = hclge_tqps_get_stats(handle, p);
911} 568}
912 569
@@ -975,18 +632,22 @@ static int hclge_query_pf_resource(struct hclge_dev *hdev)
975 hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S; 632 hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
976 633
977 if (hnae3_dev_roce_supported(hdev)) { 634 if (hnae3_dev_roce_supported(hdev)) {
635 hdev->roce_base_msix_offset =
636 hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee),
637 HCLGE_MSIX_OFT_ROCEE_M, HCLGE_MSIX_OFT_ROCEE_S);
978 hdev->num_roce_msi = 638 hdev->num_roce_msi =
979 hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number), 639 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
980 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S); 640 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
981 641
982 /* PF should have NIC vectors and Roce vectors, 642 /* PF should have NIC vectors and Roce vectors,
983 * NIC vectors are queued before Roce vectors. 643 * NIC vectors are queued before Roce vectors.
984 */ 644 */
985 hdev->num_msi = hdev->num_roce_msi + HCLGE_ROCE_VECTOR_OFFSET; 645 hdev->num_msi = hdev->num_roce_msi +
646 hdev->roce_base_msix_offset;
986 } else { 647 } else {
987 hdev->num_msi = 648 hdev->num_msi =
988 hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number), 649 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
989 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S); 650 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
990 } 651 }
991 652
992 return 0; 653 return 0;
@@ -1075,38 +736,38 @@ static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
1075 req = (struct hclge_cfg_param_cmd *)desc[0].data; 736 req = (struct hclge_cfg_param_cmd *)desc[0].data;
1076 737
1077 /* get the configuration */ 738 /* get the configuration */
1078 cfg->vmdq_vport_num = hnae_get_field(__le32_to_cpu(req->param[0]), 739 cfg->vmdq_vport_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
1079 HCLGE_CFG_VMDQ_M, 740 HCLGE_CFG_VMDQ_M,
1080 HCLGE_CFG_VMDQ_S); 741 HCLGE_CFG_VMDQ_S);
1081 cfg->tc_num = hnae_get_field(__le32_to_cpu(req->param[0]), 742 cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
1082 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S); 743 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
1083 cfg->tqp_desc_num = hnae_get_field(__le32_to_cpu(req->param[0]), 744 cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
1084 HCLGE_CFG_TQP_DESC_N_M, 745 HCLGE_CFG_TQP_DESC_N_M,
1085 HCLGE_CFG_TQP_DESC_N_S); 746 HCLGE_CFG_TQP_DESC_N_S);
1086 747
1087 cfg->phy_addr = hnae_get_field(__le32_to_cpu(req->param[1]), 748 cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]),
1088 HCLGE_CFG_PHY_ADDR_M, 749 HCLGE_CFG_PHY_ADDR_M,
1089 HCLGE_CFG_PHY_ADDR_S); 750 HCLGE_CFG_PHY_ADDR_S);
1090 cfg->media_type = hnae_get_field(__le32_to_cpu(req->param[1]), 751 cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]),
1091 HCLGE_CFG_MEDIA_TP_M, 752 HCLGE_CFG_MEDIA_TP_M,
1092 HCLGE_CFG_MEDIA_TP_S); 753 HCLGE_CFG_MEDIA_TP_S);
1093 cfg->rx_buf_len = hnae_get_field(__le32_to_cpu(req->param[1]), 754 cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]),
1094 HCLGE_CFG_RX_BUF_LEN_M, 755 HCLGE_CFG_RX_BUF_LEN_M,
1095 HCLGE_CFG_RX_BUF_LEN_S); 756 HCLGE_CFG_RX_BUF_LEN_S);
1096 /* get mac_address */ 757 /* get mac_address */
1097 mac_addr_tmp = __le32_to_cpu(req->param[2]); 758 mac_addr_tmp = __le32_to_cpu(req->param[2]);
1098 mac_addr_tmp_high = hnae_get_field(__le32_to_cpu(req->param[3]), 759 mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]),
1099 HCLGE_CFG_MAC_ADDR_H_M, 760 HCLGE_CFG_MAC_ADDR_H_M,
1100 HCLGE_CFG_MAC_ADDR_H_S); 761 HCLGE_CFG_MAC_ADDR_H_S);
1101 762
1102 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1; 763 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
1103 764
1104 cfg->default_speed = hnae_get_field(__le32_to_cpu(req->param[3]), 765 cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]),
1105 HCLGE_CFG_DEFAULT_SPEED_M, 766 HCLGE_CFG_DEFAULT_SPEED_M,
1106 HCLGE_CFG_DEFAULT_SPEED_S); 767 HCLGE_CFG_DEFAULT_SPEED_S);
1107 cfg->rss_size_max = hnae_get_field(__le32_to_cpu(req->param[3]), 768 cfg->rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]),
1108 HCLGE_CFG_RSS_SIZE_M, 769 HCLGE_CFG_RSS_SIZE_M,
1109 HCLGE_CFG_RSS_SIZE_S); 770 HCLGE_CFG_RSS_SIZE_S);
1110 771
1111 for (i = 0; i < ETH_ALEN; i++) 772 for (i = 0; i < ETH_ALEN; i++)
1112 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff; 773 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
@@ -1114,9 +775,14 @@ static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
1114 req = (struct hclge_cfg_param_cmd *)desc[1].data; 775 req = (struct hclge_cfg_param_cmd *)desc[1].data;
1115 cfg->numa_node_map = __le32_to_cpu(req->param[0]); 776 cfg->numa_node_map = __le32_to_cpu(req->param[0]);
1116 777
1117 cfg->speed_ability = hnae_get_field(__le32_to_cpu(req->param[1]), 778 cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]),
1118 HCLGE_CFG_SPEED_ABILITY_M, 779 HCLGE_CFG_SPEED_ABILITY_M,
1119 HCLGE_CFG_SPEED_ABILITY_S); 780 HCLGE_CFG_SPEED_ABILITY_S);
781 cfg->umv_space = hnae3_get_field(__le32_to_cpu(req->param[1]),
782 HCLGE_CFG_UMV_TBL_SPACE_M,
783 HCLGE_CFG_UMV_TBL_SPACE_S);
784 if (!cfg->umv_space)
785 cfg->umv_space = HCLGE_DEFAULT_UMV_SPACE_PER_PF;
1120} 786}
1121 787
1122/* hclge_get_cfg: query the static parameter from flash 788/* hclge_get_cfg: query the static parameter from flash
@@ -1135,22 +801,22 @@ static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
1135 req = (struct hclge_cfg_param_cmd *)desc[i].data; 801 req = (struct hclge_cfg_param_cmd *)desc[i].data;
1136 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM, 802 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
1137 true); 803 true);
1138 hnae_set_field(offset, HCLGE_CFG_OFFSET_M, 804 hnae3_set_field(offset, HCLGE_CFG_OFFSET_M,
1139 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES); 805 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
1140 /* Len should be united by 4 bytes when send to hardware */ 806 /* Len should be united by 4 bytes when send to hardware */
1141 hnae_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S, 807 hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S,
1142 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT); 808 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
1143 req->offset = cpu_to_le32(offset); 809 req->offset = cpu_to_le32(offset);
1144 } 810 }
1145 811
1146 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM); 812 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
1147 if (ret) { 813 if (ret) {
1148 dev_err(&hdev->pdev->dev, 814 dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret);
1149 "get config failed %d.\n", ret);
1150 return ret; 815 return ret;
1151 } 816 }
1152 817
1153 hclge_parse_cfg(hcfg, desc); 818 hclge_parse_cfg(hcfg, desc);
819
1154 return 0; 820 return 0;
1155} 821}
1156 822
@@ -1167,13 +833,10 @@ static int hclge_get_cap(struct hclge_dev *hdev)
1167 833
1168 /* get pf resource */ 834 /* get pf resource */
1169 ret = hclge_query_pf_resource(hdev); 835 ret = hclge_query_pf_resource(hdev);
1170 if (ret) { 836 if (ret)
1171 dev_err(&hdev->pdev->dev, 837 dev_err(&hdev->pdev->dev, "query pf resource error %d.\n", ret);
1172 "query pf resource error %d.\n", ret);
1173 return ret;
1174 }
1175 838
1176 return 0; 839 return ret;
1177} 840}
1178 841
1179static int hclge_configure(struct hclge_dev *hdev) 842static int hclge_configure(struct hclge_dev *hdev)
@@ -1198,6 +861,7 @@ static int hclge_configure(struct hclge_dev *hdev)
1198 hdev->tm_info.num_pg = 1; 861 hdev->tm_info.num_pg = 1;
1199 hdev->tc_max = cfg.tc_num; 862 hdev->tc_max = cfg.tc_num;
1200 hdev->tm_info.hw_pfc_map = 0; 863 hdev->tm_info.hw_pfc_map = 0;
864 hdev->wanted_umv_size = cfg.umv_space;
1201 865
1202 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed); 866 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
1203 if (ret) { 867 if (ret) {
@@ -1226,7 +890,7 @@ static int hclge_configure(struct hclge_dev *hdev)
1226 890
1227 /* Currently not support uncontiuous tc */ 891 /* Currently not support uncontiuous tc */
1228 for (i = 0; i < hdev->tm_info.num_tc; i++) 892 for (i = 0; i < hdev->tm_info.num_tc; i++)
1229 hnae_set_bit(hdev->hw_tc_map, i, 1); 893 hnae3_set_bit(hdev->hw_tc_map, i, 1);
1230 894
1231 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE; 895 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
1232 896
@@ -1245,13 +909,13 @@ static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min,
1245 req = (struct hclge_cfg_tso_status_cmd *)desc.data; 909 req = (struct hclge_cfg_tso_status_cmd *)desc.data;
1246 910
1247 tso_mss = 0; 911 tso_mss = 0;
1248 hnae_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M, 912 hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
1249 HCLGE_TSO_MSS_MIN_S, tso_mss_min); 913 HCLGE_TSO_MSS_MIN_S, tso_mss_min);
1250 req->tso_mss_min = cpu_to_le16(tso_mss); 914 req->tso_mss_min = cpu_to_le16(tso_mss);
1251 915
1252 tso_mss = 0; 916 tso_mss = 0;
1253 hnae_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M, 917 hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
1254 HCLGE_TSO_MSS_MIN_S, tso_mss_max); 918 HCLGE_TSO_MSS_MIN_S, tso_mss_max);
1255 req->tso_mss_max = cpu_to_le16(tso_mss); 919 req->tso_mss_max = cpu_to_le16(tso_mss);
1256 920
1257 return hclge_cmd_send(&hdev->hw, &desc, 1); 921 return hclge_cmd_send(&hdev->hw, &desc, 1);
@@ -1302,44 +966,43 @@ static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
1302 req->tqp_vid = cpu_to_le16(tqp_vid); 966 req->tqp_vid = cpu_to_le16(tqp_vid);
1303 967
1304 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 968 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1305 if (ret) { 969 if (ret)
1306 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", 970 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", ret);
1307 ret);
1308 return ret;
1309 }
1310 971
1311 return 0; 972 return ret;
1312} 973}
1313 974
1314static int hclge_assign_tqp(struct hclge_vport *vport, 975static int hclge_assign_tqp(struct hclge_vport *vport)
1315 struct hnae3_queue **tqp, u16 num_tqps)
1316{ 976{
977 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
1317 struct hclge_dev *hdev = vport->back; 978 struct hclge_dev *hdev = vport->back;
1318 int i, alloced; 979 int i, alloced;
1319 980
1320 for (i = 0, alloced = 0; i < hdev->num_tqps && 981 for (i = 0, alloced = 0; i < hdev->num_tqps &&
1321 alloced < num_tqps; i++) { 982 alloced < kinfo->num_tqps; i++) {
1322 if (!hdev->htqp[i].alloced) { 983 if (!hdev->htqp[i].alloced) {
1323 hdev->htqp[i].q.handle = &vport->nic; 984 hdev->htqp[i].q.handle = &vport->nic;
1324 hdev->htqp[i].q.tqp_index = alloced; 985 hdev->htqp[i].q.tqp_index = alloced;
1325 tqp[alloced] = &hdev->htqp[i].q; 986 hdev->htqp[i].q.desc_num = kinfo->num_desc;
987 kinfo->tqp[alloced] = &hdev->htqp[i].q;
1326 hdev->htqp[i].alloced = true; 988 hdev->htqp[i].alloced = true;
1327 alloced++; 989 alloced++;
1328 } 990 }
1329 } 991 }
1330 vport->alloc_tqps = num_tqps; 992 vport->alloc_tqps = kinfo->num_tqps;
1331 993
1332 return 0; 994 return 0;
1333} 995}
1334 996
1335static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps) 997static int hclge_knic_setup(struct hclge_vport *vport,
998 u16 num_tqps, u16 num_desc)
1336{ 999{
1337 struct hnae3_handle *nic = &vport->nic; 1000 struct hnae3_handle *nic = &vport->nic;
1338 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 1001 struct hnae3_knic_private_info *kinfo = &nic->kinfo;
1339 struct hclge_dev *hdev = vport->back; 1002 struct hclge_dev *hdev = vport->back;
1340 int i, ret; 1003 int i, ret;
1341 1004
1342 kinfo->num_desc = hdev->num_desc; 1005 kinfo->num_desc = num_desc;
1343 kinfo->rx_buf_len = hdev->rx_buf_len; 1006 kinfo->rx_buf_len = hdev->rx_buf_len;
1344 kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc); 1007 kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc);
1345 kinfo->rss_size 1008 kinfo->rss_size
@@ -1366,13 +1029,11 @@ static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps)
1366 if (!kinfo->tqp) 1029 if (!kinfo->tqp)
1367 return -ENOMEM; 1030 return -ENOMEM;
1368 1031
1369 ret = hclge_assign_tqp(vport, kinfo->tqp, kinfo->num_tqps); 1032 ret = hclge_assign_tqp(vport);
1370 if (ret) { 1033 if (ret)
1371 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret); 1034 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
1372 return -EINVAL;
1373 }
1374 1035
1375 return 0; 1036 return ret;
1376} 1037}
1377 1038
1378static int hclge_map_tqp_to_vport(struct hclge_dev *hdev, 1039static int hclge_map_tqp_to_vport(struct hclge_dev *hdev,
@@ -1434,7 +1095,7 @@ static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
1434 nic->numa_node_mask = hdev->numa_node_mask; 1095 nic->numa_node_mask = hdev->numa_node_mask;
1435 1096
1436 if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) { 1097 if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) {
1437 ret = hclge_knic_setup(vport, num_tqps); 1098 ret = hclge_knic_setup(vport, num_tqps, hdev->num_desc);
1438 if (ret) { 1099 if (ret) {
1439 dev_err(&hdev->pdev->dev, "knic setup failed %d\n", 1100 dev_err(&hdev->pdev->dev, "knic setup failed %d\n",
1440 ret); 1101 ret);
@@ -1459,8 +1120,11 @@ static int hclge_alloc_vport(struct hclge_dev *hdev)
1459 /* We need to alloc a vport for main NIC of PF */ 1120 /* We need to alloc a vport for main NIC of PF */
1460 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1; 1121 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1461 1122
1462 if (hdev->num_tqps < num_vport) 1123 if (hdev->num_tqps < num_vport) {
1463 num_vport = hdev->num_tqps; 1124 dev_err(&hdev->pdev->dev, "tqps(%d) is less than vports(%d)",
1125 hdev->num_tqps, num_vport);
1126 return -EINVAL;
1127 }
1464 1128
1465 /* Alloc the same number of TQPs for every vport */ 1129 /* Alloc the same number of TQPs for every vport */
1466 tqp_per_vport = hdev->num_tqps / num_vport; 1130 tqp_per_vport = hdev->num_tqps / num_vport;
@@ -1474,21 +1138,8 @@ static int hclge_alloc_vport(struct hclge_dev *hdev)
1474 hdev->vport = vport; 1138 hdev->vport = vport;
1475 hdev->num_alloc_vport = num_vport; 1139 hdev->num_alloc_vport = num_vport;
1476 1140
1477#ifdef CONFIG_PCI_IOV 1141 if (IS_ENABLED(CONFIG_PCI_IOV))
1478 /* Enable SRIOV */ 1142 hdev->num_alloc_vfs = hdev->num_req_vfs;
1479 if (hdev->num_req_vfs) {
1480 dev_info(&pdev->dev, "active VFs(%d) found, enabling SRIOV\n",
1481 hdev->num_req_vfs);
1482 ret = pci_enable_sriov(hdev->pdev, hdev->num_req_vfs);
1483 if (ret) {
1484 hdev->num_alloc_vfs = 0;
1485 dev_err(&pdev->dev, "SRIOV enable failed %d\n",
1486 ret);
1487 return ret;
1488 }
1489 }
1490 hdev->num_alloc_vfs = hdev->num_req_vfs;
1491#endif
1492 1143
1493 for (i = 0; i < num_vport; i++) { 1144 for (i = 0; i < num_vport; i++) {
1494 vport->back = hdev; 1145 vport->back = hdev;
@@ -1534,13 +1185,11 @@ static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev,
1534 } 1185 }
1535 1186
1536 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1187 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1537 if (ret) { 1188 if (ret)
1538 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n", 1189 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
1539 ret); 1190 ret);
1540 return ret;
1541 }
1542 1191
1543 return 0; 1192 return ret;
1544} 1193}
1545 1194
1546static int hclge_tx_buffer_alloc(struct hclge_dev *hdev, 1195static int hclge_tx_buffer_alloc(struct hclge_dev *hdev,
@@ -1548,13 +1197,10 @@ static int hclge_tx_buffer_alloc(struct hclge_dev *hdev,
1548{ 1197{
1549 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc); 1198 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc);
1550 1199
1551 if (ret) { 1200 if (ret)
1552 dev_err(&hdev->pdev->dev, 1201 dev_err(&hdev->pdev->dev, "tx buffer alloc failed %d\n", ret);
1553 "tx buffer alloc failed %d\n", ret);
1554 return ret;
1555 }
1556 1202
1557 return 0; 1203 return ret;
1558} 1204}
1559 1205
1560static int hclge_get_tc_num(struct hclge_dev *hdev) 1206static int hclge_get_tc_num(struct hclge_dev *hdev)
@@ -1716,11 +1362,13 @@ static int hclge_tx_buffer_calc(struct hclge_dev *hdev,
1716static int hclge_rx_buffer_calc(struct hclge_dev *hdev, 1362static int hclge_rx_buffer_calc(struct hclge_dev *hdev,
1717 struct hclge_pkt_buf_alloc *buf_alloc) 1363 struct hclge_pkt_buf_alloc *buf_alloc)
1718{ 1364{
1719 u32 rx_all = hdev->pkt_buf_size; 1365#define HCLGE_BUF_SIZE_UNIT 128
1366 u32 rx_all = hdev->pkt_buf_size, aligned_mps;
1720 int no_pfc_priv_num, pfc_priv_num; 1367 int no_pfc_priv_num, pfc_priv_num;
1721 struct hclge_priv_buf *priv; 1368 struct hclge_priv_buf *priv;
1722 int i; 1369 int i;
1723 1370
1371 aligned_mps = round_up(hdev->mps, HCLGE_BUF_SIZE_UNIT);
1724 rx_all -= hclge_get_tx_buff_alloced(buf_alloc); 1372 rx_all -= hclge_get_tx_buff_alloced(buf_alloc);
1725 1373
1726 /* When DCB is not supported, rx private 1374 /* When DCB is not supported, rx private
@@ -1739,13 +1387,13 @@ static int hclge_rx_buffer_calc(struct hclge_dev *hdev,
1739 if (hdev->hw_tc_map & BIT(i)) { 1387 if (hdev->hw_tc_map & BIT(i)) {
1740 priv->enable = 1; 1388 priv->enable = 1;
1741 if (hdev->tm_info.hw_pfc_map & BIT(i)) { 1389 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1742 priv->wl.low = hdev->mps; 1390 priv->wl.low = aligned_mps;
1743 priv->wl.high = priv->wl.low + hdev->mps; 1391 priv->wl.high = priv->wl.low + aligned_mps;
1744 priv->buf_size = priv->wl.high + 1392 priv->buf_size = priv->wl.high +
1745 HCLGE_DEFAULT_DV; 1393 HCLGE_DEFAULT_DV;
1746 } else { 1394 } else {
1747 priv->wl.low = 0; 1395 priv->wl.low = 0;
1748 priv->wl.high = 2 * hdev->mps; 1396 priv->wl.high = 2 * aligned_mps;
1749 priv->buf_size = priv->wl.high; 1397 priv->buf_size = priv->wl.high;
1750 } 1398 }
1751 } else { 1399 } else {
@@ -1777,11 +1425,11 @@ static int hclge_rx_buffer_calc(struct hclge_dev *hdev,
1777 1425
1778 if (hdev->tm_info.hw_pfc_map & BIT(i)) { 1426 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1779 priv->wl.low = 128; 1427 priv->wl.low = 128;
1780 priv->wl.high = priv->wl.low + hdev->mps; 1428 priv->wl.high = priv->wl.low + aligned_mps;
1781 priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV; 1429 priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV;
1782 } else { 1430 } else {
1783 priv->wl.low = 0; 1431 priv->wl.low = 0;
1784 priv->wl.high = hdev->mps; 1432 priv->wl.high = aligned_mps;
1785 priv->buf_size = priv->wl.high; 1433 priv->buf_size = priv->wl.high;
1786 } 1434 }
1787 } 1435 }
@@ -1872,17 +1520,13 @@ static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev,
1872 (1 << HCLGE_TC0_PRI_BUF_EN_B)); 1520 (1 << HCLGE_TC0_PRI_BUF_EN_B));
1873 1521
1874 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1522 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1875 if (ret) { 1523 if (ret)
1876 dev_err(&hdev->pdev->dev, 1524 dev_err(&hdev->pdev->dev,
1877 "rx private buffer alloc cmd failed %d\n", ret); 1525 "rx private buffer alloc cmd failed %d\n", ret);
1878 return ret;
1879 }
1880 1526
1881 return 0; 1527 return ret;
1882} 1528}
1883 1529
1884#define HCLGE_PRIV_ENABLE(a) ((a) > 0 ? 1 : 0)
1885
1886static int hclge_rx_priv_wl_config(struct hclge_dev *hdev, 1530static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
1887 struct hclge_pkt_buf_alloc *buf_alloc) 1531 struct hclge_pkt_buf_alloc *buf_alloc)
1888{ 1532{
@@ -1910,25 +1554,21 @@ static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
1910 req->tc_wl[j].high = 1554 req->tc_wl[j].high =
1911 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S); 1555 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
1912 req->tc_wl[j].high |= 1556 req->tc_wl[j].high |=
1913 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.high) << 1557 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1914 HCLGE_RX_PRIV_EN_B);
1915 req->tc_wl[j].low = 1558 req->tc_wl[j].low =
1916 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S); 1559 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
1917 req->tc_wl[j].low |= 1560 req->tc_wl[j].low |=
1918 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.low) << 1561 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1919 HCLGE_RX_PRIV_EN_B);
1920 } 1562 }
1921 } 1563 }
1922 1564
1923 /* Send 2 descriptor at one time */ 1565 /* Send 2 descriptor at one time */
1924 ret = hclge_cmd_send(&hdev->hw, desc, 2); 1566 ret = hclge_cmd_send(&hdev->hw, desc, 2);
1925 if (ret) { 1567 if (ret)
1926 dev_err(&hdev->pdev->dev, 1568 dev_err(&hdev->pdev->dev,
1927 "rx private waterline config cmd failed %d\n", 1569 "rx private waterline config cmd failed %d\n",
1928 ret); 1570 ret);
1929 return ret; 1571 return ret;
1930 }
1931 return 0;
1932} 1572}
1933 1573
1934static int hclge_common_thrd_config(struct hclge_dev *hdev, 1574static int hclge_common_thrd_config(struct hclge_dev *hdev,
@@ -1958,24 +1598,20 @@ static int hclge_common_thrd_config(struct hclge_dev *hdev,
1958 req->com_thrd[j].high = 1598 req->com_thrd[j].high =
1959 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S); 1599 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
1960 req->com_thrd[j].high |= 1600 req->com_thrd[j].high |=
1961 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->high) << 1601 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1962 HCLGE_RX_PRIV_EN_B);
1963 req->com_thrd[j].low = 1602 req->com_thrd[j].low =
1964 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S); 1603 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
1965 req->com_thrd[j].low |= 1604 req->com_thrd[j].low |=
1966 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->low) << 1605 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1967 HCLGE_RX_PRIV_EN_B);
1968 } 1606 }
1969 } 1607 }
1970 1608
1971 /* Send 2 descriptors at one time */ 1609 /* Send 2 descriptors at one time */
1972 ret = hclge_cmd_send(&hdev->hw, desc, 2); 1610 ret = hclge_cmd_send(&hdev->hw, desc, 2);
1973 if (ret) { 1611 if (ret)
1974 dev_err(&hdev->pdev->dev, 1612 dev_err(&hdev->pdev->dev,
1975 "common threshold config cmd failed %d\n", ret); 1613 "common threshold config cmd failed %d\n", ret);
1976 return ret; 1614 return ret;
1977 }
1978 return 0;
1979} 1615}
1980 1616
1981static int hclge_common_wl_config(struct hclge_dev *hdev, 1617static int hclge_common_wl_config(struct hclge_dev *hdev,
@@ -1990,23 +1626,17 @@ static int hclge_common_wl_config(struct hclge_dev *hdev,
1990 1626
1991 req = (struct hclge_rx_com_wl *)desc.data; 1627 req = (struct hclge_rx_com_wl *)desc.data;
1992 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S); 1628 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
1993 req->com_wl.high |= 1629 req->com_wl.high |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1994 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.high) <<
1995 HCLGE_RX_PRIV_EN_B);
1996 1630
1997 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S); 1631 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
1998 req->com_wl.low |= 1632 req->com_wl.low |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1999 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.low) <<
2000 HCLGE_RX_PRIV_EN_B);
2001 1633
2002 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1634 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2003 if (ret) { 1635 if (ret)
2004 dev_err(&hdev->pdev->dev, 1636 dev_err(&hdev->pdev->dev,
2005 "common waterline config cmd failed %d\n", ret); 1637 "common waterline config cmd failed %d\n", ret);
2006 return ret;
2007 }
2008 1638
2009 return 0; 1639 return ret;
2010} 1640}
2011 1641
2012int hclge_buffer_alloc(struct hclge_dev *hdev) 1642int hclge_buffer_alloc(struct hclge_dev *hdev)
@@ -2121,7 +1751,7 @@ static int hclge_init_msi(struct hclge_dev *hdev)
2121 hdev->num_msi_left = vectors; 1751 hdev->num_msi_left = vectors;
2122 hdev->base_msi_vector = pdev->irq; 1752 hdev->base_msi_vector = pdev->irq;
2123 hdev->roce_base_vector = hdev->base_msi_vector + 1753 hdev->roce_base_vector = hdev->base_msi_vector +
2124 HCLGE_ROCE_VECTOR_OFFSET; 1754 hdev->roce_base_msix_offset;
2125 1755
2126 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 1756 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
2127 sizeof(u16), GFP_KERNEL); 1757 sizeof(u16), GFP_KERNEL);
@@ -2143,19 +1773,17 @@ static int hclge_init_msi(struct hclge_dev *hdev)
2143 return 0; 1773 return 0;
2144} 1774}
2145 1775
2146static void hclge_check_speed_dup(struct hclge_dev *hdev, int duplex, int speed) 1776static u8 hclge_check_speed_dup(u8 duplex, int speed)
2147{ 1777{
2148 struct hclge_mac *mac = &hdev->hw.mac;
2149 1778
2150 if ((speed == HCLGE_MAC_SPEED_10M) || (speed == HCLGE_MAC_SPEED_100M)) 1779 if (!(speed == HCLGE_MAC_SPEED_10M || speed == HCLGE_MAC_SPEED_100M))
2151 mac->duplex = (u8)duplex; 1780 duplex = HCLGE_MAC_FULL;
2152 else
2153 mac->duplex = HCLGE_MAC_FULL;
2154 1781
2155 mac->speed = speed; 1782 return duplex;
2156} 1783}
2157 1784
2158int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex) 1785static int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed,
1786 u8 duplex)
2159{ 1787{
2160 struct hclge_config_mac_speed_dup_cmd *req; 1788 struct hclge_config_mac_speed_dup_cmd *req;
2161 struct hclge_desc desc; 1789 struct hclge_desc desc;
@@ -2165,48 +1793,48 @@ int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
2165 1793
2166 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false); 1794 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
2167 1795
2168 hnae_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex); 1796 hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex);
2169 1797
2170 switch (speed) { 1798 switch (speed) {
2171 case HCLGE_MAC_SPEED_10M: 1799 case HCLGE_MAC_SPEED_10M:
2172 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 1800 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2173 HCLGE_CFG_SPEED_S, 6); 1801 HCLGE_CFG_SPEED_S, 6);
2174 break; 1802 break;
2175 case HCLGE_MAC_SPEED_100M: 1803 case HCLGE_MAC_SPEED_100M:
2176 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 1804 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2177 HCLGE_CFG_SPEED_S, 7); 1805 HCLGE_CFG_SPEED_S, 7);
2178 break; 1806 break;
2179 case HCLGE_MAC_SPEED_1G: 1807 case HCLGE_MAC_SPEED_1G:
2180 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 1808 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2181 HCLGE_CFG_SPEED_S, 0); 1809 HCLGE_CFG_SPEED_S, 0);
2182 break; 1810 break;
2183 case HCLGE_MAC_SPEED_10G: 1811 case HCLGE_MAC_SPEED_10G:
2184 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 1812 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2185 HCLGE_CFG_SPEED_S, 1); 1813 HCLGE_CFG_SPEED_S, 1);
2186 break; 1814 break;
2187 case HCLGE_MAC_SPEED_25G: 1815 case HCLGE_MAC_SPEED_25G:
2188 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 1816 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2189 HCLGE_CFG_SPEED_S, 2); 1817 HCLGE_CFG_SPEED_S, 2);
2190 break; 1818 break;
2191 case HCLGE_MAC_SPEED_40G: 1819 case HCLGE_MAC_SPEED_40G:
2192 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 1820 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2193 HCLGE_CFG_SPEED_S, 3); 1821 HCLGE_CFG_SPEED_S, 3);
2194 break; 1822 break;
2195 case HCLGE_MAC_SPEED_50G: 1823 case HCLGE_MAC_SPEED_50G:
2196 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 1824 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2197 HCLGE_CFG_SPEED_S, 4); 1825 HCLGE_CFG_SPEED_S, 4);
2198 break; 1826 break;
2199 case HCLGE_MAC_SPEED_100G: 1827 case HCLGE_MAC_SPEED_100G:
2200 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 1828 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2201 HCLGE_CFG_SPEED_S, 5); 1829 HCLGE_CFG_SPEED_S, 5);
2202 break; 1830 break;
2203 default: 1831 default:
2204 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed); 1832 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
2205 return -EINVAL; 1833 return -EINVAL;
2206 } 1834 }
2207 1835
2208 hnae_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B, 1836 hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
2209 1); 1837 1);
2210 1838
2211 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1839 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2212 if (ret) { 1840 if (ret) {
@@ -2215,7 +1843,23 @@ int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
2215 return ret; 1843 return ret;
2216 } 1844 }
2217 1845
2218 hclge_check_speed_dup(hdev, duplex, speed); 1846 return 0;
1847}
1848
1849int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
1850{
1851 int ret;
1852
1853 duplex = hclge_check_speed_dup(duplex, speed);
1854 if (hdev->hw.mac.speed == speed && hdev->hw.mac.duplex == duplex)
1855 return 0;
1856
1857 ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex);
1858 if (ret)
1859 return ret;
1860
1861 hdev->hw.mac.speed = speed;
1862 hdev->hw.mac.duplex = duplex;
2219 1863
2220 return 0; 1864 return 0;
2221} 1865}
@@ -2248,18 +1892,16 @@ static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed,
2248 return ret; 1892 return ret;
2249 } 1893 }
2250 1894
2251 *duplex = hnae_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B); 1895 *duplex = hnae3_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B);
2252 speed_tmp = hnae_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M, 1896 speed_tmp = hnae3_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M,
2253 HCLGE_QUERY_SPEED_S); 1897 HCLGE_QUERY_SPEED_S);
2254 1898
2255 ret = hclge_parse_speed(speed_tmp, speed); 1899 ret = hclge_parse_speed(speed_tmp, speed);
2256 if (ret) { 1900 if (ret)
2257 dev_err(&hdev->pdev->dev, 1901 dev_err(&hdev->pdev->dev,
2258 "could not parse speed(=%d), %d\n", speed_tmp, ret); 1902 "could not parse speed(=%d), %d\n", speed_tmp, ret);
2259 return -EIO;
2260 }
2261 1903
2262 return 0; 1904 return ret;
2263} 1905}
2264 1906
2265static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable) 1907static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
@@ -2272,17 +1914,15 @@ static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
2272 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false); 1914 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
2273 1915
2274 req = (struct hclge_config_auto_neg_cmd *)desc.data; 1916 req = (struct hclge_config_auto_neg_cmd *)desc.data;
2275 hnae_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, !!enable); 1917 hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, !!enable);
2276 req->cfg_an_cmd_flag = cpu_to_le32(flag); 1918 req->cfg_an_cmd_flag = cpu_to_le32(flag);
2277 1919
2278 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1920 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2279 if (ret) { 1921 if (ret)
2280 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n", 1922 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
2281 ret); 1923 ret);
2282 return ret;
2283 }
2284 1924
2285 return 0; 1925 return ret;
2286} 1926}
2287 1927
2288static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable) 1928static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
@@ -2305,40 +1945,17 @@ static int hclge_get_autoneg(struct hnae3_handle *handle)
2305 return hdev->hw.mac.autoneg; 1945 return hdev->hw.mac.autoneg;
2306} 1946}
2307 1947
2308static int hclge_set_default_mac_vlan_mask(struct hclge_dev *hdev,
2309 bool mask_vlan,
2310 u8 *mac_mask)
2311{
2312 struct hclge_mac_vlan_mask_entry_cmd *req;
2313 struct hclge_desc desc;
2314 int status;
2315
2316 req = (struct hclge_mac_vlan_mask_entry_cmd *)desc.data;
2317 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_MASK_SET, false);
2318
2319 hnae_set_bit(req->vlan_mask, HCLGE_VLAN_MASK_EN_B,
2320 mask_vlan ? 1 : 0);
2321 ether_addr_copy(req->mac_mask, mac_mask);
2322
2323 status = hclge_cmd_send(&hdev->hw, &desc, 1);
2324 if (status)
2325 dev_err(&hdev->pdev->dev,
2326 "Config mac_vlan_mask failed for cmd_send, ret =%d\n",
2327 status);
2328
2329 return status;
2330}
2331
2332static int hclge_mac_init(struct hclge_dev *hdev) 1948static int hclge_mac_init(struct hclge_dev *hdev)
2333{ 1949{
2334 struct hnae3_handle *handle = &hdev->vport[0].nic; 1950 struct hnae3_handle *handle = &hdev->vport[0].nic;
2335 struct net_device *netdev = handle->kinfo.netdev; 1951 struct net_device *netdev = handle->kinfo.netdev;
2336 struct hclge_mac *mac = &hdev->hw.mac; 1952 struct hclge_mac *mac = &hdev->hw.mac;
2337 u8 mac_mask[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
2338 int mtu; 1953 int mtu;
2339 int ret; 1954 int ret;
2340 1955
2341 ret = hclge_cfg_mac_speed_dup(hdev, hdev->hw.mac.speed, HCLGE_MAC_FULL); 1956 hdev->hw.mac.duplex = HCLGE_MAC_FULL;
1957 ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.speed,
1958 hdev->hw.mac.duplex);
2342 if (ret) { 1959 if (ret) {
2343 dev_err(&hdev->pdev->dev, 1960 dev_err(&hdev->pdev->dev,
2344 "Config mac speed dup fail ret=%d\n", ret); 1961 "Config mac speed dup fail ret=%d\n", ret);
@@ -2347,47 +1964,17 @@ static int hclge_mac_init(struct hclge_dev *hdev)
2347 1964
2348 mac->link = 0; 1965 mac->link = 0;
2349 1966
2350 /* Initialize the MTA table work mode */
2351 hdev->accept_mta_mc = true;
2352 hdev->enable_mta = true;
2353 hdev->mta_mac_sel_type = HCLGE_MAC_ADDR_47_36;
2354
2355 ret = hclge_set_mta_filter_mode(hdev,
2356 hdev->mta_mac_sel_type,
2357 hdev->enable_mta);
2358 if (ret) {
2359 dev_err(&hdev->pdev->dev, "set mta filter mode failed %d\n",
2360 ret);
2361 return ret;
2362 }
2363
2364 ret = hclge_cfg_func_mta_filter(hdev, 0, hdev->accept_mta_mc);
2365 if (ret) {
2366 dev_err(&hdev->pdev->dev,
2367 "set mta filter mode fail ret=%d\n", ret);
2368 return ret;
2369 }
2370
2371 ret = hclge_set_default_mac_vlan_mask(hdev, true, mac_mask);
2372 if (ret) {
2373 dev_err(&hdev->pdev->dev,
2374 "set default mac_vlan_mask fail ret=%d\n", ret);
2375 return ret;
2376 }
2377
2378 if (netdev) 1967 if (netdev)
2379 mtu = netdev->mtu; 1968 mtu = netdev->mtu;
2380 else 1969 else
2381 mtu = ETH_DATA_LEN; 1970 mtu = ETH_DATA_LEN;
2382 1971
2383 ret = hclge_set_mtu(handle, mtu); 1972 ret = hclge_set_mtu(handle, mtu);
2384 if (ret) { 1973 if (ret)
2385 dev_err(&hdev->pdev->dev, 1974 dev_err(&hdev->pdev->dev,
2386 "set mtu failed ret=%d\n", ret); 1975 "set mtu failed ret=%d\n", ret);
2387 return ret;
2388 }
2389 1976
2390 return 0; 1977 return ret;
2391} 1978}
2392 1979
2393static void hclge_mbx_task_schedule(struct hclge_dev *hdev) 1980static void hclge_mbx_task_schedule(struct hclge_dev *hdev)
@@ -2426,7 +2013,7 @@ static int hclge_get_mac_link_status(struct hclge_dev *hdev)
2426 } 2013 }
2427 2014
2428 req = (struct hclge_link_status_cmd *)desc.data; 2015 req = (struct hclge_link_status_cmd *)desc.data;
2429 link_status = req->status & HCLGE_LINK_STATUS; 2016 link_status = req->status & HCLGE_LINK_STATUS_UP_M;
2430 2017
2431 return !!link_status; 2018 return !!link_status;
2432} 2019}
@@ -2436,10 +2023,13 @@ static int hclge_get_mac_phy_link(struct hclge_dev *hdev)
2436 int mac_state; 2023 int mac_state;
2437 int link_stat; 2024 int link_stat;
2438 2025
2026 if (test_bit(HCLGE_STATE_DOWN, &hdev->state))
2027 return 0;
2028
2439 mac_state = hclge_get_mac_link_status(hdev); 2029 mac_state = hclge_get_mac_link_status(hdev);
2440 2030
2441 if (hdev->hw.mac.phydev) { 2031 if (hdev->hw.mac.phydev) {
2442 if (!genphy_read_status(hdev->hw.mac.phydev)) 2032 if (hdev->hw.mac.phydev->state == PHY_RUNNING)
2443 link_stat = mac_state & 2033 link_stat = mac_state &
2444 hdev->hw.mac.phydev->link; 2034 hdev->hw.mac.phydev->link;
2445 else 2035 else
@@ -2491,13 +2081,11 @@ static int hclge_update_speed_duplex(struct hclge_dev *hdev)
2491 return ret; 2081 return ret;
2492 } 2082 }
2493 2083
2494 if ((mac.speed != speed) || (mac.duplex != duplex)) { 2084 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2495 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex); 2085 if (ret) {
2496 if (ret) { 2086 dev_err(&hdev->pdev->dev,
2497 dev_err(&hdev->pdev->dev, 2087 "mac speed/duplex config failed %d\n", ret);
2498 "mac speed/duplex config failed %d\n", ret); 2088 return ret;
2499 return ret;
2500 }
2501 } 2089 }
2502 2090
2503 return 0; 2091 return 0;
@@ -2545,7 +2133,7 @@ static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
2545 u32 cmdq_src_reg; 2133 u32 cmdq_src_reg;
2546 2134
2547 /* fetch the events from their corresponding regs */ 2135 /* fetch the events from their corresponding regs */
2548 rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG); 2136 rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS);
2549 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG); 2137 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG);
2550 2138
2551 /* Assumption: If by any chance reset and mailbox events are reported 2139 /* Assumption: If by any chance reset and mailbox events are reported
@@ -2557,12 +2145,14 @@ static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
2557 2145
2558 /* check for vector0 reset event sources */ 2146 /* check for vector0 reset event sources */
2559 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) { 2147 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) {
2148 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
2560 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending); 2149 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
2561 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); 2150 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2562 return HCLGE_VECTOR0_EVENT_RST; 2151 return HCLGE_VECTOR0_EVENT_RST;
2563 } 2152 }
2564 2153
2565 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) { 2154 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) {
2155 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
2566 set_bit(HNAE3_CORE_RESET, &hdev->reset_pending); 2156 set_bit(HNAE3_CORE_RESET, &hdev->reset_pending);
2567 *clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B); 2157 *clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2568 return HCLGE_VECTOR0_EVENT_RST; 2158 return HCLGE_VECTOR0_EVENT_RST;
@@ -2594,9 +2184,20 @@ static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type,
2594 case HCLGE_VECTOR0_EVENT_MBX: 2184 case HCLGE_VECTOR0_EVENT_MBX:
2595 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr); 2185 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr);
2596 break; 2186 break;
2187 default:
2188 break;
2597 } 2189 }
2598} 2190}
2599 2191
2192static void hclge_clear_all_event_cause(struct hclge_dev *hdev)
2193{
2194 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_RST,
2195 BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) |
2196 BIT(HCLGE_VECTOR0_CORERESET_INT_B) |
2197 BIT(HCLGE_VECTOR0_IMPRESET_INT_B));
2198 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_MBX, 0);
2199}
2200
2600static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable) 2201static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable)
2601{ 2202{
2602 writel(enable ? 1 : 0, vector->addr); 2203 writel(enable ? 1 : 0, vector->addr);
@@ -2627,22 +2228,30 @@ static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
2627 * mbx messages reported by this interrupt. 2228 * mbx messages reported by this interrupt.
2628 */ 2229 */
2629 hclge_mbx_task_schedule(hdev); 2230 hclge_mbx_task_schedule(hdev);
2630 2231 break;
2631 default: 2232 default:
2632 dev_dbg(&hdev->pdev->dev, 2233 dev_warn(&hdev->pdev->dev,
2633 "received unknown or unhandled event of vector0\n"); 2234 "received unknown or unhandled event of vector0\n");
2634 break; 2235 break;
2635 } 2236 }
2636 2237
2637 /* we should clear the source of interrupt */ 2238 /* clear the source of interrupt if it is not cause by reset */
2638 hclge_clear_event_cause(hdev, event_cause, clearval); 2239 if (event_cause == HCLGE_VECTOR0_EVENT_MBX) {
2639 hclge_enable_vector(&hdev->misc_vector, true); 2240 hclge_clear_event_cause(hdev, event_cause, clearval);
2241 hclge_enable_vector(&hdev->misc_vector, true);
2242 }
2640 2243
2641 return IRQ_HANDLED; 2244 return IRQ_HANDLED;
2642} 2245}
2643 2246
2644static void hclge_free_vector(struct hclge_dev *hdev, int vector_id) 2247static void hclge_free_vector(struct hclge_dev *hdev, int vector_id)
2645{ 2248{
2249 if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) {
2250 dev_warn(&hdev->pdev->dev,
2251 "vector(vector_id %d) has been freed.\n", vector_id);
2252 return;
2253 }
2254
2646 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT; 2255 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT;
2647 hdev->num_msi_left += 1; 2256 hdev->num_msi_left += 1;
2648 hdev->num_msi_used -= 1; 2257 hdev->num_msi_used -= 1;
@@ -2734,7 +2343,7 @@ static int hclge_reset_wait(struct hclge_dev *hdev)
2734 } 2343 }
2735 2344
2736 val = hclge_read_dev(&hdev->hw, reg); 2345 val = hclge_read_dev(&hdev->hw, reg);
2737 while (hnae_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) { 2346 while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) {
2738 msleep(HCLGE_RESET_WATI_MS); 2347 msleep(HCLGE_RESET_WATI_MS);
2739 val = hclge_read_dev(&hdev->hw, reg); 2348 val = hclge_read_dev(&hdev->hw, reg);
2740 cnt++; 2349 cnt++;
@@ -2756,8 +2365,7 @@ int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id)
2756 int ret; 2365 int ret;
2757 2366
2758 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false); 2367 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);
2759 hnae_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_MAC_B, 0); 2368 hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1);
2760 hnae_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1);
2761 req->fun_reset_vfid = func_id; 2369 req->fun_reset_vfid = func_id;
2762 2370
2763 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2371 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
@@ -2776,13 +2384,13 @@ static void hclge_do_reset(struct hclge_dev *hdev)
2776 switch (hdev->reset_type) { 2384 switch (hdev->reset_type) {
2777 case HNAE3_GLOBAL_RESET: 2385 case HNAE3_GLOBAL_RESET:
2778 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG); 2386 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2779 hnae_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1); 2387 hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1);
2780 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val); 2388 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2781 dev_info(&pdev->dev, "Global Reset requested\n"); 2389 dev_info(&pdev->dev, "Global Reset requested\n");
2782 break; 2390 break;
2783 case HNAE3_CORE_RESET: 2391 case HNAE3_CORE_RESET:
2784 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG); 2392 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2785 hnae_set_bit(val, HCLGE_CORE_RESET_BIT, 1); 2393 hnae3_set_bit(val, HCLGE_CORE_RESET_BIT, 1);
2786 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val); 2394 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2787 dev_info(&pdev->dev, "Core Reset requested\n"); 2395 dev_info(&pdev->dev, "Core Reset requested\n");
2788 break; 2396 break;
@@ -2824,39 +2432,92 @@ static enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev,
2824 return rst_level; 2432 return rst_level;
2825} 2433}
2826 2434
2435static void hclge_clear_reset_cause(struct hclge_dev *hdev)
2436{
2437 u32 clearval = 0;
2438
2439 switch (hdev->reset_type) {
2440 case HNAE3_IMP_RESET:
2441 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2442 break;
2443 case HNAE3_GLOBAL_RESET:
2444 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2445 break;
2446 case HNAE3_CORE_RESET:
2447 clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2448 break;
2449 default:
2450 break;
2451 }
2452
2453 if (!clearval)
2454 return;
2455
2456 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, clearval);
2457 hclge_enable_vector(&hdev->misc_vector, true);
2458}
2459
2827static void hclge_reset(struct hclge_dev *hdev) 2460static void hclge_reset(struct hclge_dev *hdev)
2828{ 2461{
2829 /* perform reset of the stack & ae device for a client */ 2462 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
2463 struct hnae3_handle *handle;
2830 2464
2465 /* Initialize ae_dev reset status as well, in case enet layer wants to
2466 * know if device is undergoing reset
2467 */
2468 ae_dev->reset_type = hdev->reset_type;
2469 /* perform reset of the stack & ae device for a client */
2470 handle = &hdev->vport[0].nic;
2471 rtnl_lock();
2831 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 2472 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
2473 rtnl_unlock();
2832 2474
2833 if (!hclge_reset_wait(hdev)) { 2475 if (!hclge_reset_wait(hdev)) {
2834 rtnl_lock(); 2476 rtnl_lock();
2835 hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT); 2477 hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
2836 hclge_reset_ae_dev(hdev->ae_dev); 2478 hclge_reset_ae_dev(hdev->ae_dev);
2837 hclge_notify_client(hdev, HNAE3_INIT_CLIENT); 2479 hclge_notify_client(hdev, HNAE3_INIT_CLIENT);
2838 rtnl_unlock(); 2480
2481 hclge_clear_reset_cause(hdev);
2839 } else { 2482 } else {
2483 rtnl_lock();
2840 /* schedule again to check pending resets later */ 2484 /* schedule again to check pending resets later */
2841 set_bit(hdev->reset_type, &hdev->reset_pending); 2485 set_bit(hdev->reset_type, &hdev->reset_pending);
2842 hclge_reset_task_schedule(hdev); 2486 hclge_reset_task_schedule(hdev);
2843 } 2487 }
2844 2488
2845 hclge_notify_client(hdev, HNAE3_UP_CLIENT); 2489 hclge_notify_client(hdev, HNAE3_UP_CLIENT);
2490 handle->last_reset_time = jiffies;
2491 rtnl_unlock();
2492 ae_dev->reset_type = HNAE3_NONE_RESET;
2846} 2493}
2847 2494
2848static void hclge_reset_event(struct hnae3_handle *handle) 2495static void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle)
2849{ 2496{
2850 struct hclge_vport *vport = hclge_get_vport(handle); 2497 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2851 struct hclge_dev *hdev = vport->back; 2498 struct hclge_dev *hdev = ae_dev->priv;
2852 2499
2853 /* check if this is a new reset request and we are not here just because 2500 /* We might end up getting called broadly because of 2 below cases:
2501 * 1. Recoverable error was conveyed through APEI and only way to bring
2502 * normalcy is to reset.
2503 * 2. A new reset request from the stack due to timeout
2504 *
2505 * For the first case,error event might not have ae handle available.
2506 * check if this is a new reset request and we are not here just because
2854 * last reset attempt did not succeed and watchdog hit us again. We will 2507 * last reset attempt did not succeed and watchdog hit us again. We will
2855 * know this if last reset request did not occur very recently (watchdog 2508 * know this if last reset request did not occur very recently (watchdog
2856 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz) 2509 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz)
2857 * In case of new request we reset the "reset level" to PF reset. 2510 * In case of new request we reset the "reset level" to PF reset.
2511 * And if it is a repeat reset request of the most recent one then we
2512 * want to make sure we throttle the reset request. Therefore, we will
2513 * not allow it again before 3*HZ times.
2858 */ 2514 */
2859 if (time_after(jiffies, (handle->last_reset_time + 4 * 5 * HZ))) 2515 if (!handle)
2516 handle = &hdev->vport[0].nic;
2517
2518 if (time_before(jiffies, (handle->last_reset_time + 3 * HZ)))
2519 return;
2520 else if (time_after(jiffies, (handle->last_reset_time + 4 * 5 * HZ)))
2860 handle->reset_level = HNAE3_FUNC_RESET; 2521 handle->reset_level = HNAE3_FUNC_RESET;
2861 2522
2862 dev_info(&hdev->pdev->dev, "received reset event , reset type is %d", 2523 dev_info(&hdev->pdev->dev, "received reset event , reset type is %d",
@@ -2868,8 +2529,6 @@ static void hclge_reset_event(struct hnae3_handle *handle)
2868 2529
2869 if (handle->reset_level < HNAE3_GLOBAL_RESET) 2530 if (handle->reset_level < HNAE3_GLOBAL_RESET)
2870 handle->reset_level++; 2531 handle->reset_level++;
2871
2872 handle->last_reset_time = jiffies;
2873} 2532}
2874 2533
2875static void hclge_reset_subtask(struct hclge_dev *hdev) 2534static void hclge_reset_subtask(struct hclge_dev *hdev)
@@ -2930,38 +2589,16 @@ static void hclge_service_task(struct work_struct *work)
2930 struct hclge_dev *hdev = 2589 struct hclge_dev *hdev =
2931 container_of(work, struct hclge_dev, service_task); 2590 container_of(work, struct hclge_dev, service_task);
2932 2591
2933 /* The total rx/tx packets statstics are wanted to be updated
2934 * per second. Both hclge_update_stats_for_all() and
2935 * hclge_mac_get_traffic_stats() can do it.
2936 */
2937 if (hdev->hw_stats.stats_timer >= HCLGE_STATS_TIMER_INTERVAL) { 2592 if (hdev->hw_stats.stats_timer >= HCLGE_STATS_TIMER_INTERVAL) {
2938 hclge_update_stats_for_all(hdev); 2593 hclge_update_stats_for_all(hdev);
2939 hdev->hw_stats.stats_timer = 0; 2594 hdev->hw_stats.stats_timer = 0;
2940 } else {
2941 hclge_mac_get_traffic_stats(hdev);
2942 } 2595 }
2943 2596
2944 hclge_update_speed_duplex(hdev); 2597 hclge_update_speed_duplex(hdev);
2945 hclge_update_link_status(hdev); 2598 hclge_update_link_status(hdev);
2946 hclge_update_led_status(hdev);
2947 hclge_service_complete(hdev); 2599 hclge_service_complete(hdev);
2948} 2600}
2949 2601
2950static void hclge_disable_sriov(struct hclge_dev *hdev)
2951{
2952 /* If our VFs are assigned we cannot shut down SR-IOV
2953 * without causing issues, so just leave the hardware
2954 * available but disabled
2955 */
2956 if (pci_vfs_assigned(hdev->pdev)) {
2957 dev_warn(&hdev->pdev->dev,
2958 "disabling driver while VFs are assigned\n");
2959 return;
2960 }
2961
2962 pci_disable_sriov(hdev->pdev);
2963}
2964
2965struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle) 2602struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
2966{ 2603{
2967 /* VF handle has no client */ 2604 /* VF handle has no client */
@@ -3132,23 +2769,37 @@ static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid,
3132 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2769 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
3133 u16 mode = 0; 2770 u16 mode = 0;
3134 2771
3135 hnae_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1)); 2772 hnae3_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1));
3136 hnae_set_field(mode, HCLGE_RSS_TC_SIZE_M, 2773 hnae3_set_field(mode, HCLGE_RSS_TC_SIZE_M,
3137 HCLGE_RSS_TC_SIZE_S, tc_size[i]); 2774 HCLGE_RSS_TC_SIZE_S, tc_size[i]);
3138 hnae_set_field(mode, HCLGE_RSS_TC_OFFSET_M, 2775 hnae3_set_field(mode, HCLGE_RSS_TC_OFFSET_M,
3139 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]); 2776 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]);
3140 2777
3141 req->rss_tc_mode[i] = cpu_to_le16(mode); 2778 req->rss_tc_mode[i] = cpu_to_le16(mode);
3142 } 2779 }
3143 2780
3144 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2781 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3145 if (ret) { 2782 if (ret)
3146 dev_err(&hdev->pdev->dev, 2783 dev_err(&hdev->pdev->dev,
3147 "Configure rss tc mode fail, status = %d\n", ret); 2784 "Configure rss tc mode fail, status = %d\n", ret);
3148 return ret;
3149 }
3150 2785
3151 return 0; 2786 return ret;
2787}
2788
2789static void hclge_get_rss_type(struct hclge_vport *vport)
2790{
2791 if (vport->rss_tuple_sets.ipv4_tcp_en ||
2792 vport->rss_tuple_sets.ipv4_udp_en ||
2793 vport->rss_tuple_sets.ipv4_sctp_en ||
2794 vport->rss_tuple_sets.ipv6_tcp_en ||
2795 vport->rss_tuple_sets.ipv6_udp_en ||
2796 vport->rss_tuple_sets.ipv6_sctp_en)
2797 vport->nic.kinfo.rss_type = PKT_HASH_TYPE_L4;
2798 else if (vport->rss_tuple_sets.ipv4_fragment_en ||
2799 vport->rss_tuple_sets.ipv6_fragment_en)
2800 vport->nic.kinfo.rss_type = PKT_HASH_TYPE_L3;
2801 else
2802 vport->nic.kinfo.rss_type = PKT_HASH_TYPE_NONE;
3152} 2803}
3153 2804
3154static int hclge_set_rss_input_tuple(struct hclge_dev *hdev) 2805static int hclge_set_rss_input_tuple(struct hclge_dev *hdev)
@@ -3170,14 +2821,12 @@ static int hclge_set_rss_input_tuple(struct hclge_dev *hdev)
3170 req->ipv6_udp_en = hdev->vport[0].rss_tuple_sets.ipv6_udp_en; 2821 req->ipv6_udp_en = hdev->vport[0].rss_tuple_sets.ipv6_udp_en;
3171 req->ipv6_sctp_en = hdev->vport[0].rss_tuple_sets.ipv6_sctp_en; 2822 req->ipv6_sctp_en = hdev->vport[0].rss_tuple_sets.ipv6_sctp_en;
3172 req->ipv6_fragment_en = hdev->vport[0].rss_tuple_sets.ipv6_fragment_en; 2823 req->ipv6_fragment_en = hdev->vport[0].rss_tuple_sets.ipv6_fragment_en;
2824 hclge_get_rss_type(&hdev->vport[0]);
3173 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2825 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3174 if (ret) { 2826 if (ret)
3175 dev_err(&hdev->pdev->dev, 2827 dev_err(&hdev->pdev->dev,
3176 "Configure rss input fail, status = %d\n", ret); 2828 "Configure rss input fail, status = %d\n", ret);
3177 return ret; 2829 return ret;
3178 }
3179
3180 return 0;
3181} 2830}
3182 2831
3183static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir, 2832static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
@@ -3187,8 +2836,19 @@ static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
3187 int i; 2836 int i;
3188 2837
3189 /* Get hash algorithm */ 2838 /* Get hash algorithm */
3190 if (hfunc) 2839 if (hfunc) {
3191 *hfunc = vport->rss_algo; 2840 switch (vport->rss_algo) {
2841 case HCLGE_RSS_HASH_ALGO_TOEPLITZ:
2842 *hfunc = ETH_RSS_HASH_TOP;
2843 break;
2844 case HCLGE_RSS_HASH_ALGO_SIMPLE:
2845 *hfunc = ETH_RSS_HASH_XOR;
2846 break;
2847 default:
2848 *hfunc = ETH_RSS_HASH_UNKNOWN;
2849 break;
2850 }
2851 }
3192 2852
3193 /* Get the RSS Key required by the user */ 2853 /* Get the RSS Key required by the user */
3194 if (key) 2854 if (key)
@@ -3212,12 +2872,20 @@ static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
3212 2872
3213 /* Set the RSS Hash Key if specififed by the user */ 2873 /* Set the RSS Hash Key if specififed by the user */
3214 if (key) { 2874 if (key) {
3215 2875 switch (hfunc) {
3216 if (hfunc == ETH_RSS_HASH_TOP || 2876 case ETH_RSS_HASH_TOP:
3217 hfunc == ETH_RSS_HASH_NO_CHANGE)
3218 hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ; 2877 hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
3219 else 2878 break;
2879 case ETH_RSS_HASH_XOR:
2880 hash_algo = HCLGE_RSS_HASH_ALGO_SIMPLE;
2881 break;
2882 case ETH_RSS_HASH_NO_CHANGE:
2883 hash_algo = vport->rss_algo;
2884 break;
2885 default:
3220 return -EINVAL; 2886 return -EINVAL;
2887 }
2888
3221 ret = hclge_set_rss_algo_key(hdev, hash_algo, key); 2889 ret = hclge_set_rss_algo_key(hdev, hash_algo, key);
3222 if (ret) 2890 if (ret)
3223 return ret; 2891 return ret;
@@ -3335,6 +3003,7 @@ static int hclge_set_rss_tuple(struct hnae3_handle *handle,
3335 vport->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 3003 vport->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en;
3336 vport->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 3004 vport->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en;
3337 vport->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 3005 vport->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en;
3006 hclge_get_rss_type(vport);
3338 return 0; 3007 return 0;
3339} 3008}
3340 3009
@@ -3513,16 +3182,16 @@ int hclge_bind_ring_with_vector(struct hclge_vport *vport,
3513 i = 0; 3182 i = 0;
3514 for (node = ring_chain; node; node = node->next) { 3183 for (node = ring_chain; node; node = node->next) {
3515 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]); 3184 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]);
3516 hnae_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M, 3185 hnae3_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M,
3517 HCLGE_INT_TYPE_S, 3186 HCLGE_INT_TYPE_S,
3518 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B)); 3187 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B));
3519 hnae_set_field(tqp_type_and_id, HCLGE_TQP_ID_M, 3188 hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M,
3520 HCLGE_TQP_ID_S, node->tqp_index); 3189 HCLGE_TQP_ID_S, node->tqp_index);
3521 hnae_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M, 3190 hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M,
3522 HCLGE_INT_GL_IDX_S, 3191 HCLGE_INT_GL_IDX_S,
3523 hnae_get_field(node->int_gl_idx, 3192 hnae3_get_field(node->int_gl_idx,
3524 HNAE3_RING_GL_IDX_M, 3193 HNAE3_RING_GL_IDX_M,
3525 HNAE3_RING_GL_IDX_S)); 3194 HNAE3_RING_GL_IDX_S));
3526 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id); 3195 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id);
3527 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) { 3196 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
3528 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD; 3197 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
@@ -3615,15 +3284,21 @@ int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
3615 3284
3616 req = (struct hclge_promisc_cfg_cmd *)desc.data; 3285 req = (struct hclge_promisc_cfg_cmd *)desc.data;
3617 req->vf_id = param->vf_id; 3286 req->vf_id = param->vf_id;
3618 req->flag = (param->enable << HCLGE_PROMISC_EN_B); 3287
3288 /* HCLGE_PROMISC_TX_EN_B and HCLGE_PROMISC_RX_EN_B are not supported on
3289 * pdev revision(0x20), new revision support them. The
3290 * value of this two fields will not return error when driver
3291 * send command to fireware in revision(0x20).
3292 */
3293 req->flag = (param->enable << HCLGE_PROMISC_EN_B) |
3294 HCLGE_PROMISC_TX_EN_B | HCLGE_PROMISC_RX_EN_B;
3619 3295
3620 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3296 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3621 if (ret) { 3297 if (ret)
3622 dev_err(&hdev->pdev->dev, 3298 dev_err(&hdev->pdev->dev,
3623 "Set promisc mode fail, status is %d.\n", ret); 3299 "Set promisc mode fail, status is %d.\n", ret);
3624 return ret; 3300
3625 } 3301 return ret;
3626 return 0;
3627} 3302}
3628 3303
3629void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc, 3304void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
@@ -3642,14 +3317,1291 @@ void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
3642 param->vf_id = vport_id; 3317 param->vf_id = vport_id;
3643} 3318}
3644 3319
3645static void hclge_set_promisc_mode(struct hnae3_handle *handle, u32 en) 3320static int hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc,
3321 bool en_mc_pmc)
3646{ 3322{
3647 struct hclge_vport *vport = hclge_get_vport(handle); 3323 struct hclge_vport *vport = hclge_get_vport(handle);
3648 struct hclge_dev *hdev = vport->back; 3324 struct hclge_dev *hdev = vport->back;
3649 struct hclge_promisc_param param; 3325 struct hclge_promisc_param param;
3650 3326
3651 hclge_promisc_param_init(&param, en, en, true, vport->vport_id); 3327 hclge_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, true,
3652 hclge_cmd_set_promisc_mode(hdev, &param); 3328 vport->vport_id);
3329 return hclge_cmd_set_promisc_mode(hdev, &param);
3330}
3331
3332static int hclge_get_fd_mode(struct hclge_dev *hdev, u8 *fd_mode)
3333{
3334 struct hclge_get_fd_mode_cmd *req;
3335 struct hclge_desc desc;
3336 int ret;
3337
3338 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_MODE_CTRL, true);
3339
3340 req = (struct hclge_get_fd_mode_cmd *)desc.data;
3341
3342 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3343 if (ret) {
3344 dev_err(&hdev->pdev->dev, "get fd mode fail, ret=%d\n", ret);
3345 return ret;
3346 }
3347
3348 *fd_mode = req->mode;
3349
3350 return ret;
3351}
3352
3353static int hclge_get_fd_allocation(struct hclge_dev *hdev,
3354 u32 *stage1_entry_num,
3355 u32 *stage2_entry_num,
3356 u16 *stage1_counter_num,
3357 u16 *stage2_counter_num)
3358{
3359 struct hclge_get_fd_allocation_cmd *req;
3360 struct hclge_desc desc;
3361 int ret;
3362
3363 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_GET_ALLOCATION, true);
3364
3365 req = (struct hclge_get_fd_allocation_cmd *)desc.data;
3366
3367 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3368 if (ret) {
3369 dev_err(&hdev->pdev->dev, "query fd allocation fail, ret=%d\n",
3370 ret);
3371 return ret;
3372 }
3373
3374 *stage1_entry_num = le32_to_cpu(req->stage1_entry_num);
3375 *stage2_entry_num = le32_to_cpu(req->stage2_entry_num);
3376 *stage1_counter_num = le16_to_cpu(req->stage1_counter_num);
3377 *stage2_counter_num = le16_to_cpu(req->stage2_counter_num);
3378
3379 return ret;
3380}
3381
3382static int hclge_set_fd_key_config(struct hclge_dev *hdev, int stage_num)
3383{
3384 struct hclge_set_fd_key_config_cmd *req;
3385 struct hclge_fd_key_cfg *stage;
3386 struct hclge_desc desc;
3387 int ret;
3388
3389 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_KEY_CONFIG, false);
3390
3391 req = (struct hclge_set_fd_key_config_cmd *)desc.data;
3392 stage = &hdev->fd_cfg.key_cfg[stage_num];
3393 req->stage = stage_num;
3394 req->key_select = stage->key_sel;
3395 req->inner_sipv6_word_en = stage->inner_sipv6_word_en;
3396 req->inner_dipv6_word_en = stage->inner_dipv6_word_en;
3397 req->outer_sipv6_word_en = stage->outer_sipv6_word_en;
3398 req->outer_dipv6_word_en = stage->outer_dipv6_word_en;
3399 req->tuple_mask = cpu_to_le32(~stage->tuple_active);
3400 req->meta_data_mask = cpu_to_le32(~stage->meta_data_active);
3401
3402 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3403 if (ret)
3404 dev_err(&hdev->pdev->dev, "set fd key fail, ret=%d\n", ret);
3405
3406 return ret;
3407}
3408
3409static int hclge_init_fd_config(struct hclge_dev *hdev)
3410{
3411#define LOW_2_WORDS 0x03
3412 struct hclge_fd_key_cfg *key_cfg;
3413 int ret;
3414
3415 if (!hnae3_dev_fd_supported(hdev))
3416 return 0;
3417
3418 ret = hclge_get_fd_mode(hdev, &hdev->fd_cfg.fd_mode);
3419 if (ret)
3420 return ret;
3421
3422 switch (hdev->fd_cfg.fd_mode) {
3423 case HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1:
3424 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH;
3425 break;
3426 case HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1:
3427 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH / 2;
3428 break;
3429 default:
3430 dev_err(&hdev->pdev->dev,
3431 "Unsupported flow director mode %d\n",
3432 hdev->fd_cfg.fd_mode);
3433 return -EOPNOTSUPP;
3434 }
3435
3436 hdev->fd_cfg.fd_en = true;
3437 hdev->fd_cfg.proto_support =
3438 TCP_V4_FLOW | UDP_V4_FLOW | SCTP_V4_FLOW | TCP_V6_FLOW |
3439 UDP_V6_FLOW | SCTP_V6_FLOW | IPV4_USER_FLOW | IPV6_USER_FLOW;
3440 key_cfg = &hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1];
3441 key_cfg->key_sel = HCLGE_FD_KEY_BASE_ON_TUPLE,
3442 key_cfg->inner_sipv6_word_en = LOW_2_WORDS;
3443 key_cfg->inner_dipv6_word_en = LOW_2_WORDS;
3444 key_cfg->outer_sipv6_word_en = 0;
3445 key_cfg->outer_dipv6_word_en = 0;
3446
3447 key_cfg->tuple_active = BIT(INNER_VLAN_TAG_FST) | BIT(INNER_ETH_TYPE) |
3448 BIT(INNER_IP_PROTO) | BIT(INNER_IP_TOS) |
3449 BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) |
3450 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT);
3451
3452 /* If use max 400bit key, we can support tuples for ether type */
3453 if (hdev->fd_cfg.max_key_length == MAX_KEY_LENGTH) {
3454 hdev->fd_cfg.proto_support |= ETHER_FLOW;
3455 key_cfg->tuple_active |=
3456 BIT(INNER_DST_MAC) | BIT(INNER_SRC_MAC);
3457 }
3458
3459 /* roce_type is used to filter roce frames
3460 * dst_vport is used to specify the rule
3461 */
3462 key_cfg->meta_data_active = BIT(ROCE_TYPE) | BIT(DST_VPORT);
3463
3464 ret = hclge_get_fd_allocation(hdev,
3465 &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1],
3466 &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_2],
3467 &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1],
3468 &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_2]);
3469 if (ret)
3470 return ret;
3471
3472 return hclge_set_fd_key_config(hdev, HCLGE_FD_STAGE_1);
3473}
3474
3475static int hclge_fd_tcam_config(struct hclge_dev *hdev, u8 stage, bool sel_x,
3476 int loc, u8 *key, bool is_add)
3477{
3478 struct hclge_fd_tcam_config_1_cmd *req1;
3479 struct hclge_fd_tcam_config_2_cmd *req2;
3480 struct hclge_fd_tcam_config_3_cmd *req3;
3481 struct hclge_desc desc[3];
3482 int ret;
3483
3484 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_FD_TCAM_OP, false);
3485 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3486 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_FD_TCAM_OP, false);
3487 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3488 hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_FD_TCAM_OP, false);
3489
3490 req1 = (struct hclge_fd_tcam_config_1_cmd *)desc[0].data;
3491 req2 = (struct hclge_fd_tcam_config_2_cmd *)desc[1].data;
3492 req3 = (struct hclge_fd_tcam_config_3_cmd *)desc[2].data;
3493
3494 req1->stage = stage;
3495 req1->xy_sel = sel_x ? 1 : 0;
3496 hnae3_set_bit(req1->port_info, HCLGE_FD_EPORT_SW_EN_B, 0);
3497 req1->index = cpu_to_le32(loc);
3498 req1->entry_vld = sel_x ? is_add : 0;
3499
3500 if (key) {
3501 memcpy(req1->tcam_data, &key[0], sizeof(req1->tcam_data));
3502 memcpy(req2->tcam_data, &key[sizeof(req1->tcam_data)],
3503 sizeof(req2->tcam_data));
3504 memcpy(req3->tcam_data, &key[sizeof(req1->tcam_data) +
3505 sizeof(req2->tcam_data)], sizeof(req3->tcam_data));
3506 }
3507
3508 ret = hclge_cmd_send(&hdev->hw, desc, 3);
3509 if (ret)
3510 dev_err(&hdev->pdev->dev,
3511 "config tcam key fail, ret=%d\n",
3512 ret);
3513
3514 return ret;
3515}
3516
3517static int hclge_fd_ad_config(struct hclge_dev *hdev, u8 stage, int loc,
3518 struct hclge_fd_ad_data *action)
3519{
3520 struct hclge_fd_ad_config_cmd *req;
3521 struct hclge_desc desc;
3522 u64 ad_data = 0;
3523 int ret;
3524
3525 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_AD_OP, false);
3526
3527 req = (struct hclge_fd_ad_config_cmd *)desc.data;
3528 req->index = cpu_to_le32(loc);
3529 req->stage = stage;
3530
3531 hnae3_set_bit(ad_data, HCLGE_FD_AD_WR_RULE_ID_B,
3532 action->write_rule_id_to_bd);
3533 hnae3_set_field(ad_data, HCLGE_FD_AD_RULE_ID_M, HCLGE_FD_AD_RULE_ID_S,
3534 action->rule_id);
3535 ad_data <<= 32;
3536 hnae3_set_bit(ad_data, HCLGE_FD_AD_DROP_B, action->drop_packet);
3537 hnae3_set_bit(ad_data, HCLGE_FD_AD_DIRECT_QID_B,
3538 action->forward_to_direct_queue);
3539 hnae3_set_field(ad_data, HCLGE_FD_AD_QID_M, HCLGE_FD_AD_QID_S,
3540 action->queue_id);
3541 hnae3_set_bit(ad_data, HCLGE_FD_AD_USE_COUNTER_B, action->use_counter);
3542 hnae3_set_field(ad_data, HCLGE_FD_AD_COUNTER_NUM_M,
3543 HCLGE_FD_AD_COUNTER_NUM_S, action->counter_id);
3544 hnae3_set_bit(ad_data, HCLGE_FD_AD_NXT_STEP_B, action->use_next_stage);
3545 hnae3_set_field(ad_data, HCLGE_FD_AD_NXT_KEY_M, HCLGE_FD_AD_NXT_KEY_S,
3546 action->counter_id);
3547
3548 req->ad_data = cpu_to_le64(ad_data);
3549 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3550 if (ret)
3551 dev_err(&hdev->pdev->dev, "fd ad config fail, ret=%d\n", ret);
3552
3553 return ret;
3554}
3555
3556static bool hclge_fd_convert_tuple(u32 tuple_bit, u8 *key_x, u8 *key_y,
3557 struct hclge_fd_rule *rule)
3558{
3559 u16 tmp_x_s, tmp_y_s;
3560 u32 tmp_x_l, tmp_y_l;
3561 int i;
3562
3563 if (rule->unused_tuple & tuple_bit)
3564 return true;
3565
3566 switch (tuple_bit) {
3567 case 0:
3568 return false;
3569 case BIT(INNER_DST_MAC):
3570 for (i = 0; i < 6; i++) {
3571 calc_x(key_x[5 - i], rule->tuples.dst_mac[i],
3572 rule->tuples_mask.dst_mac[i]);
3573 calc_y(key_y[5 - i], rule->tuples.dst_mac[i],
3574 rule->tuples_mask.dst_mac[i]);
3575 }
3576
3577 return true;
3578 case BIT(INNER_SRC_MAC):
3579 for (i = 0; i < 6; i++) {
3580 calc_x(key_x[5 - i], rule->tuples.src_mac[i],
3581 rule->tuples.src_mac[i]);
3582 calc_y(key_y[5 - i], rule->tuples.src_mac[i],
3583 rule->tuples.src_mac[i]);
3584 }
3585
3586 return true;
3587 case BIT(INNER_VLAN_TAG_FST):
3588 calc_x(tmp_x_s, rule->tuples.vlan_tag1,
3589 rule->tuples_mask.vlan_tag1);
3590 calc_y(tmp_y_s, rule->tuples.vlan_tag1,
3591 rule->tuples_mask.vlan_tag1);
3592 *(__le16 *)key_x = cpu_to_le16(tmp_x_s);
3593 *(__le16 *)key_y = cpu_to_le16(tmp_y_s);
3594
3595 return true;
3596 case BIT(INNER_ETH_TYPE):
3597 calc_x(tmp_x_s, rule->tuples.ether_proto,
3598 rule->tuples_mask.ether_proto);
3599 calc_y(tmp_y_s, rule->tuples.ether_proto,
3600 rule->tuples_mask.ether_proto);
3601 *(__le16 *)key_x = cpu_to_le16(tmp_x_s);
3602 *(__le16 *)key_y = cpu_to_le16(tmp_y_s);
3603
3604 return true;
3605 case BIT(INNER_IP_TOS):
3606 calc_x(*key_x, rule->tuples.ip_tos, rule->tuples_mask.ip_tos);
3607 calc_y(*key_y, rule->tuples.ip_tos, rule->tuples_mask.ip_tos);
3608
3609 return true;
3610 case BIT(INNER_IP_PROTO):
3611 calc_x(*key_x, rule->tuples.ip_proto,
3612 rule->tuples_mask.ip_proto);
3613 calc_y(*key_y, rule->tuples.ip_proto,
3614 rule->tuples_mask.ip_proto);
3615
3616 return true;
3617 case BIT(INNER_SRC_IP):
3618 calc_x(tmp_x_l, rule->tuples.src_ip[3],
3619 rule->tuples_mask.src_ip[3]);
3620 calc_y(tmp_y_l, rule->tuples.src_ip[3],
3621 rule->tuples_mask.src_ip[3]);
3622 *(__le32 *)key_x = cpu_to_le32(tmp_x_l);
3623 *(__le32 *)key_y = cpu_to_le32(tmp_y_l);
3624
3625 return true;
3626 case BIT(INNER_DST_IP):
3627 calc_x(tmp_x_l, rule->tuples.dst_ip[3],
3628 rule->tuples_mask.dst_ip[3]);
3629 calc_y(tmp_y_l, rule->tuples.dst_ip[3],
3630 rule->tuples_mask.dst_ip[3]);
3631 *(__le32 *)key_x = cpu_to_le32(tmp_x_l);
3632 *(__le32 *)key_y = cpu_to_le32(tmp_y_l);
3633
3634 return true;
3635 case BIT(INNER_SRC_PORT):
3636 calc_x(tmp_x_s, rule->tuples.src_port,
3637 rule->tuples_mask.src_port);
3638 calc_y(tmp_y_s, rule->tuples.src_port,
3639 rule->tuples_mask.src_port);
3640 *(__le16 *)key_x = cpu_to_le16(tmp_x_s);
3641 *(__le16 *)key_y = cpu_to_le16(tmp_y_s);
3642
3643 return true;
3644 case BIT(INNER_DST_PORT):
3645 calc_x(tmp_x_s, rule->tuples.dst_port,
3646 rule->tuples_mask.dst_port);
3647 calc_y(tmp_y_s, rule->tuples.dst_port,
3648 rule->tuples_mask.dst_port);
3649 *(__le16 *)key_x = cpu_to_le16(tmp_x_s);
3650 *(__le16 *)key_y = cpu_to_le16(tmp_y_s);
3651
3652 return true;
3653 default:
3654 return false;
3655 }
3656}
3657
3658static u32 hclge_get_port_number(enum HLCGE_PORT_TYPE port_type, u8 pf_id,
3659 u8 vf_id, u8 network_port_id)
3660{
3661 u32 port_number = 0;
3662
3663 if (port_type == HOST_PORT) {
3664 hnae3_set_field(port_number, HCLGE_PF_ID_M, HCLGE_PF_ID_S,
3665 pf_id);
3666 hnae3_set_field(port_number, HCLGE_VF_ID_M, HCLGE_VF_ID_S,
3667 vf_id);
3668 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, HOST_PORT);
3669 } else {
3670 hnae3_set_field(port_number, HCLGE_NETWORK_PORT_ID_M,
3671 HCLGE_NETWORK_PORT_ID_S, network_port_id);
3672 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, NETWORK_PORT);
3673 }
3674
3675 return port_number;
3676}
3677
3678static void hclge_fd_convert_meta_data(struct hclge_fd_key_cfg *key_cfg,
3679 __le32 *key_x, __le32 *key_y,
3680 struct hclge_fd_rule *rule)
3681{
3682 u32 tuple_bit, meta_data = 0, tmp_x, tmp_y, port_number;
3683 u8 cur_pos = 0, tuple_size, shift_bits;
3684 int i;
3685
3686 for (i = 0; i < MAX_META_DATA; i++) {
3687 tuple_size = meta_data_key_info[i].key_length;
3688 tuple_bit = key_cfg->meta_data_active & BIT(i);
3689
3690 switch (tuple_bit) {
3691 case BIT(ROCE_TYPE):
3692 hnae3_set_bit(meta_data, cur_pos, NIC_PACKET);
3693 cur_pos += tuple_size;
3694 break;
3695 case BIT(DST_VPORT):
3696 port_number = hclge_get_port_number(HOST_PORT, 0,
3697 rule->vf_id, 0);
3698 hnae3_set_field(meta_data,
3699 GENMASK(cur_pos + tuple_size, cur_pos),
3700 cur_pos, port_number);
3701 cur_pos += tuple_size;
3702 break;
3703 default:
3704 break;
3705 }
3706 }
3707
3708 calc_x(tmp_x, meta_data, 0xFFFFFFFF);
3709 calc_y(tmp_y, meta_data, 0xFFFFFFFF);
3710 shift_bits = sizeof(meta_data) * 8 - cur_pos;
3711
3712 *key_x = cpu_to_le32(tmp_x << shift_bits);
3713 *key_y = cpu_to_le32(tmp_y << shift_bits);
3714}
3715
3716/* A complete key is combined with meta data key and tuple key.
3717 * Meta data key is stored at the MSB region, and tuple key is stored at
3718 * the LSB region, unused bits will be filled 0.
3719 */
3720static int hclge_config_key(struct hclge_dev *hdev, u8 stage,
3721 struct hclge_fd_rule *rule)
3722{
3723 struct hclge_fd_key_cfg *key_cfg = &hdev->fd_cfg.key_cfg[stage];
3724 u8 key_x[MAX_KEY_BYTES], key_y[MAX_KEY_BYTES];
3725 u8 *cur_key_x, *cur_key_y;
3726 int i, ret, tuple_size;
3727 u8 meta_data_region;
3728
3729 memset(key_x, 0, sizeof(key_x));
3730 memset(key_y, 0, sizeof(key_y));
3731 cur_key_x = key_x;
3732 cur_key_y = key_y;
3733
3734 for (i = 0 ; i < MAX_TUPLE; i++) {
3735 bool tuple_valid;
3736 u32 check_tuple;
3737
3738 tuple_size = tuple_key_info[i].key_length / 8;
3739 check_tuple = key_cfg->tuple_active & BIT(i);
3740
3741 tuple_valid = hclge_fd_convert_tuple(check_tuple, cur_key_x,
3742 cur_key_y, rule);
3743 if (tuple_valid) {
3744 cur_key_x += tuple_size;
3745 cur_key_y += tuple_size;
3746 }
3747 }
3748
3749 meta_data_region = hdev->fd_cfg.max_key_length / 8 -
3750 MAX_META_DATA_LENGTH / 8;
3751
3752 hclge_fd_convert_meta_data(key_cfg,
3753 (__le32 *)(key_x + meta_data_region),
3754 (__le32 *)(key_y + meta_data_region),
3755 rule);
3756
3757 ret = hclge_fd_tcam_config(hdev, stage, false, rule->location, key_y,
3758 true);
3759 if (ret) {
3760 dev_err(&hdev->pdev->dev,
3761 "fd key_y config fail, loc=%d, ret=%d\n",
3762 rule->queue_id, ret);
3763 return ret;
3764 }
3765
3766 ret = hclge_fd_tcam_config(hdev, stage, true, rule->location, key_x,
3767 true);
3768 if (ret)
3769 dev_err(&hdev->pdev->dev,
3770 "fd key_x config fail, loc=%d, ret=%d\n",
3771 rule->queue_id, ret);
3772 return ret;
3773}
3774
3775static int hclge_config_action(struct hclge_dev *hdev, u8 stage,
3776 struct hclge_fd_rule *rule)
3777{
3778 struct hclge_fd_ad_data ad_data;
3779
3780 ad_data.ad_id = rule->location;
3781
3782 if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) {
3783 ad_data.drop_packet = true;
3784 ad_data.forward_to_direct_queue = false;
3785 ad_data.queue_id = 0;
3786 } else {
3787 ad_data.drop_packet = false;
3788 ad_data.forward_to_direct_queue = true;
3789 ad_data.queue_id = rule->queue_id;
3790 }
3791
3792 ad_data.use_counter = false;
3793 ad_data.counter_id = 0;
3794
3795 ad_data.use_next_stage = false;
3796 ad_data.next_input_key = 0;
3797
3798 ad_data.write_rule_id_to_bd = true;
3799 ad_data.rule_id = rule->location;
3800
3801 return hclge_fd_ad_config(hdev, stage, ad_data.ad_id, &ad_data);
3802}
3803
3804static int hclge_fd_check_spec(struct hclge_dev *hdev,
3805 struct ethtool_rx_flow_spec *fs, u32 *unused)
3806{
3807 struct ethtool_tcpip4_spec *tcp_ip4_spec;
3808 struct ethtool_usrip4_spec *usr_ip4_spec;
3809 struct ethtool_tcpip6_spec *tcp_ip6_spec;
3810 struct ethtool_usrip6_spec *usr_ip6_spec;
3811 struct ethhdr *ether_spec;
3812
3813 if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1])
3814 return -EINVAL;
3815
3816 if (!(fs->flow_type & hdev->fd_cfg.proto_support))
3817 return -EOPNOTSUPP;
3818
3819 if ((fs->flow_type & FLOW_EXT) &&
3820 (fs->h_ext.data[0] != 0 || fs->h_ext.data[1] != 0)) {
3821 dev_err(&hdev->pdev->dev, "user-def bytes are not supported\n");
3822 return -EOPNOTSUPP;
3823 }
3824
3825 switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
3826 case SCTP_V4_FLOW:
3827 case TCP_V4_FLOW:
3828 case UDP_V4_FLOW:
3829 tcp_ip4_spec = &fs->h_u.tcp_ip4_spec;
3830 *unused |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC);
3831
3832 if (!tcp_ip4_spec->ip4src)
3833 *unused |= BIT(INNER_SRC_IP);
3834
3835 if (!tcp_ip4_spec->ip4dst)
3836 *unused |= BIT(INNER_DST_IP);
3837
3838 if (!tcp_ip4_spec->psrc)
3839 *unused |= BIT(INNER_SRC_PORT);
3840
3841 if (!tcp_ip4_spec->pdst)
3842 *unused |= BIT(INNER_DST_PORT);
3843
3844 if (!tcp_ip4_spec->tos)
3845 *unused |= BIT(INNER_IP_TOS);
3846
3847 break;
3848 case IP_USER_FLOW:
3849 usr_ip4_spec = &fs->h_u.usr_ip4_spec;
3850 *unused |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) |
3851 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT);
3852
3853 if (!usr_ip4_spec->ip4src)
3854 *unused |= BIT(INNER_SRC_IP);
3855
3856 if (!usr_ip4_spec->ip4dst)
3857 *unused |= BIT(INNER_DST_IP);
3858
3859 if (!usr_ip4_spec->tos)
3860 *unused |= BIT(INNER_IP_TOS);
3861
3862 if (!usr_ip4_spec->proto)
3863 *unused |= BIT(INNER_IP_PROTO);
3864
3865 if (usr_ip4_spec->l4_4_bytes)
3866 return -EOPNOTSUPP;
3867
3868 if (usr_ip4_spec->ip_ver != ETH_RX_NFC_IP4)
3869 return -EOPNOTSUPP;
3870
3871 break;
3872 case SCTP_V6_FLOW:
3873 case TCP_V6_FLOW:
3874 case UDP_V6_FLOW:
3875 tcp_ip6_spec = &fs->h_u.tcp_ip6_spec;
3876 *unused |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) |
3877 BIT(INNER_IP_TOS);
3878
3879 if (!tcp_ip6_spec->ip6src[0] && !tcp_ip6_spec->ip6src[1] &&
3880 !tcp_ip6_spec->ip6src[2] && !tcp_ip6_spec->ip6src[3])
3881 *unused |= BIT(INNER_SRC_IP);
3882
3883 if (!tcp_ip6_spec->ip6dst[0] && !tcp_ip6_spec->ip6dst[1] &&
3884 !tcp_ip6_spec->ip6dst[2] && !tcp_ip6_spec->ip6dst[3])
3885 *unused |= BIT(INNER_DST_IP);
3886
3887 if (!tcp_ip6_spec->psrc)
3888 *unused |= BIT(INNER_SRC_PORT);
3889
3890 if (!tcp_ip6_spec->pdst)
3891 *unused |= BIT(INNER_DST_PORT);
3892
3893 if (tcp_ip6_spec->tclass)
3894 return -EOPNOTSUPP;
3895
3896 break;
3897 case IPV6_USER_FLOW:
3898 usr_ip6_spec = &fs->h_u.usr_ip6_spec;
3899 *unused |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) |
3900 BIT(INNER_IP_TOS) | BIT(INNER_SRC_PORT) |
3901 BIT(INNER_DST_PORT);
3902
3903 if (!usr_ip6_spec->ip6src[0] && !usr_ip6_spec->ip6src[1] &&
3904 !usr_ip6_spec->ip6src[2] && !usr_ip6_spec->ip6src[3])
3905 *unused |= BIT(INNER_SRC_IP);
3906
3907 if (!usr_ip6_spec->ip6dst[0] && !usr_ip6_spec->ip6dst[1] &&
3908 !usr_ip6_spec->ip6dst[2] && !usr_ip6_spec->ip6dst[3])
3909 *unused |= BIT(INNER_DST_IP);
3910
3911 if (!usr_ip6_spec->l4_proto)
3912 *unused |= BIT(INNER_IP_PROTO);
3913
3914 if (usr_ip6_spec->tclass)
3915 return -EOPNOTSUPP;
3916
3917 if (usr_ip6_spec->l4_4_bytes)
3918 return -EOPNOTSUPP;
3919
3920 break;
3921 case ETHER_FLOW:
3922 ether_spec = &fs->h_u.ether_spec;
3923 *unused |= BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) |
3924 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT) |
3925 BIT(INNER_IP_TOS) | BIT(INNER_IP_PROTO);
3926
3927 if (is_zero_ether_addr(ether_spec->h_source))
3928 *unused |= BIT(INNER_SRC_MAC);
3929
3930 if (is_zero_ether_addr(ether_spec->h_dest))
3931 *unused |= BIT(INNER_DST_MAC);
3932
3933 if (!ether_spec->h_proto)
3934 *unused |= BIT(INNER_ETH_TYPE);
3935
3936 break;
3937 default:
3938 return -EOPNOTSUPP;
3939 }
3940
3941 if ((fs->flow_type & FLOW_EXT)) {
3942 if (fs->h_ext.vlan_etype)
3943 return -EOPNOTSUPP;
3944 if (!fs->h_ext.vlan_tci)
3945 *unused |= BIT(INNER_VLAN_TAG_FST);
3946
3947 if (fs->m_ext.vlan_tci) {
3948 if (be16_to_cpu(fs->h_ext.vlan_tci) >= VLAN_N_VID)
3949 return -EINVAL;
3950 }
3951 } else {
3952 *unused |= BIT(INNER_VLAN_TAG_FST);
3953 }
3954
3955 if (fs->flow_type & FLOW_MAC_EXT) {
3956 if (!(hdev->fd_cfg.proto_support & ETHER_FLOW))
3957 return -EOPNOTSUPP;
3958
3959 if (is_zero_ether_addr(fs->h_ext.h_dest))
3960 *unused |= BIT(INNER_DST_MAC);
3961 else
3962 *unused &= ~(BIT(INNER_DST_MAC));
3963 }
3964
3965 return 0;
3966}
3967
3968static bool hclge_fd_rule_exist(struct hclge_dev *hdev, u16 location)
3969{
3970 struct hclge_fd_rule *rule = NULL;
3971 struct hlist_node *node2;
3972
3973 hlist_for_each_entry_safe(rule, node2, &hdev->fd_rule_list, rule_node) {
3974 if (rule->location >= location)
3975 break;
3976 }
3977
3978 return rule && rule->location == location;
3979}
3980
3981static int hclge_fd_update_rule_list(struct hclge_dev *hdev,
3982 struct hclge_fd_rule *new_rule,
3983 u16 location,
3984 bool is_add)
3985{
3986 struct hclge_fd_rule *rule = NULL, *parent = NULL;
3987 struct hlist_node *node2;
3988
3989 if (is_add && !new_rule)
3990 return -EINVAL;
3991
3992 hlist_for_each_entry_safe(rule, node2,
3993 &hdev->fd_rule_list, rule_node) {
3994 if (rule->location >= location)
3995 break;
3996 parent = rule;
3997 }
3998
3999 if (rule && rule->location == location) {
4000 hlist_del(&rule->rule_node);
4001 kfree(rule);
4002 hdev->hclge_fd_rule_num--;
4003
4004 if (!is_add)
4005 return 0;
4006
4007 } else if (!is_add) {
4008 dev_err(&hdev->pdev->dev,
4009 "delete fail, rule %d is inexistent\n",
4010 location);
4011 return -EINVAL;
4012 }
4013
4014 INIT_HLIST_NODE(&new_rule->rule_node);
4015
4016 if (parent)
4017 hlist_add_behind(&new_rule->rule_node, &parent->rule_node);
4018 else
4019 hlist_add_head(&new_rule->rule_node, &hdev->fd_rule_list);
4020
4021 hdev->hclge_fd_rule_num++;
4022
4023 return 0;
4024}
4025
4026static int hclge_fd_get_tuple(struct hclge_dev *hdev,
4027 struct ethtool_rx_flow_spec *fs,
4028 struct hclge_fd_rule *rule)
4029{
4030 u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT);
4031
4032 switch (flow_type) {
4033 case SCTP_V4_FLOW:
4034 case TCP_V4_FLOW:
4035 case UDP_V4_FLOW:
4036 rule->tuples.src_ip[3] =
4037 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4src);
4038 rule->tuples_mask.src_ip[3] =
4039 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4src);
4040
4041 rule->tuples.dst_ip[3] =
4042 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4dst);
4043 rule->tuples_mask.dst_ip[3] =
4044 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4dst);
4045
4046 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc);
4047 rule->tuples_mask.src_port =
4048 be16_to_cpu(fs->m_u.tcp_ip4_spec.psrc);
4049
4050 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst);
4051 rule->tuples_mask.dst_port =
4052 be16_to_cpu(fs->m_u.tcp_ip4_spec.pdst);
4053
4054 rule->tuples.ip_tos = fs->h_u.tcp_ip4_spec.tos;
4055 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip4_spec.tos;
4056
4057 rule->tuples.ether_proto = ETH_P_IP;
4058 rule->tuples_mask.ether_proto = 0xFFFF;
4059
4060 break;
4061 case IP_USER_FLOW:
4062 rule->tuples.src_ip[3] =
4063 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4src);
4064 rule->tuples_mask.src_ip[3] =
4065 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4src);
4066
4067 rule->tuples.dst_ip[3] =
4068 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4dst);
4069 rule->tuples_mask.dst_ip[3] =
4070 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4dst);
4071
4072 rule->tuples.ip_tos = fs->h_u.usr_ip4_spec.tos;
4073 rule->tuples_mask.ip_tos = fs->m_u.usr_ip4_spec.tos;
4074
4075 rule->tuples.ip_proto = fs->h_u.usr_ip4_spec.proto;
4076 rule->tuples_mask.ip_proto = fs->m_u.usr_ip4_spec.proto;
4077
4078 rule->tuples.ether_proto = ETH_P_IP;
4079 rule->tuples_mask.ether_proto = 0xFFFF;
4080
4081 break;
4082 case SCTP_V6_FLOW:
4083 case TCP_V6_FLOW:
4084 case UDP_V6_FLOW:
4085 be32_to_cpu_array(rule->tuples.src_ip,
4086 fs->h_u.tcp_ip6_spec.ip6src, 4);
4087 be32_to_cpu_array(rule->tuples_mask.src_ip,
4088 fs->m_u.tcp_ip6_spec.ip6src, 4);
4089
4090 be32_to_cpu_array(rule->tuples.dst_ip,
4091 fs->h_u.tcp_ip6_spec.ip6dst, 4);
4092 be32_to_cpu_array(rule->tuples_mask.dst_ip,
4093 fs->m_u.tcp_ip6_spec.ip6dst, 4);
4094
4095 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.psrc);
4096 rule->tuples_mask.src_port =
4097 be16_to_cpu(fs->m_u.tcp_ip6_spec.psrc);
4098
4099 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.pdst);
4100 rule->tuples_mask.dst_port =
4101 be16_to_cpu(fs->m_u.tcp_ip6_spec.pdst);
4102
4103 rule->tuples.ether_proto = ETH_P_IPV6;
4104 rule->tuples_mask.ether_proto = 0xFFFF;
4105
4106 break;
4107 case IPV6_USER_FLOW:
4108 be32_to_cpu_array(rule->tuples.src_ip,
4109 fs->h_u.usr_ip6_spec.ip6src, 4);
4110 be32_to_cpu_array(rule->tuples_mask.src_ip,
4111 fs->m_u.usr_ip6_spec.ip6src, 4);
4112
4113 be32_to_cpu_array(rule->tuples.dst_ip,
4114 fs->h_u.usr_ip6_spec.ip6dst, 4);
4115 be32_to_cpu_array(rule->tuples_mask.dst_ip,
4116 fs->m_u.usr_ip6_spec.ip6dst, 4);
4117
4118 rule->tuples.ip_proto = fs->h_u.usr_ip6_spec.l4_proto;
4119 rule->tuples_mask.ip_proto = fs->m_u.usr_ip6_spec.l4_proto;
4120
4121 rule->tuples.ether_proto = ETH_P_IPV6;
4122 rule->tuples_mask.ether_proto = 0xFFFF;
4123
4124 break;
4125 case ETHER_FLOW:
4126 ether_addr_copy(rule->tuples.src_mac,
4127 fs->h_u.ether_spec.h_source);
4128 ether_addr_copy(rule->tuples_mask.src_mac,
4129 fs->m_u.ether_spec.h_source);
4130
4131 ether_addr_copy(rule->tuples.dst_mac,
4132 fs->h_u.ether_spec.h_dest);
4133 ether_addr_copy(rule->tuples_mask.dst_mac,
4134 fs->m_u.ether_spec.h_dest);
4135
4136 rule->tuples.ether_proto =
4137 be16_to_cpu(fs->h_u.ether_spec.h_proto);
4138 rule->tuples_mask.ether_proto =
4139 be16_to_cpu(fs->m_u.ether_spec.h_proto);
4140
4141 break;
4142 default:
4143 return -EOPNOTSUPP;
4144 }
4145
4146 switch (flow_type) {
4147 case SCTP_V4_FLOW:
4148 case SCTP_V6_FLOW:
4149 rule->tuples.ip_proto = IPPROTO_SCTP;
4150 rule->tuples_mask.ip_proto = 0xFF;
4151 break;
4152 case TCP_V4_FLOW:
4153 case TCP_V6_FLOW:
4154 rule->tuples.ip_proto = IPPROTO_TCP;
4155 rule->tuples_mask.ip_proto = 0xFF;
4156 break;
4157 case UDP_V4_FLOW:
4158 case UDP_V6_FLOW:
4159 rule->tuples.ip_proto = IPPROTO_UDP;
4160 rule->tuples_mask.ip_proto = 0xFF;
4161 break;
4162 default:
4163 break;
4164 }
4165
4166 if ((fs->flow_type & FLOW_EXT)) {
4167 rule->tuples.vlan_tag1 = be16_to_cpu(fs->h_ext.vlan_tci);
4168 rule->tuples_mask.vlan_tag1 = be16_to_cpu(fs->m_ext.vlan_tci);
4169 }
4170
4171 if (fs->flow_type & FLOW_MAC_EXT) {
4172 ether_addr_copy(rule->tuples.dst_mac, fs->h_ext.h_dest);
4173 ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_ext.h_dest);
4174 }
4175
4176 return 0;
4177}
4178
4179static int hclge_add_fd_entry(struct hnae3_handle *handle,
4180 struct ethtool_rxnfc *cmd)
4181{
4182 struct hclge_vport *vport = hclge_get_vport(handle);
4183 struct hclge_dev *hdev = vport->back;
4184 u16 dst_vport_id = 0, q_index = 0;
4185 struct ethtool_rx_flow_spec *fs;
4186 struct hclge_fd_rule *rule;
4187 u32 unused = 0;
4188 u8 action;
4189 int ret;
4190
4191 if (!hnae3_dev_fd_supported(hdev))
4192 return -EOPNOTSUPP;
4193
4194 if (!hdev->fd_cfg.fd_en) {
4195 dev_warn(&hdev->pdev->dev,
4196 "Please enable flow director first\n");
4197 return -EOPNOTSUPP;
4198 }
4199
4200 fs = (struct ethtool_rx_flow_spec *)&cmd->fs;
4201
4202 ret = hclge_fd_check_spec(hdev, fs, &unused);
4203 if (ret) {
4204 dev_err(&hdev->pdev->dev, "Check fd spec failed\n");
4205 return ret;
4206 }
4207
4208 if (fs->ring_cookie == RX_CLS_FLOW_DISC) {
4209 action = HCLGE_FD_ACTION_DROP_PACKET;
4210 } else {
4211 u32 ring = ethtool_get_flow_spec_ring(fs->ring_cookie);
4212 u8 vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie);
4213 u16 tqps;
4214
4215 dst_vport_id = vf ? hdev->vport[vf].vport_id : vport->vport_id;
4216 tqps = vf ? hdev->vport[vf].alloc_tqps : vport->alloc_tqps;
4217
4218 if (ring >= tqps) {
4219 dev_err(&hdev->pdev->dev,
4220 "Error: queue id (%d) > max tqp num (%d)\n",
4221 ring, tqps - 1);
4222 return -EINVAL;
4223 }
4224
4225 if (vf > hdev->num_req_vfs) {
4226 dev_err(&hdev->pdev->dev,
4227 "Error: vf id (%d) > max vf num (%d)\n",
4228 vf, hdev->num_req_vfs);
4229 return -EINVAL;
4230 }
4231
4232 action = HCLGE_FD_ACTION_ACCEPT_PACKET;
4233 q_index = ring;
4234 }
4235
4236 rule = kzalloc(sizeof(*rule), GFP_KERNEL);
4237 if (!rule)
4238 return -ENOMEM;
4239
4240 ret = hclge_fd_get_tuple(hdev, fs, rule);
4241 if (ret)
4242 goto free_rule;
4243
4244 rule->flow_type = fs->flow_type;
4245
4246 rule->location = fs->location;
4247 rule->unused_tuple = unused;
4248 rule->vf_id = dst_vport_id;
4249 rule->queue_id = q_index;
4250 rule->action = action;
4251
4252 ret = hclge_config_action(hdev, HCLGE_FD_STAGE_1, rule);
4253 if (ret)
4254 goto free_rule;
4255
4256 ret = hclge_config_key(hdev, HCLGE_FD_STAGE_1, rule);
4257 if (ret)
4258 goto free_rule;
4259
4260 ret = hclge_fd_update_rule_list(hdev, rule, fs->location, true);
4261 if (ret)
4262 goto free_rule;
4263
4264 return ret;
4265
4266free_rule:
4267 kfree(rule);
4268 return ret;
4269}
4270
4271static int hclge_del_fd_entry(struct hnae3_handle *handle,
4272 struct ethtool_rxnfc *cmd)
4273{
4274 struct hclge_vport *vport = hclge_get_vport(handle);
4275 struct hclge_dev *hdev = vport->back;
4276 struct ethtool_rx_flow_spec *fs;
4277 int ret;
4278
4279 if (!hnae3_dev_fd_supported(hdev))
4280 return -EOPNOTSUPP;
4281
4282 fs = (struct ethtool_rx_flow_spec *)&cmd->fs;
4283
4284 if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1])
4285 return -EINVAL;
4286
4287 if (!hclge_fd_rule_exist(hdev, fs->location)) {
4288 dev_err(&hdev->pdev->dev,
4289 "Delete fail, rule %d is inexistent\n",
4290 fs->location);
4291 return -ENOENT;
4292 }
4293
4294 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true,
4295 fs->location, NULL, false);
4296 if (ret)
4297 return ret;
4298
4299 return hclge_fd_update_rule_list(hdev, NULL, fs->location,
4300 false);
4301}
4302
4303static void hclge_del_all_fd_entries(struct hnae3_handle *handle,
4304 bool clear_list)
4305{
4306 struct hclge_vport *vport = hclge_get_vport(handle);
4307 struct hclge_dev *hdev = vport->back;
4308 struct hclge_fd_rule *rule;
4309 struct hlist_node *node;
4310
4311 if (!hnae3_dev_fd_supported(hdev))
4312 return;
4313
4314 if (clear_list) {
4315 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list,
4316 rule_node) {
4317 hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true,
4318 rule->location, NULL, false);
4319 hlist_del(&rule->rule_node);
4320 kfree(rule);
4321 hdev->hclge_fd_rule_num--;
4322 }
4323 } else {
4324 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list,
4325 rule_node)
4326 hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true,
4327 rule->location, NULL, false);
4328 }
4329}
4330
4331static int hclge_restore_fd_entries(struct hnae3_handle *handle)
4332{
4333 struct hclge_vport *vport = hclge_get_vport(handle);
4334 struct hclge_dev *hdev = vport->back;
4335 struct hclge_fd_rule *rule;
4336 struct hlist_node *node;
4337 int ret;
4338
4339 if (!hnae3_dev_fd_supported(hdev))
4340 return -EOPNOTSUPP;
4341
4342 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) {
4343 ret = hclge_config_action(hdev, HCLGE_FD_STAGE_1, rule);
4344 if (!ret)
4345 ret = hclge_config_key(hdev, HCLGE_FD_STAGE_1, rule);
4346
4347 if (ret) {
4348 dev_warn(&hdev->pdev->dev,
4349 "Restore rule %d failed, remove it\n",
4350 rule->location);
4351 hlist_del(&rule->rule_node);
4352 kfree(rule);
4353 hdev->hclge_fd_rule_num--;
4354 }
4355 }
4356 return 0;
4357}
4358
4359static int hclge_get_fd_rule_cnt(struct hnae3_handle *handle,
4360 struct ethtool_rxnfc *cmd)
4361{
4362 struct hclge_vport *vport = hclge_get_vport(handle);
4363 struct hclge_dev *hdev = vport->back;
4364
4365 if (!hnae3_dev_fd_supported(hdev))
4366 return -EOPNOTSUPP;
4367
4368 cmd->rule_cnt = hdev->hclge_fd_rule_num;
4369 cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1];
4370
4371 return 0;
4372}
4373
4374static int hclge_get_fd_rule_info(struct hnae3_handle *handle,
4375 struct ethtool_rxnfc *cmd)
4376{
4377 struct hclge_vport *vport = hclge_get_vport(handle);
4378 struct hclge_fd_rule *rule = NULL;
4379 struct hclge_dev *hdev = vport->back;
4380 struct ethtool_rx_flow_spec *fs;
4381 struct hlist_node *node2;
4382
4383 if (!hnae3_dev_fd_supported(hdev))
4384 return -EOPNOTSUPP;
4385
4386 fs = (struct ethtool_rx_flow_spec *)&cmd->fs;
4387
4388 hlist_for_each_entry_safe(rule, node2, &hdev->fd_rule_list, rule_node) {
4389 if (rule->location >= fs->location)
4390 break;
4391 }
4392
4393 if (!rule || fs->location != rule->location)
4394 return -ENOENT;
4395
4396 fs->flow_type = rule->flow_type;
4397 switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
4398 case SCTP_V4_FLOW:
4399 case TCP_V4_FLOW:
4400 case UDP_V4_FLOW:
4401 fs->h_u.tcp_ip4_spec.ip4src =
4402 cpu_to_be32(rule->tuples.src_ip[3]);
4403 fs->m_u.tcp_ip4_spec.ip4src =
4404 rule->unused_tuple & BIT(INNER_SRC_IP) ?
4405 0 : cpu_to_be32(rule->tuples_mask.src_ip[3]);
4406
4407 fs->h_u.tcp_ip4_spec.ip4dst =
4408 cpu_to_be32(rule->tuples.dst_ip[3]);
4409 fs->m_u.tcp_ip4_spec.ip4dst =
4410 rule->unused_tuple & BIT(INNER_DST_IP) ?
4411 0 : cpu_to_be32(rule->tuples_mask.dst_ip[3]);
4412
4413 fs->h_u.tcp_ip4_spec.psrc = cpu_to_be16(rule->tuples.src_port);
4414 fs->m_u.tcp_ip4_spec.psrc =
4415 rule->unused_tuple & BIT(INNER_SRC_PORT) ?
4416 0 : cpu_to_be16(rule->tuples_mask.src_port);
4417
4418 fs->h_u.tcp_ip4_spec.pdst = cpu_to_be16(rule->tuples.dst_port);
4419 fs->m_u.tcp_ip4_spec.pdst =
4420 rule->unused_tuple & BIT(INNER_DST_PORT) ?
4421 0 : cpu_to_be16(rule->tuples_mask.dst_port);
4422
4423 fs->h_u.tcp_ip4_spec.tos = rule->tuples.ip_tos;
4424 fs->m_u.tcp_ip4_spec.tos =
4425 rule->unused_tuple & BIT(INNER_IP_TOS) ?
4426 0 : rule->tuples_mask.ip_tos;
4427
4428 break;
4429 case IP_USER_FLOW:
4430 fs->h_u.usr_ip4_spec.ip4src =
4431 cpu_to_be32(rule->tuples.src_ip[3]);
4432 fs->m_u.tcp_ip4_spec.ip4src =
4433 rule->unused_tuple & BIT(INNER_SRC_IP) ?
4434 0 : cpu_to_be32(rule->tuples_mask.src_ip[3]);
4435
4436 fs->h_u.usr_ip4_spec.ip4dst =
4437 cpu_to_be32(rule->tuples.dst_ip[3]);
4438 fs->m_u.usr_ip4_spec.ip4dst =
4439 rule->unused_tuple & BIT(INNER_DST_IP) ?
4440 0 : cpu_to_be32(rule->tuples_mask.dst_ip[3]);
4441
4442 fs->h_u.usr_ip4_spec.tos = rule->tuples.ip_tos;
4443 fs->m_u.usr_ip4_spec.tos =
4444 rule->unused_tuple & BIT(INNER_IP_TOS) ?
4445 0 : rule->tuples_mask.ip_tos;
4446
4447 fs->h_u.usr_ip4_spec.proto = rule->tuples.ip_proto;
4448 fs->m_u.usr_ip4_spec.proto =
4449 rule->unused_tuple & BIT(INNER_IP_PROTO) ?
4450 0 : rule->tuples_mask.ip_proto;
4451
4452 fs->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
4453
4454 break;
4455 case SCTP_V6_FLOW:
4456 case TCP_V6_FLOW:
4457 case UDP_V6_FLOW:
4458 cpu_to_be32_array(fs->h_u.tcp_ip6_spec.ip6src,
4459 rule->tuples.src_ip, 4);
4460 if (rule->unused_tuple & BIT(INNER_SRC_IP))
4461 memset(fs->m_u.tcp_ip6_spec.ip6src, 0, sizeof(int) * 4);
4462 else
4463 cpu_to_be32_array(fs->m_u.tcp_ip6_spec.ip6src,
4464 rule->tuples_mask.src_ip, 4);
4465
4466 cpu_to_be32_array(fs->h_u.tcp_ip6_spec.ip6dst,
4467 rule->tuples.dst_ip, 4);
4468 if (rule->unused_tuple & BIT(INNER_DST_IP))
4469 memset(fs->m_u.tcp_ip6_spec.ip6dst, 0, sizeof(int) * 4);
4470 else
4471 cpu_to_be32_array(fs->m_u.tcp_ip6_spec.ip6dst,
4472 rule->tuples_mask.dst_ip, 4);
4473
4474 fs->h_u.tcp_ip6_spec.psrc = cpu_to_be16(rule->tuples.src_port);
4475 fs->m_u.tcp_ip6_spec.psrc =
4476 rule->unused_tuple & BIT(INNER_SRC_PORT) ?
4477 0 : cpu_to_be16(rule->tuples_mask.src_port);
4478
4479 fs->h_u.tcp_ip6_spec.pdst = cpu_to_be16(rule->tuples.dst_port);
4480 fs->m_u.tcp_ip6_spec.pdst =
4481 rule->unused_tuple & BIT(INNER_DST_PORT) ?
4482 0 : cpu_to_be16(rule->tuples_mask.dst_port);
4483
4484 break;
4485 case IPV6_USER_FLOW:
4486 cpu_to_be32_array(fs->h_u.usr_ip6_spec.ip6src,
4487 rule->tuples.src_ip, 4);
4488 if (rule->unused_tuple & BIT(INNER_SRC_IP))
4489 memset(fs->m_u.usr_ip6_spec.ip6src, 0, sizeof(int) * 4);
4490 else
4491 cpu_to_be32_array(fs->m_u.usr_ip6_spec.ip6src,
4492 rule->tuples_mask.src_ip, 4);
4493
4494 cpu_to_be32_array(fs->h_u.usr_ip6_spec.ip6dst,
4495 rule->tuples.dst_ip, 4);
4496 if (rule->unused_tuple & BIT(INNER_DST_IP))
4497 memset(fs->m_u.usr_ip6_spec.ip6dst, 0, sizeof(int) * 4);
4498 else
4499 cpu_to_be32_array(fs->m_u.usr_ip6_spec.ip6dst,
4500 rule->tuples_mask.dst_ip, 4);
4501
4502 fs->h_u.usr_ip6_spec.l4_proto = rule->tuples.ip_proto;
4503 fs->m_u.usr_ip6_spec.l4_proto =
4504 rule->unused_tuple & BIT(INNER_IP_PROTO) ?
4505 0 : rule->tuples_mask.ip_proto;
4506
4507 break;
4508 case ETHER_FLOW:
4509 ether_addr_copy(fs->h_u.ether_spec.h_source,
4510 rule->tuples.src_mac);
4511 if (rule->unused_tuple & BIT(INNER_SRC_MAC))
4512 eth_zero_addr(fs->m_u.ether_spec.h_source);
4513 else
4514 ether_addr_copy(fs->m_u.ether_spec.h_source,
4515 rule->tuples_mask.src_mac);
4516
4517 ether_addr_copy(fs->h_u.ether_spec.h_dest,
4518 rule->tuples.dst_mac);
4519 if (rule->unused_tuple & BIT(INNER_DST_MAC))
4520 eth_zero_addr(fs->m_u.ether_spec.h_dest);
4521 else
4522 ether_addr_copy(fs->m_u.ether_spec.h_dest,
4523 rule->tuples_mask.dst_mac);
4524
4525 fs->h_u.ether_spec.h_proto =
4526 cpu_to_be16(rule->tuples.ether_proto);
4527 fs->m_u.ether_spec.h_proto =
4528 rule->unused_tuple & BIT(INNER_ETH_TYPE) ?
4529 0 : cpu_to_be16(rule->tuples_mask.ether_proto);
4530
4531 break;
4532 default:
4533 return -EOPNOTSUPP;
4534 }
4535
4536 if (fs->flow_type & FLOW_EXT) {
4537 fs->h_ext.vlan_tci = cpu_to_be16(rule->tuples.vlan_tag1);
4538 fs->m_ext.vlan_tci =
4539 rule->unused_tuple & BIT(INNER_VLAN_TAG_FST) ?
4540 cpu_to_be16(VLAN_VID_MASK) :
4541 cpu_to_be16(rule->tuples_mask.vlan_tag1);
4542 }
4543
4544 if (fs->flow_type & FLOW_MAC_EXT) {
4545 ether_addr_copy(fs->h_ext.h_dest, rule->tuples.dst_mac);
4546 if (rule->unused_tuple & BIT(INNER_DST_MAC))
4547 eth_zero_addr(fs->m_u.ether_spec.h_dest);
4548 else
4549 ether_addr_copy(fs->m_u.ether_spec.h_dest,
4550 rule->tuples_mask.dst_mac);
4551 }
4552
4553 if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) {
4554 fs->ring_cookie = RX_CLS_FLOW_DISC;
4555 } else {
4556 u64 vf_id;
4557
4558 fs->ring_cookie = rule->queue_id;
4559 vf_id = rule->vf_id;
4560 vf_id <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF;
4561 fs->ring_cookie |= vf_id;
4562 }
4563
4564 return 0;
4565}
4566
4567static int hclge_get_all_rules(struct hnae3_handle *handle,
4568 struct ethtool_rxnfc *cmd, u32 *rule_locs)
4569{
4570 struct hclge_vport *vport = hclge_get_vport(handle);
4571 struct hclge_dev *hdev = vport->back;
4572 struct hclge_fd_rule *rule;
4573 struct hlist_node *node2;
4574 int cnt = 0;
4575
4576 if (!hnae3_dev_fd_supported(hdev))
4577 return -EOPNOTSUPP;
4578
4579 cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1];
4580
4581 hlist_for_each_entry_safe(rule, node2,
4582 &hdev->fd_rule_list, rule_node) {
4583 if (cnt == cmd->rule_cnt)
4584 return -EMSGSIZE;
4585
4586 rule_locs[cnt] = rule->location;
4587 cnt++;
4588 }
4589
4590 cmd->rule_cnt = cnt;
4591
4592 return 0;
4593}
4594
4595static void hclge_enable_fd(struct hnae3_handle *handle, bool enable)
4596{
4597 struct hclge_vport *vport = hclge_get_vport(handle);
4598 struct hclge_dev *hdev = vport->back;
4599
4600 hdev->fd_cfg.fd_en = enable;
4601 if (!enable)
4602 hclge_del_all_fd_entries(handle, false);
4603 else
4604 hclge_restore_fd_entries(handle);
3653} 4605}
3654 4606
3655static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable) 4607static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
@@ -3661,20 +4613,20 @@ static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
3661 int ret; 4613 int ret;
3662 4614
3663 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false); 4615 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false);
3664 hnae_set_bit(loop_en, HCLGE_MAC_TX_EN_B, enable); 4616 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, enable);
3665 hnae_set_bit(loop_en, HCLGE_MAC_RX_EN_B, enable); 4617 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, enable);
3666 hnae_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, enable); 4618 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, enable);
3667 hnae_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, enable); 4619 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, enable);
3668 hnae_set_bit(loop_en, HCLGE_MAC_1588_TX_B, 0); 4620 hnae3_set_bit(loop_en, HCLGE_MAC_1588_TX_B, 0);
3669 hnae_set_bit(loop_en, HCLGE_MAC_1588_RX_B, 0); 4621 hnae3_set_bit(loop_en, HCLGE_MAC_1588_RX_B, 0);
3670 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0); 4622 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
3671 hnae_set_bit(loop_en, HCLGE_MAC_LINE_LP_B, 0); 4623 hnae3_set_bit(loop_en, HCLGE_MAC_LINE_LP_B, 0);
3672 hnae_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, enable); 4624 hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, enable);
3673 hnae_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, enable); 4625 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, enable);
3674 hnae_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, enable); 4626 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, enable);
3675 hnae_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable); 4627 hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable);
3676 hnae_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable); 4628 hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable);
3677 hnae_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable); 4629 hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable);
3678 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 4630 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
3679 4631
3680 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4632 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
@@ -3683,57 +4635,105 @@ static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
3683 "mac enable fail, ret =%d.\n", ret); 4635 "mac enable fail, ret =%d.\n", ret);
3684} 4636}
3685 4637
3686static int hclge_set_loopback(struct hnae3_handle *handle, 4638static int hclge_set_app_loopback(struct hclge_dev *hdev, bool en)
3687 enum hnae3_loop loop_mode, bool en)
3688{ 4639{
3689 struct hclge_vport *vport = hclge_get_vport(handle);
3690 struct hclge_config_mac_mode_cmd *req; 4640 struct hclge_config_mac_mode_cmd *req;
3691 struct hclge_dev *hdev = vport->back;
3692 struct hclge_desc desc; 4641 struct hclge_desc desc;
3693 u32 loop_en; 4642 u32 loop_en;
3694 int ret; 4643 int ret;
3695 4644
4645 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0];
4646 /* 1 Read out the MAC mode config at first */
4647 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true);
4648 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4649 if (ret) {
4650 dev_err(&hdev->pdev->dev,
4651 "mac loopback get fail, ret =%d.\n", ret);
4652 return ret;
4653 }
4654
4655 /* 2 Then setup the loopback flag */
4656 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en);
4657 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0);
4658 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, en ? 1 : 0);
4659 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, en ? 1 : 0);
4660
4661 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
4662
4663 /* 3 Config mac work mode with loopback flag
4664 * and its original configure parameters
4665 */
4666 hclge_cmd_reuse_desc(&desc, false);
4667 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4668 if (ret)
4669 dev_err(&hdev->pdev->dev,
4670 "mac loopback set fail, ret =%d.\n", ret);
4671 return ret;
4672}
4673
4674static int hclge_set_serdes_loopback(struct hclge_dev *hdev, bool en,
4675 enum hnae3_loop loop_mode)
4676{
4677#define HCLGE_SERDES_RETRY_MS 10
4678#define HCLGE_SERDES_RETRY_NUM 100
4679 struct hclge_serdes_lb_cmd *req;
4680 struct hclge_desc desc;
4681 int ret, i = 0;
4682 u8 loop_mode_b;
4683
4684 req = (struct hclge_serdes_lb_cmd *)desc.data;
4685 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK, false);
4686
3696 switch (loop_mode) { 4687 switch (loop_mode) {
3697 case HNAE3_MAC_INTER_LOOP_MAC: 4688 case HNAE3_LOOP_SERIAL_SERDES:
3698 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0]; 4689 loop_mode_b = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B;
3699 /* 1 Read out the MAC mode config at first */ 4690 break;
3700 hclge_cmd_setup_basic_desc(&desc, 4691 case HNAE3_LOOP_PARALLEL_SERDES:
3701 HCLGE_OPC_CONFIG_MAC_MODE, 4692 loop_mode_b = HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B;
4693 break;
4694 default:
4695 dev_err(&hdev->pdev->dev,
4696 "unsupported serdes loopback mode %d\n", loop_mode);
4697 return -ENOTSUPP;
4698 }
4699
4700 if (en) {
4701 req->enable = loop_mode_b;
4702 req->mask = loop_mode_b;
4703 } else {
4704 req->mask = loop_mode_b;
4705 }
4706
4707 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4708 if (ret) {
4709 dev_err(&hdev->pdev->dev,
4710 "serdes loopback set fail, ret = %d\n", ret);
4711 return ret;
4712 }
4713
4714 do {
4715 msleep(HCLGE_SERDES_RETRY_MS);
4716 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK,
3702 true); 4717 true);
3703 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4718 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3704 if (ret) { 4719 if (ret) {
3705 dev_err(&hdev->pdev->dev, 4720 dev_err(&hdev->pdev->dev,
3706 "mac loopback get fail, ret =%d.\n", 4721 "serdes loopback get, ret = %d\n", ret);
3707 ret);
3708 return ret; 4722 return ret;
3709 } 4723 }
4724 } while (++i < HCLGE_SERDES_RETRY_NUM &&
4725 !(req->result & HCLGE_CMD_SERDES_DONE_B));
3710 4726
3711 /* 2 Then setup the loopback flag */ 4727 if (!(req->result & HCLGE_CMD_SERDES_DONE_B)) {
3712 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en); 4728 dev_err(&hdev->pdev->dev, "serdes loopback set timeout\n");
3713 if (en) 4729 return -EBUSY;
3714 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 1); 4730 } else if (!(req->result & HCLGE_CMD_SERDES_SUCCESS_B)) {
3715 else 4731 dev_err(&hdev->pdev->dev, "serdes loopback set failed in fw\n");
3716 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0); 4732 return -EIO;
3717
3718 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
3719
3720 /* 3 Config mac work mode with loopback flag
3721 * and its original configure parameters
3722 */
3723 hclge_cmd_reuse_desc(&desc, false);
3724 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3725 if (ret)
3726 dev_err(&hdev->pdev->dev,
3727 "mac loopback set fail, ret =%d.\n", ret);
3728 break;
3729 default:
3730 ret = -ENOTSUPP;
3731 dev_err(&hdev->pdev->dev,
3732 "loop_mode %d is not supported\n", loop_mode);
3733 break;
3734 } 4733 }
3735 4734
3736 return ret; 4735 hclge_cfg_mac_mode(hdev, en);
4736 return 0;
3737} 4737}
3738 4738
3739static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id, 4739static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id,
@@ -3756,6 +4756,37 @@ static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id,
3756 return ret; 4756 return ret;
3757} 4757}
3758 4758
4759static int hclge_set_loopback(struct hnae3_handle *handle,
4760 enum hnae3_loop loop_mode, bool en)
4761{
4762 struct hclge_vport *vport = hclge_get_vport(handle);
4763 struct hclge_dev *hdev = vport->back;
4764 int i, ret;
4765
4766 switch (loop_mode) {
4767 case HNAE3_LOOP_APP:
4768 ret = hclge_set_app_loopback(hdev, en);
4769 break;
4770 case HNAE3_LOOP_SERIAL_SERDES:
4771 case HNAE3_LOOP_PARALLEL_SERDES:
4772 ret = hclge_set_serdes_loopback(hdev, en, loop_mode);
4773 break;
4774 default:
4775 ret = -ENOTSUPP;
4776 dev_err(&hdev->pdev->dev,
4777 "loop_mode %d is not supported\n", loop_mode);
4778 break;
4779 }
4780
4781 for (i = 0; i < vport->alloc_tqps; i++) {
4782 ret = hclge_tqp_enable(hdev, i, 0, en);
4783 if (ret)
4784 return ret;
4785 }
4786
4787 return 0;
4788}
4789
3759static void hclge_reset_tqp_stats(struct hnae3_handle *handle) 4790static void hclge_reset_tqp_stats(struct hnae3_handle *handle)
3760{ 4791{
3761 struct hclge_vport *vport = hclge_get_vport(handle); 4792 struct hclge_vport *vport = hclge_get_vport(handle);
@@ -3774,7 +4805,7 @@ static int hclge_ae_start(struct hnae3_handle *handle)
3774{ 4805{
3775 struct hclge_vport *vport = hclge_get_vport(handle); 4806 struct hclge_vport *vport = hclge_get_vport(handle);
3776 struct hclge_dev *hdev = vport->back; 4807 struct hclge_dev *hdev = vport->back;
3777 int i, ret; 4808 int i;
3778 4809
3779 for (i = 0; i < vport->alloc_tqps; i++) 4810 for (i = 0; i < vport->alloc_tqps; i++)
3780 hclge_tqp_enable(hdev, i, 0, true); 4811 hclge_tqp_enable(hdev, i, 0, true);
@@ -3783,16 +4814,12 @@ static int hclge_ae_start(struct hnae3_handle *handle)
3783 hclge_cfg_mac_mode(hdev, true); 4814 hclge_cfg_mac_mode(hdev, true);
3784 clear_bit(HCLGE_STATE_DOWN, &hdev->state); 4815 clear_bit(HCLGE_STATE_DOWN, &hdev->state);
3785 mod_timer(&hdev->service_timer, jiffies + HZ); 4816 mod_timer(&hdev->service_timer, jiffies + HZ);
4817 hdev->hw.mac.link = 0;
3786 4818
3787 /* reset tqp stats */ 4819 /* reset tqp stats */
3788 hclge_reset_tqp_stats(handle); 4820 hclge_reset_tqp_stats(handle);
3789 4821
3790 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 4822 hclge_mac_start_phy(hdev);
3791 return 0;
3792
3793 ret = hclge_mac_start_phy(hdev);
3794 if (ret)
3795 return ret;
3796 4823
3797 return 0; 4824 return 0;
3798} 4825}
@@ -3803,11 +4830,16 @@ static void hclge_ae_stop(struct hnae3_handle *handle)
3803 struct hclge_dev *hdev = vport->back; 4830 struct hclge_dev *hdev = vport->back;
3804 int i; 4831 int i;
3805 4832
4833 set_bit(HCLGE_STATE_DOWN, &hdev->state);
4834
3806 del_timer_sync(&hdev->service_timer); 4835 del_timer_sync(&hdev->service_timer);
3807 cancel_work_sync(&hdev->service_task); 4836 cancel_work_sync(&hdev->service_task);
4837 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
3808 4838
3809 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 4839 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) {
4840 hclge_mac_stop_phy(hdev);
3810 return; 4841 return;
4842 }
3811 4843
3812 for (i = 0; i < vport->alloc_tqps; i++) 4844 for (i = 0; i < vport->alloc_tqps; i++)
3813 hclge_tqp_enable(hdev, i, 0, false); 4845 hclge_tqp_enable(hdev, i, 0, false);
@@ -3819,6 +4851,8 @@ static void hclge_ae_stop(struct hnae3_handle *handle)
3819 4851
3820 /* reset tqp stats */ 4852 /* reset tqp stats */
3821 hclge_reset_tqp_stats(handle); 4853 hclge_reset_tqp_stats(handle);
4854 del_timer_sync(&hdev->service_timer);
4855 cancel_work_sync(&hdev->service_task);
3822 hclge_update_link_status(hdev); 4856 hclge_update_link_status(hdev);
3823} 4857}
3824 4858
@@ -3919,7 +4953,7 @@ static bool hclge_is_all_function_id_zero(struct hclge_desc *desc)
3919#define HCLGE_FUNC_NUMBER_PER_DESC 6 4953#define HCLGE_FUNC_NUMBER_PER_DESC 6
3920 int i, j; 4954 int i, j;
3921 4955
3922 for (i = 0; i < HCLGE_DESC_NUMBER; i++) 4956 for (i = 1; i < HCLGE_DESC_NUMBER; i++)
3923 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++) 4957 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++)
3924 if (desc[i].data[j]) 4958 if (desc[i].data[j])
3925 return false; 4959 return false;
@@ -3939,99 +4973,6 @@ static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req,
3939 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff); 4973 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff);
3940} 4974}
3941 4975
3942static u16 hclge_get_mac_addr_to_mta_index(struct hclge_vport *vport,
3943 const u8 *addr)
3944{
3945 u16 high_val = addr[1] | (addr[0] << 8);
3946 struct hclge_dev *hdev = vport->back;
3947 u32 rsh = 4 - hdev->mta_mac_sel_type;
3948 u16 ret_val = (high_val >> rsh) & 0xfff;
3949
3950 return ret_val;
3951}
3952
3953static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
3954 enum hclge_mta_dmac_sel_type mta_mac_sel,
3955 bool enable)
3956{
3957 struct hclge_mta_filter_mode_cmd *req;
3958 struct hclge_desc desc;
3959 int ret;
3960
3961 req = (struct hclge_mta_filter_mode_cmd *)desc.data;
3962 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_MODE_CFG, false);
3963
3964 hnae_set_bit(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_EN_B,
3965 enable);
3966 hnae_set_field(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_SEL_M,
3967 HCLGE_CFG_MTA_MAC_SEL_S, mta_mac_sel);
3968
3969 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3970 if (ret) {
3971 dev_err(&hdev->pdev->dev,
3972 "Config mat filter mode failed for cmd_send, ret =%d.\n",
3973 ret);
3974 return ret;
3975 }
3976
3977 return 0;
3978}
3979
3980int hclge_cfg_func_mta_filter(struct hclge_dev *hdev,
3981 u8 func_id,
3982 bool enable)
3983{
3984 struct hclge_cfg_func_mta_filter_cmd *req;
3985 struct hclge_desc desc;
3986 int ret;
3987
3988 req = (struct hclge_cfg_func_mta_filter_cmd *)desc.data;
3989 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_FUNC_CFG, false);
3990
3991 hnae_set_bit(req->accept, HCLGE_CFG_FUNC_MTA_ACCEPT_B,
3992 enable);
3993 req->function_id = func_id;
3994
3995 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3996 if (ret) {
3997 dev_err(&hdev->pdev->dev,
3998 "Config func_id enable failed for cmd_send, ret =%d.\n",
3999 ret);
4000 return ret;
4001 }
4002
4003 return 0;
4004}
4005
4006static int hclge_set_mta_table_item(struct hclge_vport *vport,
4007 u16 idx,
4008 bool enable)
4009{
4010 struct hclge_dev *hdev = vport->back;
4011 struct hclge_cfg_func_mta_item_cmd *req;
4012 struct hclge_desc desc;
4013 u16 item_idx = 0;
4014 int ret;
4015
4016 req = (struct hclge_cfg_func_mta_item_cmd *)desc.data;
4017 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_TBL_ITEM_CFG, false);
4018 hnae_set_bit(req->accept, HCLGE_CFG_MTA_ITEM_ACCEPT_B, enable);
4019
4020 hnae_set_field(item_idx, HCLGE_CFG_MTA_ITEM_IDX_M,
4021 HCLGE_CFG_MTA_ITEM_IDX_S, idx);
4022 req->item_idx = cpu_to_le16(item_idx);
4023
4024 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4025 if (ret) {
4026 dev_err(&hdev->pdev->dev,
4027 "Config mta table item failed for cmd_send, ret =%d.\n",
4028 ret);
4029 return ret;
4030 }
4031
4032 return 0;
4033}
4034
4035static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport, 4976static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport,
4036 struct hclge_mac_vlan_tbl_entry_cmd *req) 4977 struct hclge_mac_vlan_tbl_entry_cmd *req)
4037{ 4978{
@@ -4155,6 +5096,118 @@ static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport,
4155 return cfg_status; 5096 return cfg_status;
4156} 5097}
4157 5098
5099static int hclge_init_umv_space(struct hclge_dev *hdev)
5100{
5101 u16 allocated_size = 0;
5102 int ret;
5103
5104 ret = hclge_set_umv_space(hdev, hdev->wanted_umv_size, &allocated_size,
5105 true);
5106 if (ret)
5107 return ret;
5108
5109 if (allocated_size < hdev->wanted_umv_size)
5110 dev_warn(&hdev->pdev->dev,
5111 "Alloc umv space failed, want %d, get %d\n",
5112 hdev->wanted_umv_size, allocated_size);
5113
5114 mutex_init(&hdev->umv_mutex);
5115 hdev->max_umv_size = allocated_size;
5116 hdev->priv_umv_size = hdev->max_umv_size / (hdev->num_req_vfs + 2);
5117 hdev->share_umv_size = hdev->priv_umv_size +
5118 hdev->max_umv_size % (hdev->num_req_vfs + 2);
5119
5120 return 0;
5121}
5122
5123static int hclge_uninit_umv_space(struct hclge_dev *hdev)
5124{
5125 int ret;
5126
5127 if (hdev->max_umv_size > 0) {
5128 ret = hclge_set_umv_space(hdev, hdev->max_umv_size, NULL,
5129 false);
5130 if (ret)
5131 return ret;
5132 hdev->max_umv_size = 0;
5133 }
5134 mutex_destroy(&hdev->umv_mutex);
5135
5136 return 0;
5137}
5138
5139static int hclge_set_umv_space(struct hclge_dev *hdev, u16 space_size,
5140 u16 *allocated_size, bool is_alloc)
5141{
5142 struct hclge_umv_spc_alc_cmd *req;
5143 struct hclge_desc desc;
5144 int ret;
5145
5146 req = (struct hclge_umv_spc_alc_cmd *)desc.data;
5147 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_ALLOCATE, false);
5148 hnae3_set_bit(req->allocate, HCLGE_UMV_SPC_ALC_B, !is_alloc);
5149 req->space_size = cpu_to_le32(space_size);
5150
5151 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5152 if (ret) {
5153 dev_err(&hdev->pdev->dev,
5154 "%s umv space failed for cmd_send, ret =%d\n",
5155 is_alloc ? "allocate" : "free", ret);
5156 return ret;
5157 }
5158
5159 if (is_alloc && allocated_size)
5160 *allocated_size = le32_to_cpu(desc.data[1]);
5161
5162 return 0;
5163}
5164
5165static void hclge_reset_umv_space(struct hclge_dev *hdev)
5166{
5167 struct hclge_vport *vport;
5168 int i;
5169
5170 for (i = 0; i < hdev->num_alloc_vport; i++) {
5171 vport = &hdev->vport[i];
5172 vport->used_umv_num = 0;
5173 }
5174
5175 mutex_lock(&hdev->umv_mutex);
5176 hdev->share_umv_size = hdev->priv_umv_size +
5177 hdev->max_umv_size % (hdev->num_req_vfs + 2);
5178 mutex_unlock(&hdev->umv_mutex);
5179}
5180
5181static bool hclge_is_umv_space_full(struct hclge_vport *vport)
5182{
5183 struct hclge_dev *hdev = vport->back;
5184 bool is_full;
5185
5186 mutex_lock(&hdev->umv_mutex);
5187 is_full = (vport->used_umv_num >= hdev->priv_umv_size &&
5188 hdev->share_umv_size == 0);
5189 mutex_unlock(&hdev->umv_mutex);
5190
5191 return is_full;
5192}
5193
5194static void hclge_update_umv_space(struct hclge_vport *vport, bool is_free)
5195{
5196 struct hclge_dev *hdev = vport->back;
5197
5198 mutex_lock(&hdev->umv_mutex);
5199 if (is_free) {
5200 if (vport->used_umv_num > hdev->priv_umv_size)
5201 hdev->share_umv_size++;
5202 vport->used_umv_num--;
5203 } else {
5204 if (vport->used_umv_num >= hdev->priv_umv_size)
5205 hdev->share_umv_size--;
5206 vport->used_umv_num++;
5207 }
5208 mutex_unlock(&hdev->umv_mutex);
5209}
5210
4158static int hclge_add_uc_addr(struct hnae3_handle *handle, 5211static int hclge_add_uc_addr(struct hnae3_handle *handle,
4159 const unsigned char *addr) 5212 const unsigned char *addr)
4160{ 5213{
@@ -4186,17 +5239,10 @@ int hclge_add_uc_addr_common(struct hclge_vport *vport,
4186 } 5239 }
4187 5240
4188 memset(&req, 0, sizeof(req)); 5241 memset(&req, 0, sizeof(req));
4189 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 5242 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4190 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 5243
4191 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 0); 5244 hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M,
4192 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 5245 HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
4193
4194 hnae_set_bit(egress_port, HCLGE_MAC_EPORT_SW_EN_B, 0);
4195 hnae_set_bit(egress_port, HCLGE_MAC_EPORT_TYPE_B, 0);
4196 hnae_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M,
4197 HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
4198 hnae_set_field(egress_port, HCLGE_MAC_EPORT_PFID_M,
4199 HCLGE_MAC_EPORT_PFID_S, 0);
4200 5246
4201 req.egress_port = cpu_to_le16(egress_port); 5247 req.egress_port = cpu_to_le16(egress_port);
4202 5248
@@ -4207,8 +5253,19 @@ int hclge_add_uc_addr_common(struct hclge_vport *vport,
4207 * is not allowed in the mac vlan table. 5253 * is not allowed in the mac vlan table.
4208 */ 5254 */
4209 ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false); 5255 ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false);
4210 if (ret == -ENOENT) 5256 if (ret == -ENOENT) {
4211 return hclge_add_mac_vlan_tbl(vport, &req, NULL); 5257 if (!hclge_is_umv_space_full(vport)) {
5258 ret = hclge_add_mac_vlan_tbl(vport, &req, NULL);
5259 if (!ret)
5260 hclge_update_umv_space(vport, false);
5261 return ret;
5262 }
5263
5264 dev_err(&hdev->pdev->dev, "UC MAC table full(%u)\n",
5265 hdev->priv_umv_size);
5266
5267 return -ENOSPC;
5268 }
4212 5269
4213 /* check if we just hit the duplicate */ 5270 /* check if we just hit the duplicate */
4214 if (!ret) 5271 if (!ret)
@@ -4247,10 +5304,12 @@ int hclge_rm_uc_addr_common(struct hclge_vport *vport,
4247 } 5304 }
4248 5305
4249 memset(&req, 0, sizeof(req)); 5306 memset(&req, 0, sizeof(req));
4250 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 5307 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4251 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 5308 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4252 hclge_prepare_mac_addr(&req, addr); 5309 hclge_prepare_mac_addr(&req, addr);
4253 ret = hclge_remove_mac_vlan_tbl(vport, &req); 5310 ret = hclge_remove_mac_vlan_tbl(vport, &req);
5311 if (!ret)
5312 hclge_update_umv_space(vport, true);
4254 5313
4255 return ret; 5314 return ret;
4256} 5315}
@@ -4260,7 +5319,7 @@ static int hclge_add_mc_addr(struct hnae3_handle *handle,
4260{ 5319{
4261 struct hclge_vport *vport = hclge_get_vport(handle); 5320 struct hclge_vport *vport = hclge_get_vport(handle);
4262 5321
4263 return hclge_add_mc_addr_common(vport, addr); 5322 return hclge_add_mc_addr_common(vport, addr);
4264} 5323}
4265 5324
4266int hclge_add_mc_addr_common(struct hclge_vport *vport, 5325int hclge_add_mc_addr_common(struct hclge_vport *vport,
@@ -4269,7 +5328,6 @@ int hclge_add_mc_addr_common(struct hclge_vport *vport,
4269 struct hclge_dev *hdev = vport->back; 5328 struct hclge_dev *hdev = vport->back;
4270 struct hclge_mac_vlan_tbl_entry_cmd req; 5329 struct hclge_mac_vlan_tbl_entry_cmd req;
4271 struct hclge_desc desc[3]; 5330 struct hclge_desc desc[3];
4272 u16 tbl_idx;
4273 int status; 5331 int status;
4274 5332
4275 /* mac addr check */ 5333 /* mac addr check */
@@ -4280,10 +5338,10 @@ int hclge_add_mc_addr_common(struct hclge_vport *vport,
4280 return -EINVAL; 5338 return -EINVAL;
4281 } 5339 }
4282 memset(&req, 0, sizeof(req)); 5340 memset(&req, 0, sizeof(req));
4283 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 5341 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4284 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 5342 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4285 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1); 5343 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4286 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 5344 hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4287 hclge_prepare_mac_addr(&req, addr); 5345 hclge_prepare_mac_addr(&req, addr);
4288 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 5346 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4289 if (!status) { 5347 if (!status) {
@@ -4299,9 +5357,8 @@ int hclge_add_mc_addr_common(struct hclge_vport *vport,
4299 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 5357 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4300 } 5358 }
4301 5359
4302 /* Set MTA table for this MAC address */ 5360 if (status == -ENOSPC)
4303 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr); 5361 dev_err(&hdev->pdev->dev, "mc mac vlan table is full\n");
4304 status = hclge_set_mta_table_item(vport, tbl_idx, true);
4305 5362
4306 return status; 5363 return status;
4307} 5364}
@@ -4321,7 +5378,6 @@ int hclge_rm_mc_addr_common(struct hclge_vport *vport,
4321 struct hclge_mac_vlan_tbl_entry_cmd req; 5378 struct hclge_mac_vlan_tbl_entry_cmd req;
4322 enum hclge_cmd_status status; 5379 enum hclge_cmd_status status;
4323 struct hclge_desc desc[3]; 5380 struct hclge_desc desc[3];
4324 u16 tbl_idx;
4325 5381
4326 /* mac addr check */ 5382 /* mac addr check */
4327 if (!is_multicast_ether_addr(addr)) { 5383 if (!is_multicast_ether_addr(addr)) {
@@ -4332,10 +5388,10 @@ int hclge_rm_mc_addr_common(struct hclge_vport *vport,
4332 } 5388 }
4333 5389
4334 memset(&req, 0, sizeof(req)); 5390 memset(&req, 0, sizeof(req));
4335 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 5391 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4336 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 5392 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4337 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1); 5393 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4338 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 5394 hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4339 hclge_prepare_mac_addr(&req, addr); 5395 hclge_prepare_mac_addr(&req, addr);
4340 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 5396 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4341 if (!status) { 5397 if (!status) {
@@ -4350,17 +5406,15 @@ int hclge_rm_mc_addr_common(struct hclge_vport *vport,
4350 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 5406 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4351 5407
4352 } else { 5408 } else {
4353 /* This mac addr do not exist, can't delete it */ 5409 /* Maybe this mac address is in mta table, but it cannot be
4354 dev_err(&hdev->pdev->dev, 5410 * deleted here because an entry of mta represents an address
4355 "Rm multicast mac addr failed, ret = %d.\n", 5411 * range rather than a specific address. the delete action to
4356 status); 5412 * all entries will take effect in update_mta_status called by
4357 return -EIO; 5413 * hns3_nic_set_rx_mode.
5414 */
5415 status = 0;
4358 } 5416 }
4359 5417
4360 /* Set MTB table for this MAC address */
4361 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
4362 status = hclge_set_mta_table_item(vport, tbl_idx, false);
4363
4364 return status; 5418 return status;
4365} 5419}
4366 5420
@@ -4506,8 +5560,20 @@ static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p,
4506 return 0; 5560 return 0;
4507} 5561}
4508 5562
5563static int hclge_do_ioctl(struct hnae3_handle *handle, struct ifreq *ifr,
5564 int cmd)
5565{
5566 struct hclge_vport *vport = hclge_get_vport(handle);
5567 struct hclge_dev *hdev = vport->back;
5568
5569 if (!hdev->hw.mac.phydev)
5570 return -EOPNOTSUPP;
5571
5572 return phy_mii_ioctl(hdev->hw.mac.phydev, ifr, cmd);
5573}
5574
4509static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type, 5575static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
4510 bool filter_en) 5576 u8 fe_type, bool filter_en)
4511{ 5577{
4512 struct hclge_vlan_filter_ctrl_cmd *req; 5578 struct hclge_vlan_filter_ctrl_cmd *req;
4513 struct hclge_desc desc; 5579 struct hclge_desc desc;
@@ -4517,31 +5583,51 @@ static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
4517 5583
4518 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data; 5584 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data;
4519 req->vlan_type = vlan_type; 5585 req->vlan_type = vlan_type;
4520 req->vlan_fe = filter_en; 5586 req->vlan_fe = filter_en ? fe_type : 0;
4521 5587
4522 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5588 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4523 if (ret) { 5589 if (ret)
4524 dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n", 5590 dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n",
4525 ret); 5591 ret);
4526 return ret;
4527 }
4528 5592
4529 return 0; 5593 return ret;
4530} 5594}
4531 5595
4532#define HCLGE_FILTER_TYPE_VF 0 5596#define HCLGE_FILTER_TYPE_VF 0
4533#define HCLGE_FILTER_TYPE_PORT 1 5597#define HCLGE_FILTER_TYPE_PORT 1
5598#define HCLGE_FILTER_FE_EGRESS_V1_B BIT(0)
5599#define HCLGE_FILTER_FE_NIC_INGRESS_B BIT(0)
5600#define HCLGE_FILTER_FE_NIC_EGRESS_B BIT(1)
5601#define HCLGE_FILTER_FE_ROCE_INGRESS_B BIT(2)
5602#define HCLGE_FILTER_FE_ROCE_EGRESS_B BIT(3)
5603#define HCLGE_FILTER_FE_EGRESS (HCLGE_FILTER_FE_NIC_EGRESS_B \
5604 | HCLGE_FILTER_FE_ROCE_EGRESS_B)
5605#define HCLGE_FILTER_FE_INGRESS (HCLGE_FILTER_FE_NIC_INGRESS_B \
5606 | HCLGE_FILTER_FE_ROCE_INGRESS_B)
4534 5607
4535static void hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable) 5608static void hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable)
4536{ 5609{
4537 struct hclge_vport *vport = hclge_get_vport(handle); 5610 struct hclge_vport *vport = hclge_get_vport(handle);
4538 struct hclge_dev *hdev = vport->back; 5611 struct hclge_dev *hdev = vport->back;
4539 5612
4540 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, enable); 5613 if (hdev->pdev->revision >= 0x21) {
5614 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
5615 HCLGE_FILTER_FE_EGRESS, enable);
5616 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT,
5617 HCLGE_FILTER_FE_INGRESS, enable);
5618 } else {
5619 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
5620 HCLGE_FILTER_FE_EGRESS_V1_B, enable);
5621 }
5622 if (enable)
5623 handle->netdev_flags |= HNAE3_VLAN_FLTR;
5624 else
5625 handle->netdev_flags &= ~HNAE3_VLAN_FLTR;
4541} 5626}
4542 5627
4543int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid, 5628static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid,
4544 bool is_kill, u16 vlan, u8 qos, __be16 proto) 5629 bool is_kill, u16 vlan, u8 qos,
5630 __be16 proto)
4545{ 5631{
4546#define HCLGE_MAX_VF_BYTES 16 5632#define HCLGE_MAX_VF_BYTES 16
4547 struct hclge_vlan_filter_vf_cfg_cmd *req0; 5633 struct hclge_vlan_filter_vf_cfg_cmd *req0;
@@ -4581,16 +5667,31 @@ int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid,
4581 } 5667 }
4582 5668
4583 if (!is_kill) { 5669 if (!is_kill) {
5670#define HCLGE_VF_VLAN_NO_ENTRY 2
4584 if (!req0->resp_code || req0->resp_code == 1) 5671 if (!req0->resp_code || req0->resp_code == 1)
4585 return 0; 5672 return 0;
4586 5673
5674 if (req0->resp_code == HCLGE_VF_VLAN_NO_ENTRY) {
5675 dev_warn(&hdev->pdev->dev,
5676 "vf vlan table is full, vf vlan filter is disabled\n");
5677 return 0;
5678 }
5679
4587 dev_err(&hdev->pdev->dev, 5680 dev_err(&hdev->pdev->dev,
4588 "Add vf vlan filter fail, ret =%d.\n", 5681 "Add vf vlan filter fail, ret =%d.\n",
4589 req0->resp_code); 5682 req0->resp_code);
4590 } else { 5683 } else {
5684#define HCLGE_VF_VLAN_DEL_NO_FOUND 1
4591 if (!req0->resp_code) 5685 if (!req0->resp_code)
4592 return 0; 5686 return 0;
4593 5687
5688 if (req0->resp_code == HCLGE_VF_VLAN_DEL_NO_FOUND) {
5689 dev_warn(&hdev->pdev->dev,
5690 "vlan %d filter is not in vf vlan table\n",
5691 vlan);
5692 return 0;
5693 }
5694
4594 dev_err(&hdev->pdev->dev, 5695 dev_err(&hdev->pdev->dev,
4595 "Kill vf vlan filter fail, ret =%d.\n", 5696 "Kill vf vlan filter fail, ret =%d.\n",
4596 req0->resp_code); 5697 req0->resp_code);
@@ -4599,12 +5700,9 @@ int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid,
4599 return -EIO; 5700 return -EIO;
4600} 5701}
4601 5702
4602static int hclge_set_port_vlan_filter(struct hnae3_handle *handle, 5703static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto,
4603 __be16 proto, u16 vlan_id, 5704 u16 vlan_id, bool is_kill)
4604 bool is_kill)
4605{ 5705{
4606 struct hclge_vport *vport = hclge_get_vport(handle);
4607 struct hclge_dev *hdev = vport->back;
4608 struct hclge_vlan_filter_pf_cfg_cmd *req; 5706 struct hclge_vlan_filter_pf_cfg_cmd *req;
4609 struct hclge_desc desc; 5707 struct hclge_desc desc;
4610 u8 vlan_offset_byte_val; 5708 u8 vlan_offset_byte_val;
@@ -4624,22 +5722,69 @@ static int hclge_set_port_vlan_filter(struct hnae3_handle *handle,
4624 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val; 5722 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
4625 5723
4626 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5724 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5725 if (ret)
5726 dev_err(&hdev->pdev->dev,
5727 "port vlan command, send fail, ret =%d.\n", ret);
5728 return ret;
5729}
5730
5731static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto,
5732 u16 vport_id, u16 vlan_id, u8 qos,
5733 bool is_kill)
5734{
5735 u16 vport_idx, vport_num = 0;
5736 int ret;
5737
5738 if (is_kill && !vlan_id)
5739 return 0;
5740
5741 ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id,
5742 0, proto);
4627 if (ret) { 5743 if (ret) {
4628 dev_err(&hdev->pdev->dev, 5744 dev_err(&hdev->pdev->dev,
4629 "port vlan command, send fail, ret =%d.\n", 5745 "Set %d vport vlan filter config fail, ret =%d.\n",
4630 ret); 5746 vport_id, ret);
4631 return ret; 5747 return ret;
4632 } 5748 }
4633 5749
4634 ret = hclge_set_vf_vlan_common(hdev, 0, is_kill, vlan_id, 0, proto); 5750 /* vlan 0 may be added twice when 8021q module is enabled */
4635 if (ret) { 5751 if (!is_kill && !vlan_id &&
5752 test_bit(vport_id, hdev->vlan_table[vlan_id]))
5753 return 0;
5754
5755 if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) {
4636 dev_err(&hdev->pdev->dev, 5756 dev_err(&hdev->pdev->dev,
4637 "Set pf vlan filter config fail, ret =%d.\n", 5757 "Add port vlan failed, vport %d is already in vlan %d\n",
4638 ret); 5758 vport_id, vlan_id);
4639 return -EIO; 5759 return -EINVAL;
4640 } 5760 }
4641 5761
4642 return 0; 5762 if (is_kill &&
5763 !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) {
5764 dev_err(&hdev->pdev->dev,
5765 "Delete port vlan failed, vport %d is not in vlan %d\n",
5766 vport_id, vlan_id);
5767 return -EINVAL;
5768 }
5769
5770 for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], HCLGE_VPORT_NUM)
5771 vport_num++;
5772
5773 if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1))
5774 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id,
5775 is_kill);
5776
5777 return ret;
5778}
5779
5780int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,
5781 u16 vlan_id, bool is_kill)
5782{
5783 struct hclge_vport *vport = hclge_get_vport(handle);
5784 struct hclge_dev *hdev = vport->back;
5785
5786 return hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, vlan_id,
5787 0, is_kill);
4643} 5788}
4644 5789
4645static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid, 5790static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
@@ -4653,7 +5798,7 @@ static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
4653 if (proto != htons(ETH_P_8021Q)) 5798 if (proto != htons(ETH_P_8021Q))
4654 return -EPROTONOSUPPORT; 5799 return -EPROTONOSUPPORT;
4655 5800
4656 return hclge_set_vf_vlan_common(hdev, vfid, false, vlan, qos, proto); 5801 return hclge_set_vlan_filter_hw(hdev, proto, vfid, vlan, qos, false);
4657} 5802}
4658 5803
4659static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport) 5804static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport)
@@ -4669,15 +5814,19 @@ static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport)
4669 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data; 5814 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data;
4670 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1); 5815 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1);
4671 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2); 5816 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2);
4672 hnae_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG_B, 5817 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B,
4673 vcfg->accept_tag ? 1 : 0); 5818 vcfg->accept_tag1 ? 1 : 0);
4674 hnae_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG_B, 5819 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B,
4675 vcfg->accept_untag ? 1 : 0); 5820 vcfg->accept_untag1 ? 1 : 0);
4676 hnae_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B, 5821 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B,
4677 vcfg->insert_tag1_en ? 1 : 0); 5822 vcfg->accept_tag2 ? 1 : 0);
4678 hnae_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B, 5823 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B,
4679 vcfg->insert_tag2_en ? 1 : 0); 5824 vcfg->accept_untag2 ? 1 : 0);
4680 hnae_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0); 5825 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B,
5826 vcfg->insert_tag1_en ? 1 : 0);
5827 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B,
5828 vcfg->insert_tag2_en ? 1 : 0);
5829 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0);
4681 5830
4682 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 5831 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
4683 req->vf_bitmap[req->vf_offset] = 5832 req->vf_bitmap[req->vf_offset] =
@@ -4703,14 +5852,14 @@ static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport)
4703 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false); 5852 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false);
4704 5853
4705 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data; 5854 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data;
4706 hnae_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B, 5855 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B,
4707 vcfg->strip_tag1_en ? 1 : 0); 5856 vcfg->strip_tag1_en ? 1 : 0);
4708 hnae_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B, 5857 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B,
4709 vcfg->strip_tag2_en ? 1 : 0); 5858 vcfg->strip_tag2_en ? 1 : 0);
4710 hnae_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B, 5859 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B,
4711 vcfg->vlan1_vlan_prionly ? 1 : 0); 5860 vcfg->vlan1_vlan_prionly ? 1 : 0);
4712 hnae_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B, 5861 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B,
4713 vcfg->vlan2_vlan_prionly ? 1 : 0); 5862 vcfg->vlan2_vlan_prionly ? 1 : 0);
4714 5863
4715 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 5864 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
4716 req->vf_bitmap[req->vf_offset] = 5865 req->vf_bitmap[req->vf_offset] =
@@ -4753,7 +5902,7 @@ static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev)
4753 5902
4754 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false); 5903 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false);
4755 5904
4756 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)&desc.data; 5905 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)desc.data;
4757 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type); 5906 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type);
4758 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type); 5907 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type);
4759 5908
@@ -4770,18 +5919,30 @@ static int hclge_init_vlan_config(struct hclge_dev *hdev)
4770{ 5919{
4771#define HCLGE_DEF_VLAN_TYPE 0x8100 5920#define HCLGE_DEF_VLAN_TYPE 0x8100
4772 5921
4773 struct hnae3_handle *handle; 5922 struct hnae3_handle *handle = &hdev->vport[0].nic;
4774 struct hclge_vport *vport; 5923 struct hclge_vport *vport;
4775 int ret; 5924 int ret;
4776 int i; 5925 int i;
4777 5926
4778 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, true); 5927 if (hdev->pdev->revision >= 0x21) {
4779 if (ret) 5928 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
4780 return ret; 5929 HCLGE_FILTER_FE_EGRESS, true);
5930 if (ret)
5931 return ret;
4781 5932
4782 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, true); 5933 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT,
4783 if (ret) 5934 HCLGE_FILTER_FE_INGRESS, true);
4784 return ret; 5935 if (ret)
5936 return ret;
5937 } else {
5938 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
5939 HCLGE_FILTER_FE_EGRESS_V1_B,
5940 true);
5941 if (ret)
5942 return ret;
5943 }
5944
5945 handle->netdev_flags |= HNAE3_VLAN_FLTR;
4785 5946
4786 hdev->vlan_type_cfg.rx_in_fst_vlan_type = HCLGE_DEF_VLAN_TYPE; 5947 hdev->vlan_type_cfg.rx_in_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
4787 hdev->vlan_type_cfg.rx_in_sec_vlan_type = HCLGE_DEF_VLAN_TYPE; 5948 hdev->vlan_type_cfg.rx_in_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
@@ -4796,8 +5957,18 @@ static int hclge_init_vlan_config(struct hclge_dev *hdev)
4796 5957
4797 for (i = 0; i < hdev->num_alloc_vport; i++) { 5958 for (i = 0; i < hdev->num_alloc_vport; i++) {
4798 vport = &hdev->vport[i]; 5959 vport = &hdev->vport[i];
4799 vport->txvlan_cfg.accept_tag = true; 5960 vport->txvlan_cfg.accept_tag1 = true;
4800 vport->txvlan_cfg.accept_untag = true; 5961 vport->txvlan_cfg.accept_untag1 = true;
5962
5963 /* accept_tag2 and accept_untag2 are not supported on
5964 * pdev revision(0x20), new revision support them. The
5965 * value of this two fields will not return error when driver
5966 * send command to fireware in revision(0x20).
5967 * This two fields can not configured by user.
5968 */
5969 vport->txvlan_cfg.accept_tag2 = true;
5970 vport->txvlan_cfg.accept_untag2 = true;
5971
4801 vport->txvlan_cfg.insert_tag1_en = false; 5972 vport->txvlan_cfg.insert_tag1_en = false;
4802 vport->txvlan_cfg.insert_tag2_en = false; 5973 vport->txvlan_cfg.insert_tag2_en = false;
4803 vport->txvlan_cfg.default_tag1 = 0; 5974 vport->txvlan_cfg.default_tag1 = 0;
@@ -4817,11 +5988,10 @@ static int hclge_init_vlan_config(struct hclge_dev *hdev)
4817 return ret; 5988 return ret;
4818 } 5989 }
4819 5990
4820 handle = &hdev->vport[0].nic; 5991 return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false);
4821 return hclge_set_port_vlan_filter(handle, htons(ETH_P_8021Q), 0, false);
4822} 5992}
4823 5993
4824static int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 5994int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
4825{ 5995{
4826 struct hclge_vport *vport = hclge_get_vport(handle); 5996 struct hclge_vport *vport = hclge_get_vport(handle);
4827 5997
@@ -4852,16 +6022,15 @@ static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mtu)
4852 6022
4853 req = (struct hclge_config_max_frm_size_cmd *)desc.data; 6023 req = (struct hclge_config_max_frm_size_cmd *)desc.data;
4854 req->max_frm_size = cpu_to_le16(max_frm_size); 6024 req->max_frm_size = cpu_to_le16(max_frm_size);
6025 req->min_frm_size = HCLGE_MAC_MIN_FRAME;
4855 6026
4856 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 6027 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4857 if (ret) { 6028 if (ret)
4858 dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret); 6029 dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret);
4859 return ret; 6030 else
4860 } 6031 hdev->mps = max_frm_size;
4861
4862 hdev->mps = max_frm_size;
4863 6032
4864 return 0; 6033 return ret;
4865} 6034}
4866 6035
4867static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu) 6036static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)
@@ -4896,7 +6065,7 @@ static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id,
4896 6065
4897 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 6066 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
4898 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK); 6067 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
4899 hnae_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable); 6068 hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable);
4900 6069
4901 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 6070 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4902 if (ret) { 6071 if (ret) {
@@ -4926,7 +6095,7 @@ static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id)
4926 return ret; 6095 return ret;
4927 } 6096 }
4928 6097
4929 return hnae_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B); 6098 return hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
4930} 6099}
4931 6100
4932static u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, 6101static u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle,
@@ -4941,31 +6110,28 @@ static u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle,
4941 return tqp->index; 6110 return tqp->index;
4942} 6111}
4943 6112
4944void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 6113int hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
4945{ 6114{
4946 struct hclge_vport *vport = hclge_get_vport(handle); 6115 struct hclge_vport *vport = hclge_get_vport(handle);
4947 struct hclge_dev *hdev = vport->back; 6116 struct hclge_dev *hdev = vport->back;
4948 int reset_try_times = 0; 6117 int reset_try_times = 0;
4949 int reset_status; 6118 int reset_status;
4950 u16 queue_gid; 6119 u16 queue_gid;
4951 int ret; 6120 int ret = 0;
4952
4953 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
4954 return;
4955 6121
4956 queue_gid = hclge_covert_handle_qid_global(handle, queue_id); 6122 queue_gid = hclge_covert_handle_qid_global(handle, queue_id);
4957 6123
4958 ret = hclge_tqp_enable(hdev, queue_id, 0, false); 6124 ret = hclge_tqp_enable(hdev, queue_id, 0, false);
4959 if (ret) { 6125 if (ret) {
4960 dev_warn(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret); 6126 dev_err(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret);
4961 return; 6127 return ret;
4962 } 6128 }
4963 6129
4964 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true); 6130 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true);
4965 if (ret) { 6131 if (ret) {
4966 dev_warn(&hdev->pdev->dev, 6132 dev_err(&hdev->pdev->dev,
4967 "Send reset tqp cmd fail, ret = %d\n", ret); 6133 "Send reset tqp cmd fail, ret = %d\n", ret);
4968 return; 6134 return ret;
4969 } 6135 }
4970 6136
4971 reset_try_times = 0; 6137 reset_try_times = 0;
@@ -4978,16 +6144,16 @@ void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
4978 } 6144 }
4979 6145
4980 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) { 6146 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
4981 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n"); 6147 dev_err(&hdev->pdev->dev, "Reset TQP fail\n");
4982 return; 6148 return ret;
4983 } 6149 }
4984 6150
4985 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false); 6151 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false);
4986 if (ret) { 6152 if (ret)
4987 dev_warn(&hdev->pdev->dev, 6153 dev_err(&hdev->pdev->dev,
4988 "Deassert the soft reset fail, ret = %d\n", ret); 6154 "Deassert the soft reset fail, ret = %d\n", ret);
4989 return; 6155
4990 } 6156 return ret;
4991} 6157}
4992 6158
4993void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id) 6159void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id)
@@ -5035,20 +6201,6 @@ static u32 hclge_get_fw_version(struct hnae3_handle *handle)
5035 return hdev->fw_version; 6201 return hdev->fw_version;
5036} 6202}
5037 6203
5038static void hclge_get_flowctrl_adv(struct hnae3_handle *handle,
5039 u32 *flowctrl_adv)
5040{
5041 struct hclge_vport *vport = hclge_get_vport(handle);
5042 struct hclge_dev *hdev = vport->back;
5043 struct phy_device *phydev = hdev->hw.mac.phydev;
5044
5045 if (!phydev)
5046 return;
5047
5048 *flowctrl_adv |= (phydev->advertising & ADVERTISED_Pause) |
5049 (phydev->advertising & ADVERTISED_Asym_Pause);
5050}
5051
5052static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 6204static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
5053{ 6205{
5054 struct phy_device *phydev = hdev->hw.mac.phydev; 6206 struct phy_device *phydev = hdev->hw.mac.phydev;
@@ -5056,13 +6208,7 @@ static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
5056 if (!phydev) 6208 if (!phydev)
5057 return; 6209 return;
5058 6210
5059 phydev->advertising &= ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause); 6211 phy_set_asym_pause(phydev, rx_en, tx_en);
5060
5061 if (rx_en)
5062 phydev->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
5063
5064 if (tx_en)
5065 phydev->advertising ^= ADVERTISED_Asym_Pause;
5066} 6212}
5067 6213
5068static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 6214static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
@@ -5104,11 +6250,7 @@ int hclge_cfg_flowctrl(struct hclge_dev *hdev)
5104 if (!phydev->link || !phydev->autoneg) 6250 if (!phydev->link || !phydev->autoneg)
5105 return 0; 6251 return 0;
5106 6252
5107 if (phydev->advertising & ADVERTISED_Pause) 6253 local_advertising = ethtool_adv_to_lcl_adv_t(phydev->advertising);
5108 local_advertising = ADVERTISE_PAUSE_CAP;
5109
5110 if (phydev->advertising & ADVERTISED_Asym_Pause)
5111 local_advertising |= ADVERTISE_PAUSE_ASYM;
5112 6254
5113 if (phydev->pause) 6255 if (phydev->pause)
5114 remote_advertising = LPA_PAUSE_CAP; 6256 remote_advertising = LPA_PAUSE_CAP;
@@ -5166,12 +6308,6 @@ static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg,
5166 struct phy_device *phydev = hdev->hw.mac.phydev; 6308 struct phy_device *phydev = hdev->hw.mac.phydev;
5167 u32 fc_autoneg; 6309 u32 fc_autoneg;
5168 6310
5169 /* Only support flow control negotiation for netdev with
5170 * phy attached for now.
5171 */
5172 if (!phydev)
5173 return -EOPNOTSUPP;
5174
5175 fc_autoneg = hclge_get_autoneg(handle); 6311 fc_autoneg = hclge_get_autoneg(handle);
5176 if (auto_neg != fc_autoneg) { 6312 if (auto_neg != fc_autoneg) {
5177 dev_info(&hdev->pdev->dev, 6313 dev_info(&hdev->pdev->dev,
@@ -5190,6 +6326,12 @@ static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg,
5190 if (!fc_autoneg) 6326 if (!fc_autoneg)
5191 return hclge_cfg_pauseparam(hdev, rx_en, tx_en); 6327 return hclge_cfg_pauseparam(hdev, rx_en, tx_en);
5192 6328
6329 /* Only support flow control negotiation for netdev with
6330 * phy attached for now.
6331 */
6332 if (!phydev)
6333 return -EOPNOTSUPP;
6334
5193 return phy_start_aneg(phydev); 6335 return phy_start_aneg(phydev);
5194} 6336}
5195 6337
@@ -5233,12 +6375,12 @@ static void hclge_get_mdix_mode(struct hnae3_handle *handle,
5233 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX); 6375 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX);
5234 6376
5235 retval = phy_read(phydev, HCLGE_PHY_CSC_REG); 6377 retval = phy_read(phydev, HCLGE_PHY_CSC_REG);
5236 mdix_ctrl = hnae_get_field(retval, HCLGE_PHY_MDIX_CTRL_M, 6378 mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M,
5237 HCLGE_PHY_MDIX_CTRL_S); 6379 HCLGE_PHY_MDIX_CTRL_S);
5238 6380
5239 retval = phy_read(phydev, HCLGE_PHY_CSS_REG); 6381 retval = phy_read(phydev, HCLGE_PHY_CSS_REG);
5240 mdix = hnae_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B); 6382 mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B);
5241 is_resolved = hnae_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B); 6383 is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B);
5242 6384
5243 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER); 6385 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER);
5244 6386
@@ -5265,6 +6407,16 @@ static void hclge_get_mdix_mode(struct hnae3_handle *handle,
5265 *tp_mdix = ETH_TP_MDI; 6407 *tp_mdix = ETH_TP_MDI;
5266} 6408}
5267 6409
6410static int hclge_init_instance_hw(struct hclge_dev *hdev)
6411{
6412 return hclge_mac_connect_phy(hdev);
6413}
6414
6415static void hclge_uninit_instance_hw(struct hclge_dev *hdev)
6416{
6417 hclge_mac_disconnect_phy(hdev);
6418}
6419
5268static int hclge_init_client_instance(struct hnae3_client *client, 6420static int hclge_init_client_instance(struct hnae3_client *client,
5269 struct hnae3_ae_dev *ae_dev) 6421 struct hnae3_ae_dev *ae_dev)
5270{ 6422{
@@ -5282,7 +6434,16 @@ static int hclge_init_client_instance(struct hnae3_client *client,
5282 vport->nic.client = client; 6434 vport->nic.client = client;
5283 ret = client->ops->init_instance(&vport->nic); 6435 ret = client->ops->init_instance(&vport->nic);
5284 if (ret) 6436 if (ret)
5285 goto err; 6437 goto clear_nic;
6438
6439 ret = hclge_init_instance_hw(hdev);
6440 if (ret) {
6441 client->ops->uninit_instance(&vport->nic,
6442 0);
6443 goto clear_nic;
6444 }
6445
6446 hnae3_set_client_init_flag(client, ae_dev, 1);
5286 6447
5287 if (hdev->roce_client && 6448 if (hdev->roce_client &&
5288 hnae3_dev_roce_supported(hdev)) { 6449 hnae3_dev_roce_supported(hdev)) {
@@ -5290,11 +6451,14 @@ static int hclge_init_client_instance(struct hnae3_client *client,
5290 6451
5291 ret = hclge_init_roce_base_info(vport); 6452 ret = hclge_init_roce_base_info(vport);
5292 if (ret) 6453 if (ret)
5293 goto err; 6454 goto clear_roce;
5294 6455
5295 ret = rc->ops->init_instance(&vport->roce); 6456 ret = rc->ops->init_instance(&vport->roce);
5296 if (ret) 6457 if (ret)
5297 goto err; 6458 goto clear_roce;
6459
6460 hnae3_set_client_init_flag(hdev->roce_client,
6461 ae_dev, 1);
5298 } 6462 }
5299 6463
5300 break; 6464 break;
@@ -5304,7 +6468,9 @@ static int hclge_init_client_instance(struct hnae3_client *client,
5304 6468
5305 ret = client->ops->init_instance(&vport->nic); 6469 ret = client->ops->init_instance(&vport->nic);
5306 if (ret) 6470 if (ret)
5307 goto err; 6471 goto clear_nic;
6472
6473 hnae3_set_client_init_flag(client, ae_dev, 1);
5308 6474
5309 break; 6475 break;
5310 case HNAE3_CLIENT_ROCE: 6476 case HNAE3_CLIENT_ROCE:
@@ -5316,17 +6482,30 @@ static int hclge_init_client_instance(struct hnae3_client *client,
5316 if (hdev->roce_client && hdev->nic_client) { 6482 if (hdev->roce_client && hdev->nic_client) {
5317 ret = hclge_init_roce_base_info(vport); 6483 ret = hclge_init_roce_base_info(vport);
5318 if (ret) 6484 if (ret)
5319 goto err; 6485 goto clear_roce;
5320 6486
5321 ret = client->ops->init_instance(&vport->roce); 6487 ret = client->ops->init_instance(&vport->roce);
5322 if (ret) 6488 if (ret)
5323 goto err; 6489 goto clear_roce;
6490
6491 hnae3_set_client_init_flag(client, ae_dev, 1);
5324 } 6492 }
6493
6494 break;
6495 default:
6496 return -EINVAL;
5325 } 6497 }
5326 } 6498 }
5327 6499
5328 return 0; 6500 return 0;
5329err: 6501
6502clear_nic:
6503 hdev->nic_client = NULL;
6504 vport->nic.client = NULL;
6505 return ret;
6506clear_roce:
6507 hdev->roce_client = NULL;
6508 vport->roce.client = NULL;
5330 return ret; 6509 return ret;
5331} 6510}
5332 6511
@@ -5347,7 +6526,8 @@ static void hclge_uninit_client_instance(struct hnae3_client *client,
5347 } 6526 }
5348 if (client->type == HNAE3_CLIENT_ROCE) 6527 if (client->type == HNAE3_CLIENT_ROCE)
5349 return; 6528 return;
5350 if (client->ops->uninit_instance) { 6529 if (hdev->nic_client && client->ops->uninit_instance) {
6530 hclge_uninit_instance_hw(hdev);
5351 client->ops->uninit_instance(&vport->nic, 0); 6531 client->ops->uninit_instance(&vport->nic, 0);
5352 hdev->nic_client = NULL; 6532 hdev->nic_client = NULL;
5353 vport->nic.client = NULL; 6533 vport->nic.client = NULL;
@@ -5364,7 +6544,7 @@ static int hclge_pci_init(struct hclge_dev *hdev)
5364 ret = pci_enable_device(pdev); 6544 ret = pci_enable_device(pdev);
5365 if (ret) { 6545 if (ret) {
5366 dev_err(&pdev->dev, "failed to enable PCI device\n"); 6546 dev_err(&pdev->dev, "failed to enable PCI device\n");
5367 goto err_no_drvdata; 6547 return ret;
5368 } 6548 }
5369 6549
5370 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 6550 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
@@ -5386,7 +6566,6 @@ static int hclge_pci_init(struct hclge_dev *hdev)
5386 6566
5387 pci_set_master(pdev); 6567 pci_set_master(pdev);
5388 hw = &hdev->hw; 6568 hw = &hdev->hw;
5389 hw->back = hdev;
5390 hw->io_base = pcim_iomap(pdev, 2, 0); 6569 hw->io_base = pcim_iomap(pdev, 2, 0);
5391 if (!hw->io_base) { 6570 if (!hw->io_base) {
5392 dev_err(&pdev->dev, "Can't map configuration register space\n"); 6571 dev_err(&pdev->dev, "Can't map configuration register space\n");
@@ -5402,8 +6581,6 @@ err_clr_master:
5402 pci_release_regions(pdev); 6581 pci_release_regions(pdev);
5403err_disable_device: 6582err_disable_device:
5404 pci_disable_device(pdev); 6583 pci_disable_device(pdev);
5405err_no_drvdata:
5406 pci_set_drvdata(pdev, NULL);
5407 6584
5408 return ret; 6585 return ret;
5409} 6586}
@@ -5412,12 +6589,37 @@ static void hclge_pci_uninit(struct hclge_dev *hdev)
5412{ 6589{
5413 struct pci_dev *pdev = hdev->pdev; 6590 struct pci_dev *pdev = hdev->pdev;
5414 6591
6592 pcim_iounmap(pdev, hdev->hw.io_base);
5415 pci_free_irq_vectors(pdev); 6593 pci_free_irq_vectors(pdev);
5416 pci_clear_master(pdev); 6594 pci_clear_master(pdev);
5417 pci_release_mem_regions(pdev); 6595 pci_release_mem_regions(pdev);
5418 pci_disable_device(pdev); 6596 pci_disable_device(pdev);
5419} 6597}
5420 6598
6599static void hclge_state_init(struct hclge_dev *hdev)
6600{
6601 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state);
6602 set_bit(HCLGE_STATE_DOWN, &hdev->state);
6603 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
6604 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
6605 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
6606 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
6607}
6608
6609static void hclge_state_uninit(struct hclge_dev *hdev)
6610{
6611 set_bit(HCLGE_STATE_DOWN, &hdev->state);
6612
6613 if (hdev->service_timer.function)
6614 del_timer_sync(&hdev->service_timer);
6615 if (hdev->service_task.func)
6616 cancel_work_sync(&hdev->service_task);
6617 if (hdev->rst_service_task.func)
6618 cancel_work_sync(&hdev->rst_service_task);
6619 if (hdev->mbx_service_task.func)
6620 cancel_work_sync(&hdev->mbx_service_task);
6621}
6622
5421static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev) 6623static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
5422{ 6624{
5423 struct pci_dev *pdev = ae_dev->pdev; 6625 struct pci_dev *pdev = ae_dev->pdev;
@@ -5427,51 +6629,49 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
5427 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 6629 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
5428 if (!hdev) { 6630 if (!hdev) {
5429 ret = -ENOMEM; 6631 ret = -ENOMEM;
5430 goto err_hclge_dev; 6632 goto out;
5431 } 6633 }
5432 6634
5433 hdev->pdev = pdev; 6635 hdev->pdev = pdev;
5434 hdev->ae_dev = ae_dev; 6636 hdev->ae_dev = ae_dev;
5435 hdev->reset_type = HNAE3_NONE_RESET; 6637 hdev->reset_type = HNAE3_NONE_RESET;
5436 hdev->reset_request = 0;
5437 hdev->reset_pending = 0;
5438 ae_dev->priv = hdev; 6638 ae_dev->priv = hdev;
5439 6639
5440 ret = hclge_pci_init(hdev); 6640 ret = hclge_pci_init(hdev);
5441 if (ret) { 6641 if (ret) {
5442 dev_err(&pdev->dev, "PCI init failed\n"); 6642 dev_err(&pdev->dev, "PCI init failed\n");
5443 goto err_pci_init; 6643 goto out;
5444 } 6644 }
5445 6645
5446 /* Firmware command queue initialize */ 6646 /* Firmware command queue initialize */
5447 ret = hclge_cmd_queue_init(hdev); 6647 ret = hclge_cmd_queue_init(hdev);
5448 if (ret) { 6648 if (ret) {
5449 dev_err(&pdev->dev, "Cmd queue init failed, ret = %d.\n", ret); 6649 dev_err(&pdev->dev, "Cmd queue init failed, ret = %d.\n", ret);
5450 return ret; 6650 goto err_pci_uninit;
5451 } 6651 }
5452 6652
5453 /* Firmware command initialize */ 6653 /* Firmware command initialize */
5454 ret = hclge_cmd_init(hdev); 6654 ret = hclge_cmd_init(hdev);
5455 if (ret) 6655 if (ret)
5456 goto err_cmd_init; 6656 goto err_cmd_uninit;
5457 6657
5458 ret = hclge_get_cap(hdev); 6658 ret = hclge_get_cap(hdev);
5459 if (ret) { 6659 if (ret) {
5460 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n", 6660 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
5461 ret); 6661 ret);
5462 return ret; 6662 goto err_cmd_uninit;
5463 } 6663 }
5464 6664
5465 ret = hclge_configure(hdev); 6665 ret = hclge_configure(hdev);
5466 if (ret) { 6666 if (ret) {
5467 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret); 6667 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
5468 return ret; 6668 goto err_cmd_uninit;
5469 } 6669 }
5470 6670
5471 ret = hclge_init_msi(hdev); 6671 ret = hclge_init_msi(hdev);
5472 if (ret) { 6672 if (ret) {
5473 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret); 6673 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret);
5474 return ret; 6674 goto err_cmd_uninit;
5475 } 6675 }
5476 6676
5477 ret = hclge_misc_irq_init(hdev); 6677 ret = hclge_misc_irq_init(hdev);
@@ -5479,69 +6679,91 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
5479 dev_err(&pdev->dev, 6679 dev_err(&pdev->dev,
5480 "Misc IRQ(vector0) init error, ret = %d.\n", 6680 "Misc IRQ(vector0) init error, ret = %d.\n",
5481 ret); 6681 ret);
5482 return ret; 6682 goto err_msi_uninit;
5483 } 6683 }
5484 6684
5485 ret = hclge_alloc_tqps(hdev); 6685 ret = hclge_alloc_tqps(hdev);
5486 if (ret) { 6686 if (ret) {
5487 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret); 6687 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret);
5488 return ret; 6688 goto err_msi_irq_uninit;
5489 } 6689 }
5490 6690
5491 ret = hclge_alloc_vport(hdev); 6691 ret = hclge_alloc_vport(hdev);
5492 if (ret) { 6692 if (ret) {
5493 dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret); 6693 dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret);
5494 return ret; 6694 goto err_msi_irq_uninit;
5495 } 6695 }
5496 6696
5497 ret = hclge_map_tqp(hdev); 6697 ret = hclge_map_tqp(hdev);
5498 if (ret) { 6698 if (ret) {
5499 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret); 6699 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
5500 return ret; 6700 goto err_msi_irq_uninit;
5501 } 6701 }
5502 6702
5503 ret = hclge_mac_mdio_config(hdev); 6703 if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) {
6704 ret = hclge_mac_mdio_config(hdev);
6705 if (ret) {
6706 dev_err(&hdev->pdev->dev,
6707 "mdio config fail ret=%d\n", ret);
6708 goto err_msi_irq_uninit;
6709 }
6710 }
6711
6712 ret = hclge_init_umv_space(hdev);
5504 if (ret) { 6713 if (ret) {
5505 dev_warn(&hdev->pdev->dev, 6714 dev_err(&pdev->dev, "umv space init error, ret=%d.\n", ret);
5506 "mdio config fail ret=%d\n", ret); 6715 goto err_msi_irq_uninit;
5507 return ret;
5508 } 6716 }
5509 6717
5510 ret = hclge_mac_init(hdev); 6718 ret = hclge_mac_init(hdev);
5511 if (ret) { 6719 if (ret) {
5512 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 6720 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
5513 return ret; 6721 goto err_mdiobus_unreg;
5514 } 6722 }
5515 6723
5516 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 6724 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
5517 if (ret) { 6725 if (ret) {
5518 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 6726 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
5519 return ret; 6727 goto err_mdiobus_unreg;
5520 } 6728 }
5521 6729
5522 ret = hclge_init_vlan_config(hdev); 6730 ret = hclge_init_vlan_config(hdev);
5523 if (ret) { 6731 if (ret) {
5524 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 6732 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
5525 return ret; 6733 goto err_mdiobus_unreg;
5526 } 6734 }
5527 6735
5528 ret = hclge_tm_schd_init(hdev); 6736 ret = hclge_tm_schd_init(hdev);
5529 if (ret) { 6737 if (ret) {
5530 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret); 6738 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
5531 return ret; 6739 goto err_mdiobus_unreg;
5532 } 6740 }
5533 6741
5534 hclge_rss_init_cfg(hdev); 6742 hclge_rss_init_cfg(hdev);
5535 ret = hclge_rss_init_hw(hdev); 6743 ret = hclge_rss_init_hw(hdev);
5536 if (ret) { 6744 if (ret) {
5537 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 6745 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
5538 return ret; 6746 goto err_mdiobus_unreg;
5539 } 6747 }
5540 6748
5541 ret = init_mgr_tbl(hdev); 6749 ret = init_mgr_tbl(hdev);
5542 if (ret) { 6750 if (ret) {
5543 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret); 6751 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret);
5544 return ret; 6752 goto err_mdiobus_unreg;
6753 }
6754
6755 ret = hclge_init_fd_config(hdev);
6756 if (ret) {
6757 dev_err(&pdev->dev,
6758 "fd table init fail, ret=%d\n", ret);
6759 goto err_mdiobus_unreg;
6760 }
6761
6762 ret = hclge_hw_error_set_state(hdev, true);
6763 if (ret) {
6764 dev_err(&pdev->dev,
6765 "hw error interrupts enable failed, ret =%d\n", ret);
6766 goto err_mdiobus_unreg;
5545 } 6767 }
5546 6768
5547 hclge_dcb_ops_set(hdev); 6769 hclge_dcb_ops_set(hdev);
@@ -5551,24 +6773,31 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
5551 INIT_WORK(&hdev->rst_service_task, hclge_reset_service_task); 6773 INIT_WORK(&hdev->rst_service_task, hclge_reset_service_task);
5552 INIT_WORK(&hdev->mbx_service_task, hclge_mailbox_service_task); 6774 INIT_WORK(&hdev->mbx_service_task, hclge_mailbox_service_task);
5553 6775
6776 hclge_clear_all_event_cause(hdev);
6777
5554 /* Enable MISC vector(vector0) */ 6778 /* Enable MISC vector(vector0) */
5555 hclge_enable_vector(&hdev->misc_vector, true); 6779 hclge_enable_vector(&hdev->misc_vector, true);
5556 6780
5557 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state); 6781 hclge_state_init(hdev);
5558 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5559 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
5560 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
5561 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
5562 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
5563 6782
5564 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME); 6783 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME);
5565 return 0; 6784 return 0;
5566 6785
5567err_cmd_init: 6786err_mdiobus_unreg:
6787 if (hdev->hw.mac.phydev)
6788 mdiobus_unregister(hdev->hw.mac.mdio_bus);
6789err_msi_irq_uninit:
6790 hclge_misc_irq_uninit(hdev);
6791err_msi_uninit:
6792 pci_free_irq_vectors(pdev);
6793err_cmd_uninit:
6794 hclge_destroy_cmd_queue(&hdev->hw);
6795err_pci_uninit:
6796 pcim_iounmap(pdev, hdev->hw.io_base);
6797 pci_clear_master(pdev);
5568 pci_release_regions(pdev); 6798 pci_release_regions(pdev);
5569err_pci_init: 6799 pci_disable_device(pdev);
5570 pci_set_drvdata(pdev, NULL); 6800out:
5571err_hclge_dev:
5572 return ret; 6801 return ret;
5573} 6802}
5574 6803
@@ -5586,6 +6815,7 @@ static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
5586 set_bit(HCLGE_STATE_DOWN, &hdev->state); 6815 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5587 6816
5588 hclge_stats_clear(hdev); 6817 hclge_stats_clear(hdev);
6818 memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table));
5589 6819
5590 ret = hclge_cmd_init(hdev); 6820 ret = hclge_cmd_init(hdev);
5591 if (ret) { 6821 if (ret) {
@@ -5612,6 +6842,8 @@ static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
5612 return ret; 6842 return ret;
5613 } 6843 }
5614 6844
6845 hclge_reset_umv_space(hdev);
6846
5615 ret = hclge_mac_init(hdev); 6847 ret = hclge_mac_init(hdev);
5616 if (ret) { 6848 if (ret) {
5617 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 6849 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
@@ -5642,8 +6874,18 @@ static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
5642 return ret; 6874 return ret;
5643 } 6875 }
5644 6876
5645 /* Enable MISC vector(vector0) */ 6877 ret = hclge_init_fd_config(hdev);
5646 hclge_enable_vector(&hdev->misc_vector, true); 6878 if (ret) {
6879 dev_err(&pdev->dev,
6880 "fd table init fail, ret=%d\n", ret);
6881 return ret;
6882 }
6883
6884 /* Re-enable the TM hw error interrupts because
6885 * they get disabled on core/global reset.
6886 */
6887 if (hclge_enable_tm_hw_error(hdev, true))
6888 dev_err(&pdev->dev, "failed to enable TM hw error interrupts\n");
5647 6889
5648 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n", 6890 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n",
5649 HCLGE_DRIVER_NAME); 6891 HCLGE_DRIVER_NAME);
@@ -5656,25 +6898,18 @@ static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
5656 struct hclge_dev *hdev = ae_dev->priv; 6898 struct hclge_dev *hdev = ae_dev->priv;
5657 struct hclge_mac *mac = &hdev->hw.mac; 6899 struct hclge_mac *mac = &hdev->hw.mac;
5658 6900
5659 set_bit(HCLGE_STATE_DOWN, &hdev->state); 6901 hclge_state_uninit(hdev);
5660
5661 if (IS_ENABLED(CONFIG_PCI_IOV))
5662 hclge_disable_sriov(hdev);
5663
5664 if (hdev->service_timer.function)
5665 del_timer_sync(&hdev->service_timer);
5666 if (hdev->service_task.func)
5667 cancel_work_sync(&hdev->service_task);
5668 if (hdev->rst_service_task.func)
5669 cancel_work_sync(&hdev->rst_service_task);
5670 if (hdev->mbx_service_task.func)
5671 cancel_work_sync(&hdev->mbx_service_task);
5672 6902
5673 if (mac->phydev) 6903 if (mac->phydev)
5674 mdiobus_unregister(mac->mdio_bus); 6904 mdiobus_unregister(mac->mdio_bus);
5675 6905
6906 hclge_uninit_umv_space(hdev);
6907
5676 /* Disable MISC vector(vector0) */ 6908 /* Disable MISC vector(vector0) */
5677 hclge_enable_vector(&hdev->misc_vector, false); 6909 hclge_enable_vector(&hdev->misc_vector, false);
6910 synchronize_irq(hdev->misc_vector.vector_irq);
6911
6912 hclge_hw_error_set_state(hdev, false);
5678 hclge_destroy_cmd_queue(&hdev->hw); 6913 hclge_destroy_cmd_queue(&hdev->hw);
5679 hclge_misc_irq_uninit(hdev); 6914 hclge_misc_irq_uninit(hdev);
5680 hclge_pci_uninit(hdev); 6915 hclge_pci_uninit(hdev);
@@ -5702,18 +6937,12 @@ static void hclge_get_channels(struct hnae3_handle *handle,
5702} 6937}
5703 6938
5704static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle, 6939static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle,
5705 u16 *free_tqps, u16 *max_rss_size) 6940 u16 *alloc_tqps, u16 *max_rss_size)
5706{ 6941{
5707 struct hclge_vport *vport = hclge_get_vport(handle); 6942 struct hclge_vport *vport = hclge_get_vport(handle);
5708 struct hclge_dev *hdev = vport->back; 6943 struct hclge_dev *hdev = vport->back;
5709 u16 temp_tqps = 0;
5710 int i;
5711 6944
5712 for (i = 0; i < hdev->num_tqps; i++) { 6945 *alloc_tqps = vport->alloc_tqps;
5713 if (!hdev->htqp[i].alloced)
5714 temp_tqps++;
5715 }
5716 *free_tqps = temp_tqps;
5717 *max_rss_size = hdev->rss_size_max; 6946 *max_rss_size = hdev->rss_size_max;
5718} 6947}
5719 6948
@@ -5750,9 +6979,10 @@ static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num)
5750 u32 *rss_indir; 6979 u32 *rss_indir;
5751 int ret, i; 6980 int ret, i;
5752 6981
6982 /* Free old tqps, and reallocate with new tqp number when nic setup */
5753 hclge_release_tqp(vport); 6983 hclge_release_tqp(vport);
5754 6984
5755 ret = hclge_knic_setup(vport, new_tqps_num); 6985 ret = hclge_knic_setup(vport, new_tqps_num, kinfo->num_desc);
5756 if (ret) { 6986 if (ret) {
5757 dev_err(&hdev->pdev->dev, "setup nic fail, ret =%d\n", ret); 6987 dev_err(&hdev->pdev->dev, "setup nic fail, ret =%d\n", ret);
5758 return ret; 6988 return ret;
@@ -5985,9 +7215,7 @@ static void hclge_get_regs(struct hnae3_handle *handle, u32 *version,
5985 "Get 64 bit register failed, ret = %d.\n", ret); 7215 "Get 64 bit register failed, ret = %d.\n", ret);
5986} 7216}
5987 7217
5988static int hclge_set_led_status_sfp(struct hclge_dev *hdev, u8 speed_led_status, 7218static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status)
5989 u8 act_led_status, u8 link_led_status,
5990 u8 locate_led_status)
5991{ 7219{
5992 struct hclge_set_led_state_cmd *req; 7220 struct hclge_set_led_state_cmd *req;
5993 struct hclge_desc desc; 7221 struct hclge_desc desc;
@@ -5996,14 +7224,8 @@ static int hclge_set_led_status_sfp(struct hclge_dev *hdev, u8 speed_led_status,
5996 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false); 7224 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false);
5997 7225
5998 req = (struct hclge_set_led_state_cmd *)desc.data; 7226 req = (struct hclge_set_led_state_cmd *)desc.data;
5999 hnae_set_field(req->port_speed_led_config, HCLGE_LED_PORT_SPEED_STATE_M, 7227 hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M,
6000 HCLGE_LED_PORT_SPEED_STATE_S, speed_led_status); 7228 HCLGE_LED_LOCATE_STATE_S, locate_led_status);
6001 hnae_set_field(req->link_led_config, HCLGE_LED_ACTIVITY_STATE_M,
6002 HCLGE_LED_ACTIVITY_STATE_S, act_led_status);
6003 hnae_set_field(req->activity_led_config, HCLGE_LED_LINK_STATE_M,
6004 HCLGE_LED_LINK_STATE_S, link_led_status);
6005 hnae_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M,
6006 HCLGE_LED_LOCATE_STATE_S, locate_led_status);
6007 7229
6008 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7230 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6009 if (ret) 7231 if (ret)
@@ -6022,105 +7244,17 @@ enum hclge_led_status {
6022static int hclge_set_led_id(struct hnae3_handle *handle, 7244static int hclge_set_led_id(struct hnae3_handle *handle,
6023 enum ethtool_phys_id_state status) 7245 enum ethtool_phys_id_state status)
6024{ 7246{
6025#define BLINK_FREQUENCY 2
6026 struct hclge_vport *vport = hclge_get_vport(handle); 7247 struct hclge_vport *vport = hclge_get_vport(handle);
6027 struct hclge_dev *hdev = vport->back; 7248 struct hclge_dev *hdev = vport->back;
6028 struct phy_device *phydev = hdev->hw.mac.phydev;
6029 int ret = 0;
6030
6031 if (phydev || hdev->hw.mac.media_type != HNAE3_MEDIA_TYPE_FIBER)
6032 return -EOPNOTSUPP;
6033 7249
6034 switch (status) { 7250 switch (status) {
6035 case ETHTOOL_ID_ACTIVE: 7251 case ETHTOOL_ID_ACTIVE:
6036 ret = hclge_set_led_status_sfp(hdev, 7252 return hclge_set_led_status(hdev, HCLGE_LED_ON);
6037 HCLGE_LED_NO_CHANGE,
6038 HCLGE_LED_NO_CHANGE,
6039 HCLGE_LED_NO_CHANGE,
6040 HCLGE_LED_ON);
6041 break;
6042 case ETHTOOL_ID_INACTIVE: 7253 case ETHTOOL_ID_INACTIVE:
6043 ret = hclge_set_led_status_sfp(hdev, 7254 return hclge_set_led_status(hdev, HCLGE_LED_OFF);
6044 HCLGE_LED_NO_CHANGE,
6045 HCLGE_LED_NO_CHANGE,
6046 HCLGE_LED_NO_CHANGE,
6047 HCLGE_LED_OFF);
6048 break;
6049 default:
6050 ret = -EINVAL;
6051 break;
6052 }
6053
6054 return ret;
6055}
6056
6057enum hclge_led_port_speed {
6058 HCLGE_SPEED_LED_FOR_1G,
6059 HCLGE_SPEED_LED_FOR_10G,
6060 HCLGE_SPEED_LED_FOR_25G,
6061 HCLGE_SPEED_LED_FOR_40G,
6062 HCLGE_SPEED_LED_FOR_50G,
6063 HCLGE_SPEED_LED_FOR_100G,
6064};
6065
6066static u8 hclge_led_get_speed_status(u32 speed)
6067{
6068 u8 speed_led;
6069
6070 switch (speed) {
6071 case HCLGE_MAC_SPEED_1G:
6072 speed_led = HCLGE_SPEED_LED_FOR_1G;
6073 break;
6074 case HCLGE_MAC_SPEED_10G:
6075 speed_led = HCLGE_SPEED_LED_FOR_10G;
6076 break;
6077 case HCLGE_MAC_SPEED_25G:
6078 speed_led = HCLGE_SPEED_LED_FOR_25G;
6079 break;
6080 case HCLGE_MAC_SPEED_40G:
6081 speed_led = HCLGE_SPEED_LED_FOR_40G;
6082 break;
6083 case HCLGE_MAC_SPEED_50G:
6084 speed_led = HCLGE_SPEED_LED_FOR_50G;
6085 break;
6086 case HCLGE_MAC_SPEED_100G:
6087 speed_led = HCLGE_SPEED_LED_FOR_100G;
6088 break;
6089 default: 7255 default:
6090 speed_led = HCLGE_LED_NO_CHANGE; 7256 return -EINVAL;
6091 } 7257 }
6092
6093 return speed_led;
6094}
6095
6096static int hclge_update_led_status(struct hclge_dev *hdev)
6097{
6098 u8 port_speed_status, link_status, activity_status;
6099 u64 rx_pkts, tx_pkts;
6100
6101 if (hdev->hw.mac.media_type != HNAE3_MEDIA_TYPE_FIBER)
6102 return 0;
6103
6104 port_speed_status = hclge_led_get_speed_status(hdev->hw.mac.speed);
6105
6106 rx_pkts = hdev->hw_stats.mac_stats.mac_rx_total_pkt_num;
6107 tx_pkts = hdev->hw_stats.mac_stats.mac_tx_total_pkt_num;
6108 if (rx_pkts != hdev->rx_pkts_for_led ||
6109 tx_pkts != hdev->tx_pkts_for_led)
6110 activity_status = HCLGE_LED_ON;
6111 else
6112 activity_status = HCLGE_LED_OFF;
6113 hdev->rx_pkts_for_led = rx_pkts;
6114 hdev->tx_pkts_for_led = tx_pkts;
6115
6116 if (hdev->hw.mac.link)
6117 link_status = HCLGE_LED_ON;
6118 else
6119 link_status = HCLGE_LED_OFF;
6120
6121 return hclge_set_led_status_sfp(hdev, port_speed_status,
6122 activity_status, link_status,
6123 HCLGE_LED_NO_CHANGE);
6124} 7258}
6125 7259
6126static void hclge_get_link_mode(struct hnae3_handle *handle, 7260static void hclge_get_link_mode(struct hnae3_handle *handle,
@@ -6138,27 +7272,6 @@ static void hclge_get_link_mode(struct hnae3_handle *handle,
6138 } 7272 }
6139} 7273}
6140 7274
6141static void hclge_get_port_type(struct hnae3_handle *handle,
6142 u8 *port_type)
6143{
6144 struct hclge_vport *vport = hclge_get_vport(handle);
6145 struct hclge_dev *hdev = vport->back;
6146 u8 media_type = hdev->hw.mac.media_type;
6147
6148 switch (media_type) {
6149 case HNAE3_MEDIA_TYPE_FIBER:
6150 *port_type = PORT_FIBRE;
6151 break;
6152 case HNAE3_MEDIA_TYPE_COPPER:
6153 *port_type = PORT_TP;
6154 break;
6155 case HNAE3_MEDIA_TYPE_UNKNOWN:
6156 default:
6157 *port_type = PORT_OTHER;
6158 break;
6159 }
6160}
6161
6162static const struct hnae3_ae_ops hclge_ops = { 7275static const struct hnae3_ae_ops hclge_ops = {
6163 .init_ae_dev = hclge_init_ae_dev, 7276 .init_ae_dev = hclge_init_ae_dev,
6164 .uninit_ae_dev = hclge_uninit_ae_dev, 7277 .uninit_ae_dev = hclge_uninit_ae_dev,
@@ -6186,6 +7299,7 @@ static const struct hnae3_ae_ops hclge_ops = {
6186 .get_tc_size = hclge_get_tc_size, 7299 .get_tc_size = hclge_get_tc_size,
6187 .get_mac_addr = hclge_get_mac_addr, 7300 .get_mac_addr = hclge_get_mac_addr,
6188 .set_mac_addr = hclge_set_mac_addr, 7301 .set_mac_addr = hclge_set_mac_addr,
7302 .do_ioctl = hclge_do_ioctl,
6189 .add_uc_addr = hclge_add_uc_addr, 7303 .add_uc_addr = hclge_add_uc_addr,
6190 .rm_uc_addr = hclge_rm_uc_addr, 7304 .rm_uc_addr = hclge_rm_uc_addr,
6191 .add_mc_addr = hclge_add_mc_addr, 7305 .add_mc_addr = hclge_add_mc_addr,
@@ -6203,24 +7317,30 @@ static const struct hnae3_ae_ops hclge_ops = {
6203 .get_fw_version = hclge_get_fw_version, 7317 .get_fw_version = hclge_get_fw_version,
6204 .get_mdix_mode = hclge_get_mdix_mode, 7318 .get_mdix_mode = hclge_get_mdix_mode,
6205 .enable_vlan_filter = hclge_enable_vlan_filter, 7319 .enable_vlan_filter = hclge_enable_vlan_filter,
6206 .set_vlan_filter = hclge_set_port_vlan_filter, 7320 .set_vlan_filter = hclge_set_vlan_filter,
6207 .set_vf_vlan_filter = hclge_set_vf_vlan_filter, 7321 .set_vf_vlan_filter = hclge_set_vf_vlan_filter,
6208 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag, 7322 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag,
6209 .reset_event = hclge_reset_event, 7323 .reset_event = hclge_reset_event,
6210 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info, 7324 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info,
6211 .set_channels = hclge_set_channels, 7325 .set_channels = hclge_set_channels,
6212 .get_channels = hclge_get_channels, 7326 .get_channels = hclge_get_channels,
6213 .get_flowctrl_adv = hclge_get_flowctrl_adv,
6214 .get_regs_len = hclge_get_regs_len, 7327 .get_regs_len = hclge_get_regs_len,
6215 .get_regs = hclge_get_regs, 7328 .get_regs = hclge_get_regs,
6216 .set_led_id = hclge_set_led_id, 7329 .set_led_id = hclge_set_led_id,
6217 .get_link_mode = hclge_get_link_mode, 7330 .get_link_mode = hclge_get_link_mode,
6218 .get_port_type = hclge_get_port_type, 7331 .add_fd_entry = hclge_add_fd_entry,
7332 .del_fd_entry = hclge_del_fd_entry,
7333 .del_all_fd_entries = hclge_del_all_fd_entries,
7334 .get_fd_rule_cnt = hclge_get_fd_rule_cnt,
7335 .get_fd_rule_info = hclge_get_fd_rule_info,
7336 .get_fd_all_rules = hclge_get_all_rules,
7337 .restore_fd_rules = hclge_restore_fd_entries,
7338 .enable_fd = hclge_enable_fd,
7339 .process_hw_error = hclge_process_ras_hw_error,
6219}; 7340};
6220 7341
6221static struct hnae3_ae_algo ae_algo = { 7342static struct hnae3_ae_algo ae_algo = {
6222 .ops = &hclge_ops, 7343 .ops = &hclge_ops,
6223 .name = HCLGE_NAME,
6224 .pdev_id_table = ae_algo_pci_tbl, 7344 .pdev_id_table = ae_algo_pci_tbl,
6225}; 7345};
6226 7346
@@ -6228,7 +7348,9 @@ static int hclge_init(void)
6228{ 7348{
6229 pr_info("%s is initializing\n", HCLGE_NAME); 7349 pr_info("%s is initializing\n", HCLGE_NAME);
6230 7350
6231 return hnae3_register_ae_algo(&ae_algo); 7351 hnae3_register_ae_algo(&ae_algo);
7352
7353 return 0;
6232} 7354}
6233 7355
6234static void hclge_exit(void) 7356static void hclge_exit(void)
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-05 03:26:51 -0500