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path: root/drivers/net/ethernet/cadence/macb_main.c
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Diffstat (limited to 'drivers/net/ethernet/cadence/macb_main.c')
-rw-r--r--drivers/net/ethernet/cadence/macb_main.c28
1 files changed, 17 insertions, 11 deletions
diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
index 66cc7927061a..2b2882615e8b 100644
--- a/drivers/net/ethernet/cadence/macb_main.c
+++ b/drivers/net/ethernet/cadence/macb_main.c
@@ -56,8 +56,7 @@
56/* level of occupied TX descriptors under which we wake up TX process */ 56/* level of occupied TX descriptors under which we wake up TX process */
57#define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4) 57#define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
58 58
59#define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \ 59#define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(ISR_ROVR))
60 | MACB_BIT(ISR_ROVR))
61#define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \ 60#define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
62 | MACB_BIT(ISR_RLE) \ 61 | MACB_BIT(ISR_RLE) \
63 | MACB_BIT(TXERR)) 62 | MACB_BIT(TXERR))
@@ -1270,7 +1269,7 @@ static int macb_poll(struct napi_struct *napi, int budget)
1270 queue_writel(queue, ISR, MACB_BIT(RCOMP)); 1269 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1271 napi_reschedule(napi); 1270 napi_reschedule(napi);
1272 } else { 1271 } else {
1273 queue_writel(queue, IER, MACB_RX_INT_FLAGS); 1272 queue_writel(queue, IER, bp->rx_intr_mask);
1274 } 1273 }
1275 } 1274 }
1276 1275
@@ -1288,7 +1287,7 @@ static void macb_hresp_error_task(unsigned long data)
1288 u32 ctrl; 1287 u32 ctrl;
1289 1288
1290 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { 1289 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1291 queue_writel(queue, IDR, MACB_RX_INT_FLAGS | 1290 queue_writel(queue, IDR, bp->rx_intr_mask |
1292 MACB_TX_INT_FLAGS | 1291 MACB_TX_INT_FLAGS |
1293 MACB_BIT(HRESP)); 1292 MACB_BIT(HRESP));
1294 } 1293 }
@@ -1318,7 +1317,7 @@ static void macb_hresp_error_task(unsigned long data)
1318 1317
1319 /* Enable interrupts */ 1318 /* Enable interrupts */
1320 queue_writel(queue, IER, 1319 queue_writel(queue, IER,
1321 MACB_RX_INT_FLAGS | 1320 bp->rx_intr_mask |
1322 MACB_TX_INT_FLAGS | 1321 MACB_TX_INT_FLAGS |
1323 MACB_BIT(HRESP)); 1322 MACB_BIT(HRESP));
1324 } 1323 }
@@ -1372,14 +1371,14 @@ static irqreturn_t macb_interrupt(int irq, void *dev_id)
1372 (unsigned int)(queue - bp->queues), 1371 (unsigned int)(queue - bp->queues),
1373 (unsigned long)status); 1372 (unsigned long)status);
1374 1373
1375 if (status & MACB_RX_INT_FLAGS) { 1374 if (status & bp->rx_intr_mask) {
1376 /* There's no point taking any more interrupts 1375 /* There's no point taking any more interrupts
1377 * until we have processed the buffers. The 1376 * until we have processed the buffers. The
1378 * scheduling call may fail if the poll routine 1377 * scheduling call may fail if the poll routine
1379 * is already scheduled, so disable interrupts 1378 * is already scheduled, so disable interrupts
1380 * now. 1379 * now.
1381 */ 1380 */
1382 queue_writel(queue, IDR, MACB_RX_INT_FLAGS); 1381 queue_writel(queue, IDR, bp->rx_intr_mask);
1383 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) 1382 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1384 queue_writel(queue, ISR, MACB_BIT(RCOMP)); 1383 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1385 1384
@@ -1412,8 +1411,9 @@ static irqreturn_t macb_interrupt(int irq, void *dev_id)
1412 /* There is a hardware issue under heavy load where DMA can 1411 /* There is a hardware issue under heavy load where DMA can
1413 * stop, this causes endless "used buffer descriptor read" 1412 * stop, this causes endless "used buffer descriptor read"
1414 * interrupts but it can be cleared by re-enabling RX. See 1413 * interrupts but it can be cleared by re-enabling RX. See
1415 * the at91 manual, section 41.3.1 or the Zynq manual 1414 * the at91rm9200 manual, section 41.3.1 or the Zynq manual
1416 * section 16.7.4 for details. 1415 * section 16.7.4 for details. RXUBR is only enabled for
1416 * these two versions.
1417 */ 1417 */
1418 if (status & MACB_BIT(RXUBR)) { 1418 if (status & MACB_BIT(RXUBR)) {
1419 ctrl = macb_readl(bp, NCR); 1419 ctrl = macb_readl(bp, NCR);
@@ -2259,7 +2259,7 @@ static void macb_init_hw(struct macb *bp)
2259 2259
2260 /* Enable interrupts */ 2260 /* Enable interrupts */
2261 queue_writel(queue, IER, 2261 queue_writel(queue, IER,
2262 MACB_RX_INT_FLAGS | 2262 bp->rx_intr_mask |
2263 MACB_TX_INT_FLAGS | 2263 MACB_TX_INT_FLAGS |
2264 MACB_BIT(HRESP)); 2264 MACB_BIT(HRESP));
2265 } 2265 }
@@ -3907,6 +3907,7 @@ static const struct macb_config sama5d4_config = {
3907}; 3907};
3908 3908
3909static const struct macb_config emac_config = { 3909static const struct macb_config emac_config = {
3910 .caps = MACB_CAPS_NEEDS_RSTONUBR,
3910 .clk_init = at91ether_clk_init, 3911 .clk_init = at91ether_clk_init,
3911 .init = at91ether_init, 3912 .init = at91ether_init,
3912}; 3913};
@@ -3928,7 +3929,8 @@ static const struct macb_config zynqmp_config = {
3928}; 3929};
3929 3930
3930static const struct macb_config zynq_config = { 3931static const struct macb_config zynq_config = {
3931 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_NO_GIGABIT_HALF, 3932 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_NO_GIGABIT_HALF |
3933 MACB_CAPS_NEEDS_RSTONUBR,
3932 .dma_burst_length = 16, 3934 .dma_burst_length = 16,
3933 .clk_init = macb_clk_init, 3935 .clk_init = macb_clk_init,
3934 .init = macb_init, 3936 .init = macb_init,
@@ -4083,6 +4085,10 @@ static int macb_probe(struct platform_device *pdev)
4083 macb_dma_desc_get_size(bp); 4085 macb_dma_desc_get_size(bp);
4084 } 4086 }
4085 4087
4088 bp->rx_intr_mask = MACB_RX_INT_FLAGS;
4089 if (bp->caps & MACB_CAPS_NEEDS_RSTONUBR)
4090 bp->rx_intr_mask |= MACB_BIT(RXUBR);
4091
4086 mac = of_get_mac_address(np); 4092 mac = of_get_mac_address(np);
4087 if (mac) { 4093 if (mac) {
4088 ether_addr_copy(bp->dev->dev_addr, mac); 4094 ether_addr_copy(bp->dev->dev_addr, mac);