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path: root/drivers/net/ethernet/cadence/macb.h
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Diffstat (limited to 'drivers/net/ethernet/cadence/macb.h')
-rw-r--r--drivers/net/ethernet/cadence/macb.h43
1 files changed, 23 insertions, 20 deletions
diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
index 24b1d9bcd865..1895b6b2addd 100644
--- a/drivers/net/ethernet/cadence/macb.h
+++ b/drivers/net/ethernet/cadence/macb.h
@@ -71,6 +71,7 @@
71#define GEM_NCFGR 0x0004 /* Network Config */ 71#define GEM_NCFGR 0x0004 /* Network Config */
72#define GEM_USRIO 0x000c /* User IO */ 72#define GEM_USRIO 0x000c /* User IO */
73#define GEM_DMACFG 0x0010 /* DMA Configuration */ 73#define GEM_DMACFG 0x0010 /* DMA Configuration */
74#define GEM_JML 0x0048 /* Jumbo Max Length */
74#define GEM_HRB 0x0080 /* Hash Bottom */ 75#define GEM_HRB 0x0080 /* Hash Bottom */
75#define GEM_HRT 0x0084 /* Hash Top */ 76#define GEM_HRT 0x0084 /* Hash Top */
76#define GEM_SA1B 0x0088 /* Specific1 Bottom */ 77#define GEM_SA1B 0x0088 /* Specific1 Bottom */
@@ -398,6 +399,7 @@
398#define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000 399#define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000
399#define MACB_CAPS_SG_DISABLED 0x40000000 400#define MACB_CAPS_SG_DISABLED 0x40000000
400#define MACB_CAPS_MACB_IS_GEM 0x80000000 401#define MACB_CAPS_MACB_IS_GEM 0x80000000
402#define MACB_CAPS_JUMBO 0x00000008
401 403
402/* Bit manipulation macros */ 404/* Bit manipulation macros */
403#define MACB_BIT(name) \ 405#define MACB_BIT(name) \
@@ -427,18 +429,12 @@
427 | GEM_BF(name, value)) 429 | GEM_BF(name, value))
428 430
429/* Register access macros */ 431/* Register access macros */
430#define macb_readl(port,reg) \ 432#define macb_readl(port, reg) (port)->macb_reg_readl((port), MACB_##reg)
431 readl_relaxed((port)->regs + MACB_##reg) 433#define macb_writel(port, reg, value) (port)->macb_reg_writel((port), MACB_##reg, (value))
432#define macb_writel(port,reg,value) \ 434#define gem_readl(port, reg) (port)->macb_reg_readl((port), GEM_##reg)
433 writel_relaxed((value), (port)->regs + MACB_##reg) 435#define gem_writel(port, reg, value) (port)->macb_reg_writel((port), GEM_##reg, (value))
434#define gem_readl(port, reg) \ 436#define queue_readl(queue, reg) (queue)->bp->macb_reg_readl((queue)->bp, (queue)->reg)
435 readl_relaxed((port)->regs + GEM_##reg) 437#define queue_writel(queue, reg, value) (queue)->bp->macb_reg_writel((queue)->bp, (queue)->reg, (value))
436#define gem_writel(port, reg, value) \
437 writel_relaxed((value), (port)->regs + GEM_##reg)
438#define queue_readl(queue, reg) \
439 readl_relaxed((queue)->bp->regs + (queue)->reg)
440#define queue_writel(queue, reg, value) \
441 writel_relaxed((value), (queue)->bp->regs + (queue)->reg)
442 438
443/* Conditional GEM/MACB macros. These perform the operation to the correct 439/* Conditional GEM/MACB macros. These perform the operation to the correct
444 * register dependent on whether the device is a GEM or a MACB. For registers 440 * register dependent on whether the device is a GEM or a MACB. For registers
@@ -515,6 +511,9 @@ struct macb_dma_desc {
515#define MACB_RX_BROADCAST_OFFSET 31 511#define MACB_RX_BROADCAST_OFFSET 31
516#define MACB_RX_BROADCAST_SIZE 1 512#define MACB_RX_BROADCAST_SIZE 1
517 513
514#define MACB_RX_FRMLEN_MASK 0xFFF
515#define MACB_RX_JFRMLEN_MASK 0x3FFF
516
518/* RX checksum offload disabled: bit 24 clear in NCFGR */ 517/* RX checksum offload disabled: bit 24 clear in NCFGR */
519#define GEM_RX_TYPEID_MATCH_OFFSET 22 518#define GEM_RX_TYPEID_MATCH_OFFSET 22
520#define GEM_RX_TYPEID_MATCH_SIZE 2 519#define GEM_RX_TYPEID_MATCH_SIZE 2
@@ -758,6 +757,7 @@ struct macb_config {
758 int (*clk_init)(struct platform_device *pdev, struct clk **pclk, 757 int (*clk_init)(struct platform_device *pdev, struct clk **pclk,
759 struct clk **hclk, struct clk **tx_clk); 758 struct clk **hclk, struct clk **tx_clk);
760 int (*init)(struct platform_device *pdev); 759 int (*init)(struct platform_device *pdev);
760 int jumbo_max_len;
761}; 761};
762 762
763struct macb_queue { 763struct macb_queue {
@@ -779,6 +779,11 @@ struct macb_queue {
779 779
780struct macb { 780struct macb {
781 void __iomem *regs; 781 void __iomem *regs;
782 bool native_io;
783
784 /* hardware IO accessors */
785 u32 (*macb_reg_readl)(struct macb *bp, int offset);
786 void (*macb_reg_writel)(struct macb *bp, int offset, u32 value);
782 787
783 unsigned int rx_tail; 788 unsigned int rx_tail;
784 unsigned int rx_prepared_head; 789 unsigned int rx_prepared_head;
@@ -811,9 +816,9 @@ struct macb {
811 816
812 struct mii_bus *mii_bus; 817 struct mii_bus *mii_bus;
813 struct phy_device *phy_dev; 818 struct phy_device *phy_dev;
814 unsigned int link; 819 int link;
815 unsigned int speed; 820 int speed;
816 unsigned int duplex; 821 int duplex;
817 822
818 u32 caps; 823 u32 caps;
819 unsigned int dma_burst_length; 824 unsigned int dma_burst_length;
@@ -827,6 +832,9 @@ struct macb {
827 unsigned int max_tx_length; 832 unsigned int max_tx_length;
828 833
829 u64 ethtool_stats[GEM_STATS_LEN]; 834 u64 ethtool_stats[GEM_STATS_LEN];
835
836 unsigned int rx_frm_len_mask;
837 unsigned int jumbo_max_len;
830}; 838};
831 839
832static inline bool macb_is_gem(struct macb *bp) 840static inline bool macb_is_gem(struct macb *bp)
@@ -834,9 +842,4 @@ static inline bool macb_is_gem(struct macb *bp)
834 return !!(bp->caps & MACB_CAPS_MACB_IS_GEM); 842 return !!(bp->caps & MACB_CAPS_MACB_IS_GEM);
835} 843}
836 844
837static inline bool macb_is_gem_hw(void __iomem *addr)
838{
839 return !!(MACB_BFEXT(IDNUM, readl_relaxed(addr + MACB_MID)) >= 0x2);
840}
841
842#endif /* _MACB_H */ 845#endif /* _MACB_H */