diff options
Diffstat (limited to 'drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c')
| -rw-r--r-- | drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c index ac76fc251d26..a851f95c307a 100644 --- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c +++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c | |||
| @@ -4166,14 +4166,14 @@ static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn) | |||
| 4166 | bnx2x_release_phy_lock(bp); | 4166 | bnx2x_release_phy_lock(bp); |
| 4167 | } | 4167 | } |
| 4168 | 4168 | ||
| 4169 | if (attn & HW_INTERRUT_ASSERT_SET_0) { | 4169 | if (attn & HW_INTERRUPT_ASSERT_SET_0) { |
| 4170 | 4170 | ||
| 4171 | val = REG_RD(bp, reg_offset); | 4171 | val = REG_RD(bp, reg_offset); |
| 4172 | val &= ~(attn & HW_INTERRUT_ASSERT_SET_0); | 4172 | val &= ~(attn & HW_INTERRUPT_ASSERT_SET_0); |
| 4173 | REG_WR(bp, reg_offset, val); | 4173 | REG_WR(bp, reg_offset, val); |
| 4174 | 4174 | ||
| 4175 | BNX2X_ERR("FATAL HW block attention set0 0x%x\n", | 4175 | BNX2X_ERR("FATAL HW block attention set0 0x%x\n", |
| 4176 | (u32)(attn & HW_INTERRUT_ASSERT_SET_0)); | 4176 | (u32)(attn & HW_INTERRUPT_ASSERT_SET_0)); |
| 4177 | bnx2x_panic(); | 4177 | bnx2x_panic(); |
| 4178 | } | 4178 | } |
| 4179 | } | 4179 | } |
| @@ -4191,7 +4191,7 @@ static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn) | |||
| 4191 | BNX2X_ERR("FATAL error from DORQ\n"); | 4191 | BNX2X_ERR("FATAL error from DORQ\n"); |
| 4192 | } | 4192 | } |
| 4193 | 4193 | ||
| 4194 | if (attn & HW_INTERRUT_ASSERT_SET_1) { | 4194 | if (attn & HW_INTERRUPT_ASSERT_SET_1) { |
| 4195 | 4195 | ||
| 4196 | int port = BP_PORT(bp); | 4196 | int port = BP_PORT(bp); |
| 4197 | int reg_offset; | 4197 | int reg_offset; |
| @@ -4200,11 +4200,11 @@ static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn) | |||
| 4200 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1); | 4200 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1); |
| 4201 | 4201 | ||
| 4202 | val = REG_RD(bp, reg_offset); | 4202 | val = REG_RD(bp, reg_offset); |
| 4203 | val &= ~(attn & HW_INTERRUT_ASSERT_SET_1); | 4203 | val &= ~(attn & HW_INTERRUPT_ASSERT_SET_1); |
| 4204 | REG_WR(bp, reg_offset, val); | 4204 | REG_WR(bp, reg_offset, val); |
| 4205 | 4205 | ||
| 4206 | BNX2X_ERR("FATAL HW block attention set1 0x%x\n", | 4206 | BNX2X_ERR("FATAL HW block attention set1 0x%x\n", |
| 4207 | (u32)(attn & HW_INTERRUT_ASSERT_SET_1)); | 4207 | (u32)(attn & HW_INTERRUPT_ASSERT_SET_1)); |
| 4208 | bnx2x_panic(); | 4208 | bnx2x_panic(); |
| 4209 | } | 4209 | } |
| 4210 | } | 4210 | } |
| @@ -4235,7 +4235,7 @@ static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn) | |||
| 4235 | } | 4235 | } |
| 4236 | } | 4236 | } |
| 4237 | 4237 | ||
| 4238 | if (attn & HW_INTERRUT_ASSERT_SET_2) { | 4238 | if (attn & HW_INTERRUPT_ASSERT_SET_2) { |
| 4239 | 4239 | ||
| 4240 | int port = BP_PORT(bp); | 4240 | int port = BP_PORT(bp); |
| 4241 | int reg_offset; | 4241 | int reg_offset; |
| @@ -4244,11 +4244,11 @@ static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn) | |||
| 4244 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2); | 4244 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2); |
| 4245 | 4245 | ||
| 4246 | val = REG_RD(bp, reg_offset); | 4246 | val = REG_RD(bp, reg_offset); |
| 4247 | val &= ~(attn & HW_INTERRUT_ASSERT_SET_2); | 4247 | val &= ~(attn & HW_INTERRUPT_ASSERT_SET_2); |
| 4248 | REG_WR(bp, reg_offset, val); | 4248 | REG_WR(bp, reg_offset, val); |
| 4249 | 4249 | ||
| 4250 | BNX2X_ERR("FATAL HW block attention set2 0x%x\n", | 4250 | BNX2X_ERR("FATAL HW block attention set2 0x%x\n", |
| 4251 | (u32)(attn & HW_INTERRUT_ASSERT_SET_2)); | 4251 | (u32)(attn & HW_INTERRUPT_ASSERT_SET_2)); |
| 4252 | bnx2x_panic(); | 4252 | bnx2x_panic(); |
| 4253 | } | 4253 | } |
| 4254 | } | 4254 | } |
