diff options
Diffstat (limited to 'drivers/net/ethernet/atheros/alx/reg.h')
| -rw-r--r-- | drivers/net/ethernet/atheros/alx/reg.h | 810 |
1 files changed, 810 insertions, 0 deletions
diff --git a/drivers/net/ethernet/atheros/alx/reg.h b/drivers/net/ethernet/atheros/alx/reg.h new file mode 100644 index 000000000000..e4358c98bc4e --- /dev/null +++ b/drivers/net/ethernet/atheros/alx/reg.h | |||
| @@ -0,0 +1,810 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2013 Johannes Berg <johannes@sipsolutions.net> | ||
| 3 | * | ||
| 4 | * This file is free software: you may copy, redistribute and/or modify it | ||
| 5 | * under the terms of the GNU General Public License as published by the | ||
| 6 | * Free Software Foundation, either version 2 of the License, or (at your | ||
| 7 | * option) any later version. | ||
| 8 | * | ||
| 9 | * This file is distributed in the hope that it will be useful, but | ||
| 10 | * WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
| 12 | * General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License | ||
| 15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
| 16 | * | ||
| 17 | * This file incorporates work covered by the following copyright and | ||
| 18 | * permission notice: | ||
| 19 | * | ||
| 20 | * Copyright (c) 2012 Qualcomm Atheros, Inc. | ||
| 21 | * | ||
| 22 | * Permission to use, copy, modify, and/or distribute this software for any | ||
| 23 | * purpose with or without fee is hereby granted, provided that the above | ||
| 24 | * copyright notice and this permission notice appear in all copies. | ||
| 25 | * | ||
| 26 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
| 27 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
| 28 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
| 29 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
| 30 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
| 31 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
| 32 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
| 33 | */ | ||
| 34 | |||
| 35 | #ifndef ALX_REG_H | ||
| 36 | #define ALX_REG_H | ||
| 37 | |||
| 38 | #define ALX_DEV_ID_AR8161 0x1091 | ||
| 39 | #define ALX_DEV_ID_E2200 0xe091 | ||
| 40 | #define ALX_DEV_ID_AR8162 0x1090 | ||
| 41 | #define ALX_DEV_ID_AR8171 0x10A1 | ||
| 42 | #define ALX_DEV_ID_AR8172 0x10A0 | ||
| 43 | |||
| 44 | /* rev definition, | ||
| 45 | * bit(0): with xD support | ||
| 46 | * bit(1): with Card Reader function | ||
| 47 | * bit(7:2): real revision | ||
| 48 | */ | ||
| 49 | #define ALX_PCI_REVID_SHIFT 3 | ||
| 50 | #define ALX_REV_A0 0 | ||
| 51 | #define ALX_REV_A1 1 | ||
| 52 | #define ALX_REV_B0 2 | ||
| 53 | #define ALX_REV_C0 3 | ||
| 54 | |||
| 55 | #define ALX_DEV_CTRL 0x0060 | ||
| 56 | #define ALX_DEV_CTRL_MAXRRS_MIN 2 | ||
| 57 | |||
| 58 | #define ALX_MSIX_MASK 0x0090 | ||
| 59 | |||
| 60 | #define ALX_UE_SVRT 0x010C | ||
| 61 | #define ALX_UE_SVRT_FCPROTERR BIT(13) | ||
| 62 | #define ALX_UE_SVRT_DLPROTERR BIT(4) | ||
| 63 | |||
| 64 | /* eeprom & flash load register */ | ||
| 65 | #define ALX_EFLD 0x0204 | ||
| 66 | #define ALX_EFLD_F_EXIST BIT(10) | ||
| 67 | #define ALX_EFLD_E_EXIST BIT(9) | ||
| 68 | #define ALX_EFLD_STAT BIT(5) | ||
| 69 | #define ALX_EFLD_START BIT(0) | ||
| 70 | |||
| 71 | /* eFuse load register */ | ||
| 72 | #define ALX_SLD 0x0218 | ||
| 73 | #define ALX_SLD_STAT BIT(12) | ||
| 74 | #define ALX_SLD_START BIT(11) | ||
| 75 | #define ALX_SLD_MAX_TO 100 | ||
| 76 | |||
| 77 | #define ALX_PDLL_TRNS1 0x1104 | ||
| 78 | #define ALX_PDLL_TRNS1_D3PLLOFF_EN BIT(11) | ||
| 79 | |||
| 80 | #define ALX_PMCTRL 0x12F8 | ||
| 81 | #define ALX_PMCTRL_HOTRST_WTEN BIT(31) | ||
| 82 | /* bit30: L0s/L1 controlled by MAC based on throughput(setting in 15A0) */ | ||
| 83 | #define ALX_PMCTRL_ASPM_FCEN BIT(30) | ||
| 84 | #define ALX_PMCTRL_SADLY_EN BIT(29) | ||
| 85 | #define ALX_PMCTRL_LCKDET_TIMER_MASK 0xF | ||
| 86 | #define ALX_PMCTRL_LCKDET_TIMER_SHIFT 24 | ||
| 87 | #define ALX_PMCTRL_LCKDET_TIMER_DEF 0xC | ||
| 88 | /* bit[23:20] if pm_request_l1 time > @, then enter L0s not L1 */ | ||
| 89 | #define ALX_PMCTRL_L1REQ_TO_MASK 0xF | ||
| 90 | #define ALX_PMCTRL_L1REQ_TO_SHIFT 20 | ||
| 91 | #define ALX_PMCTRL_L1REG_TO_DEF 0xF | ||
| 92 | #define ALX_PMCTRL_TXL1_AFTER_L0S BIT(19) | ||
| 93 | #define ALX_PMCTRL_L1_TIMER_MASK 0x7 | ||
| 94 | #define ALX_PMCTRL_L1_TIMER_SHIFT 16 | ||
| 95 | #define ALX_PMCTRL_L1_TIMER_16US 4 | ||
| 96 | #define ALX_PMCTRL_RCVR_WT_1US BIT(15) | ||
| 97 | /* bit13: enable pcie clk switch in L1 state */ | ||
| 98 | #define ALX_PMCTRL_L1_CLKSW_EN BIT(13) | ||
| 99 | #define ALX_PMCTRL_L0S_EN BIT(12) | ||
| 100 | #define ALX_PMCTRL_RXL1_AFTER_L0S BIT(11) | ||
| 101 | #define ALX_PMCTRL_L1_BUFSRX_EN BIT(7) | ||
| 102 | /* bit6: power down serdes RX */ | ||
| 103 | #define ALX_PMCTRL_L1_SRDSRX_PWD BIT(6) | ||
| 104 | #define ALX_PMCTRL_L1_SRDSPLL_EN BIT(5) | ||
| 105 | #define ALX_PMCTRL_L1_SRDS_EN BIT(4) | ||
| 106 | #define ALX_PMCTRL_L1_EN BIT(3) | ||
| 107 | |||
| 108 | /*******************************************************/ | ||
| 109 | /* following registers are mapped only to memory space */ | ||
| 110 | /*******************************************************/ | ||
| 111 | |||
| 112 | #define ALX_MASTER 0x1400 | ||
| 113 | /* bit12: 1:alwys select pclk from serdes, not sw to 25M */ | ||
| 114 | #define ALX_MASTER_PCLKSEL_SRDS BIT(12) | ||
| 115 | /* bit11: irq moduration for rx */ | ||
| 116 | #define ALX_MASTER_IRQMOD2_EN BIT(11) | ||
| 117 | /* bit10: irq moduration for tx/rx */ | ||
| 118 | #define ALX_MASTER_IRQMOD1_EN BIT(10) | ||
| 119 | #define ALX_MASTER_SYSALVTIMER_EN BIT(7) | ||
| 120 | #define ALX_MASTER_OOB_DIS BIT(6) | ||
| 121 | /* bit5: wakeup without pcie clk */ | ||
| 122 | #define ALX_MASTER_WAKEN_25M BIT(5) | ||
| 123 | /* bit0: MAC & DMA reset */ | ||
| 124 | #define ALX_MASTER_DMA_MAC_RST BIT(0) | ||
| 125 | #define ALX_DMA_MAC_RST_TO 50 | ||
| 126 | |||
| 127 | #define ALX_IRQ_MODU_TIMER 0x1408 | ||
| 128 | #define ALX_IRQ_MODU_TIMER1_MASK 0xFFFF | ||
| 129 | #define ALX_IRQ_MODU_TIMER1_SHIFT 0 | ||
| 130 | |||
| 131 | #define ALX_PHY_CTRL 0x140C | ||
| 132 | #define ALX_PHY_CTRL_100AB_EN BIT(17) | ||
| 133 | /* bit14: affect MAC & PHY, go to low power sts */ | ||
| 134 | #define ALX_PHY_CTRL_POWER_DOWN BIT(14) | ||
| 135 | /* bit13: 1:pll always ON, 0:can switch in lpw */ | ||
| 136 | #define ALX_PHY_CTRL_PLL_ON BIT(13) | ||
| 137 | #define ALX_PHY_CTRL_RST_ANALOG BIT(12) | ||
| 138 | #define ALX_PHY_CTRL_HIB_PULSE BIT(11) | ||
| 139 | #define ALX_PHY_CTRL_HIB_EN BIT(10) | ||
| 140 | #define ALX_PHY_CTRL_IDDQ BIT(7) | ||
| 141 | #define ALX_PHY_CTRL_GATE_25M BIT(5) | ||
| 142 | #define ALX_PHY_CTRL_LED_MODE BIT(2) | ||
| 143 | /* bit0: out of dsp RST state */ | ||
| 144 | #define ALX_PHY_CTRL_DSPRST_OUT BIT(0) | ||
| 145 | #define ALX_PHY_CTRL_DSPRST_TO 80 | ||
| 146 | #define ALX_PHY_CTRL_CLS (ALX_PHY_CTRL_LED_MODE | \ | ||
| 147 | ALX_PHY_CTRL_100AB_EN | \ | ||
| 148 | ALX_PHY_CTRL_PLL_ON) | ||
| 149 | |||
| 150 | #define ALX_MAC_STS 0x1410 | ||
| 151 | #define ALX_MAC_STS_TXQ_BUSY BIT(3) | ||
| 152 | #define ALX_MAC_STS_RXQ_BUSY BIT(2) | ||
| 153 | #define ALX_MAC_STS_TXMAC_BUSY BIT(1) | ||
| 154 | #define ALX_MAC_STS_RXMAC_BUSY BIT(0) | ||
| 155 | #define ALX_MAC_STS_IDLE (ALX_MAC_STS_TXQ_BUSY | \ | ||
| 156 | ALX_MAC_STS_RXQ_BUSY | \ | ||
| 157 | ALX_MAC_STS_TXMAC_BUSY | \ | ||
| 158 | ALX_MAC_STS_RXMAC_BUSY) | ||
| 159 | |||
| 160 | #define ALX_MDIO 0x1414 | ||
| 161 | #define ALX_MDIO_MODE_EXT BIT(30) | ||
| 162 | #define ALX_MDIO_BUSY BIT(27) | ||
| 163 | #define ALX_MDIO_CLK_SEL_MASK 0x7 | ||
| 164 | #define ALX_MDIO_CLK_SEL_SHIFT 24 | ||
| 165 | #define ALX_MDIO_CLK_SEL_25MD4 0 | ||
| 166 | #define ALX_MDIO_CLK_SEL_25MD128 7 | ||
| 167 | #define ALX_MDIO_START BIT(23) | ||
| 168 | #define ALX_MDIO_SPRES_PRMBL BIT(22) | ||
| 169 | /* bit21: 1:read,0:write */ | ||
| 170 | #define ALX_MDIO_OP_READ BIT(21) | ||
| 171 | #define ALX_MDIO_REG_MASK 0x1F | ||
| 172 | #define ALX_MDIO_REG_SHIFT 16 | ||
| 173 | #define ALX_MDIO_DATA_MASK 0xFFFF | ||
| 174 | #define ALX_MDIO_DATA_SHIFT 0 | ||
| 175 | #define ALX_MDIO_MAX_AC_TO 120 | ||
| 176 | |||
| 177 | #define ALX_MDIO_EXTN 0x1448 | ||
| 178 | #define ALX_MDIO_EXTN_DEVAD_MASK 0x1F | ||
| 179 | #define ALX_MDIO_EXTN_DEVAD_SHIFT 16 | ||
| 180 | #define ALX_MDIO_EXTN_REG_MASK 0xFFFF | ||
| 181 | #define ALX_MDIO_EXTN_REG_SHIFT 0 | ||
| 182 | |||
| 183 | #define ALX_SERDES 0x1424 | ||
| 184 | #define ALX_SERDES_PHYCLK_SLWDWN BIT(18) | ||
| 185 | #define ALX_SERDES_MACCLK_SLWDWN BIT(17) | ||
| 186 | |||
| 187 | #define ALX_LPI_CTRL 0x1440 | ||
| 188 | #define ALX_LPI_CTRL_EN BIT(0) | ||
| 189 | |||
| 190 | /* for B0+, bit[13..] for C0+ */ | ||
| 191 | #define ALX_HRTBT_EXT_CTRL 0x1AD0 | ||
| 192 | #define L1F_HRTBT_EXT_CTRL_PERIOD_HIGH_MASK 0x3F | ||
| 193 | #define L1F_HRTBT_EXT_CTRL_PERIOD_HIGH_SHIFT 24 | ||
| 194 | #define L1F_HRTBT_EXT_CTRL_SWOI_STARTUP_PKT_EN BIT(23) | ||
| 195 | #define L1F_HRTBT_EXT_CTRL_IOAC_2_FRAGMENTED BIT(22) | ||
| 196 | #define L1F_HRTBT_EXT_CTRL_IOAC_1_FRAGMENTED BIT(21) | ||
| 197 | #define L1F_HRTBT_EXT_CTRL_IOAC_1_KEEPALIVE_EN BIT(20) | ||
| 198 | #define L1F_HRTBT_EXT_CTRL_IOAC_1_HAS_VLAN BIT(19) | ||
| 199 | #define L1F_HRTBT_EXT_CTRL_IOAC_1_IS_8023 BIT(18) | ||
| 200 | #define L1F_HRTBT_EXT_CTRL_IOAC_1_IS_IPV6 BIT(17) | ||
| 201 | #define L1F_HRTBT_EXT_CTRL_IOAC_2_KEEPALIVE_EN BIT(16) | ||
| 202 | #define L1F_HRTBT_EXT_CTRL_IOAC_2_HAS_VLAN BIT(15) | ||
| 203 | #define L1F_HRTBT_EXT_CTRL_IOAC_2_IS_8023 BIT(14) | ||
| 204 | #define L1F_HRTBT_EXT_CTRL_IOAC_2_IS_IPV6 BIT(13) | ||
| 205 | #define ALX_HRTBT_EXT_CTRL_NS_EN BIT(12) | ||
| 206 | #define ALX_HRTBT_EXT_CTRL_FRAG_LEN_MASK 0xFF | ||
| 207 | #define ALX_HRTBT_EXT_CTRL_FRAG_LEN_SHIFT 4 | ||
| 208 | #define ALX_HRTBT_EXT_CTRL_IS_8023 BIT(3) | ||
| 209 | #define ALX_HRTBT_EXT_CTRL_IS_IPV6 BIT(2) | ||
| 210 | #define ALX_HRTBT_EXT_CTRL_WAKEUP_EN BIT(1) | ||
| 211 | #define ALX_HRTBT_EXT_CTRL_ARP_EN BIT(0) | ||
| 212 | |||
| 213 | #define ALX_HRTBT_REM_IPV4_ADDR 0x1AD4 | ||
| 214 | #define ALX_HRTBT_HOST_IPV4_ADDR 0x1478 | ||
| 215 | #define ALX_HRTBT_REM_IPV6_ADDR3 0x1AD8 | ||
| 216 | #define ALX_HRTBT_REM_IPV6_ADDR2 0x1ADC | ||
| 217 | #define ALX_HRTBT_REM_IPV6_ADDR1 0x1AE0 | ||
| 218 | #define ALX_HRTBT_REM_IPV6_ADDR0 0x1AE4 | ||
| 219 | |||
| 220 | /* 1B8C ~ 1B94 for C0+ */ | ||
| 221 | #define ALX_SWOI_ACER_CTRL 0x1B8C | ||
| 222 | #define ALX_SWOI_ORIG_ACK_NAK_EN BIT(20) | ||
| 223 | #define ALX_SWOI_ORIG_ACK_NAK_PKT_LEN_MASK 0XFF | ||
| 224 | #define ALX_SWOI_ORIG_ACK_NAK_PKT_LEN_SHIFT 12 | ||
| 225 | #define ALX_SWOI_ORIG_ACK_ADDR_MASK 0XFFF | ||
| 226 | #define ALX_SWOI_ORIG_ACK_ADDR_SHIFT 0 | ||
| 227 | |||
| 228 | #define ALX_SWOI_IOAC_CTRL_2 0x1B90 | ||
| 229 | #define ALX_SWOI_IOAC_CTRL_2_SWOI_1_FRAG_LEN_MASK 0xFF | ||
| 230 | #define ALX_SWOI_IOAC_CTRL_2_SWOI_1_FRAG_LEN_SHIFT 24 | ||
| 231 | #define ALX_SWOI_IOAC_CTRL_2_SWOI_1_PKT_LEN_MASK 0xFFF | ||
| 232 | #define ALX_SWOI_IOAC_CTRL_2_SWOI_1_PKT_LEN_SHIFT 12 | ||
| 233 | #define ALX_SWOI_IOAC_CTRL_2_SWOI_1_HDR_ADDR_MASK 0xFFF | ||
| 234 | #define ALX_SWOI_IOAC_CTRL_2_SWOI_1_HDR_ADDR_SHIFT 0 | ||
| 235 | |||
| 236 | #define ALX_SWOI_IOAC_CTRL_3 0x1B94 | ||
| 237 | #define ALX_SWOI_IOAC_CTRL_3_SWOI_2_FRAG_LEN_MASK 0xFF | ||
| 238 | #define ALX_SWOI_IOAC_CTRL_3_SWOI_2_FRAG_LEN_SHIFT 24 | ||
| 239 | #define ALX_SWOI_IOAC_CTRL_3_SWOI_2_PKT_LEN_MASK 0xFFF | ||
| 240 | #define ALX_SWOI_IOAC_CTRL_3_SWOI_2_PKT_LEN_SHIFT 12 | ||
| 241 | #define ALX_SWOI_IOAC_CTRL_3_SWOI_2_HDR_ADDR_MASK 0xFFF | ||
| 242 | #define ALX_SWOI_IOAC_CTRL_3_SWOI_2_HDR_ADDR_SHIFT 0 | ||
| 243 | |||
| 244 | /* for B0 */ | ||
| 245 | #define ALX_IDLE_DECISN_TIMER 0x1474 | ||
| 246 | /* 1ms */ | ||
| 247 | #define ALX_IDLE_DECISN_TIMER_DEF 0x400 | ||
| 248 | |||
| 249 | #define ALX_MAC_CTRL 0x1480 | ||
| 250 | #define ALX_MAC_CTRL_FAST_PAUSE BIT(31) | ||
| 251 | #define ALX_MAC_CTRL_WOLSPED_SWEN BIT(30) | ||
| 252 | /* bit29: 1:legacy(hi5b), 0:marvl(lo5b)*/ | ||
| 253 | #define ALX_MAC_CTRL_MHASH_ALG_HI5B BIT(29) | ||
| 254 | #define ALX_MAC_CTRL_BRD_EN BIT(26) | ||
| 255 | #define ALX_MAC_CTRL_MULTIALL_EN BIT(25) | ||
| 256 | #define ALX_MAC_CTRL_SPEED_MASK 0x3 | ||
| 257 | #define ALX_MAC_CTRL_SPEED_SHIFT 20 | ||
| 258 | #define ALX_MAC_CTRL_SPEED_10_100 1 | ||
| 259 | #define ALX_MAC_CTRL_SPEED_1000 2 | ||
| 260 | #define ALX_MAC_CTRL_PROMISC_EN BIT(15) | ||
| 261 | #define ALX_MAC_CTRL_VLANSTRIP BIT(14) | ||
| 262 | #define ALX_MAC_CTRL_PRMBLEN_MASK 0xF | ||
| 263 | #define ALX_MAC_CTRL_PRMBLEN_SHIFT 10 | ||
| 264 | #define ALX_MAC_CTRL_PCRCE BIT(7) | ||
| 265 | #define ALX_MAC_CTRL_CRCE BIT(6) | ||
| 266 | #define ALX_MAC_CTRL_FULLD BIT(5) | ||
| 267 | #define ALX_MAC_CTRL_RXFC_EN BIT(3) | ||
| 268 | #define ALX_MAC_CTRL_TXFC_EN BIT(2) | ||
| 269 | #define ALX_MAC_CTRL_RX_EN BIT(1) | ||
| 270 | #define ALX_MAC_CTRL_TX_EN BIT(0) | ||
| 271 | |||
| 272 | #define ALX_STAD0 0x1488 | ||
| 273 | #define ALX_STAD1 0x148C | ||
| 274 | |||
| 275 | #define ALX_HASH_TBL0 0x1490 | ||
| 276 | #define ALX_HASH_TBL1 0x1494 | ||
| 277 | |||
| 278 | #define ALX_MTU 0x149C | ||
| 279 | #define ALX_MTU_JUMBO_TH 1514 | ||
| 280 | #define ALX_MTU_STD_ALGN 1536 | ||
| 281 | |||
| 282 | #define ALX_SRAM5 0x1524 | ||
| 283 | #define ALX_SRAM_RXF_LEN_MASK 0xFFF | ||
| 284 | #define ALX_SRAM_RXF_LEN_SHIFT 0 | ||
| 285 | #define ALX_SRAM_RXF_LEN_8K (8*1024) | ||
| 286 | |||
| 287 | #define ALX_SRAM9 0x1534 | ||
| 288 | #define ALX_SRAM_LOAD_PTR BIT(0) | ||
| 289 | |||
| 290 | #define ALX_RX_BASE_ADDR_HI 0x1540 | ||
| 291 | |||
| 292 | #define ALX_TX_BASE_ADDR_HI 0x1544 | ||
| 293 | |||
| 294 | #define ALX_RFD_ADDR_LO 0x1550 | ||
| 295 | #define ALX_RFD_RING_SZ 0x1560 | ||
| 296 | #define ALX_RFD_BUF_SZ 0x1564 | ||
| 297 | |||
| 298 | #define ALX_RRD_ADDR_LO 0x1568 | ||
| 299 | #define ALX_RRD_RING_SZ 0x1578 | ||
| 300 | |||
| 301 | /* pri3: highest, pri0: lowest */ | ||
| 302 | #define ALX_TPD_PRI3_ADDR_LO 0x14E4 | ||
| 303 | #define ALX_TPD_PRI2_ADDR_LO 0x14E0 | ||
| 304 | #define ALX_TPD_PRI1_ADDR_LO 0x157C | ||
| 305 | #define ALX_TPD_PRI0_ADDR_LO 0x1580 | ||
| 306 | |||
| 307 | /* producer index is 16bit */ | ||
| 308 | #define ALX_TPD_PRI3_PIDX 0x1618 | ||
| 309 | #define ALX_TPD_PRI2_PIDX 0x161A | ||
| 310 | #define ALX_TPD_PRI1_PIDX 0x15F0 | ||
| 311 | #define ALX_TPD_PRI0_PIDX 0x15F2 | ||
| 312 | |||
| 313 | /* consumer index is 16bit */ | ||
| 314 | #define ALX_TPD_PRI3_CIDX 0x161C | ||
| 315 | #define ALX_TPD_PRI2_CIDX 0x161E | ||
| 316 | #define ALX_TPD_PRI1_CIDX 0x15F4 | ||
| 317 | #define ALX_TPD_PRI0_CIDX 0x15F6 | ||
| 318 | |||
| 319 | #define ALX_TPD_RING_SZ 0x1584 | ||
| 320 | |||
| 321 | #define ALX_TXQ0 0x1590 | ||
| 322 | #define ALX_TXQ0_TXF_BURST_PREF_MASK 0xFFFF | ||
| 323 | #define ALX_TXQ0_TXF_BURST_PREF_SHIFT 16 | ||
| 324 | #define ALX_TXQ_TXF_BURST_PREF_DEF 0x200 | ||
| 325 | #define ALX_TXQ0_LSO_8023_EN BIT(7) | ||
| 326 | #define ALX_TXQ0_MODE_ENHANCE BIT(6) | ||
| 327 | #define ALX_TXQ0_EN BIT(5) | ||
| 328 | #define ALX_TXQ0_SUPT_IPOPT BIT(4) | ||
| 329 | #define ALX_TXQ0_TPD_BURSTPREF_MASK 0xF | ||
| 330 | #define ALX_TXQ0_TPD_BURSTPREF_SHIFT 0 | ||
| 331 | #define ALX_TXQ_TPD_BURSTPREF_DEF 5 | ||
| 332 | |||
| 333 | #define ALX_TXQ1 0x1594 | ||
| 334 | /* bit11: drop large packet, len > (rfd buf) */ | ||
| 335 | #define ALX_TXQ1_ERRLGPKT_DROP_EN BIT(11) | ||
| 336 | #define ALX_TXQ1_JUMBO_TSO_TH (7*1024) | ||
| 337 | |||
| 338 | #define ALX_RXQ0 0x15A0 | ||
| 339 | #define ALX_RXQ0_EN BIT(31) | ||
| 340 | #define ALX_RXQ0_RSS_HASH_EN BIT(29) | ||
| 341 | #define ALX_RXQ0_RSS_MODE_MASK 0x3 | ||
| 342 | #define ALX_RXQ0_RSS_MODE_SHIFT 26 | ||
| 343 | #define ALX_RXQ0_RSS_MODE_DIS 0 | ||
| 344 | #define ALX_RXQ0_RSS_MODE_MQMI 3 | ||
| 345 | #define ALX_RXQ0_NUM_RFD_PREF_MASK 0x3F | ||
| 346 | #define ALX_RXQ0_NUM_RFD_PREF_SHIFT 20 | ||
| 347 | #define ALX_RXQ0_NUM_RFD_PREF_DEF 8 | ||
| 348 | #define ALX_RXQ0_IDT_TBL_SIZE_MASK 0x1FF | ||
| 349 | #define ALX_RXQ0_IDT_TBL_SIZE_SHIFT 8 | ||
| 350 | #define ALX_RXQ0_IDT_TBL_SIZE_DEF 0x100 | ||
| 351 | #define ALX_RXQ0_IDT_TBL_SIZE_NORMAL 128 | ||
| 352 | #define ALX_RXQ0_IPV6_PARSE_EN BIT(7) | ||
| 353 | #define ALX_RXQ0_RSS_HSTYP_MASK 0xF | ||
| 354 | #define ALX_RXQ0_RSS_HSTYP_SHIFT 2 | ||
| 355 | #define ALX_RXQ0_RSS_HSTYP_IPV6_TCP_EN BIT(5) | ||
| 356 | #define ALX_RXQ0_RSS_HSTYP_IPV6_EN BIT(4) | ||
| 357 | #define ALX_RXQ0_RSS_HSTYP_IPV4_TCP_EN BIT(3) | ||
| 358 | #define ALX_RXQ0_RSS_HSTYP_IPV4_EN BIT(2) | ||
| 359 | #define ALX_RXQ0_RSS_HSTYP_ALL (ALX_RXQ0_RSS_HSTYP_IPV6_TCP_EN | \ | ||
| 360 | ALX_RXQ0_RSS_HSTYP_IPV4_TCP_EN | \ | ||
| 361 | ALX_RXQ0_RSS_HSTYP_IPV6_EN | \ | ||
| 362 | ALX_RXQ0_RSS_HSTYP_IPV4_EN) | ||
| 363 | #define ALX_RXQ0_ASPM_THRESH_MASK 0x3 | ||
| 364 | #define ALX_RXQ0_ASPM_THRESH_SHIFT 0 | ||
| 365 | #define ALX_RXQ0_ASPM_THRESH_100M 3 | ||
| 366 | |||
| 367 | #define ALX_RXQ2 0x15A8 | ||
| 368 | #define ALX_RXQ2_RXF_XOFF_THRESH_MASK 0xFFF | ||
| 369 | #define ALX_RXQ2_RXF_XOFF_THRESH_SHIFT 16 | ||
| 370 | #define ALX_RXQ2_RXF_XON_THRESH_MASK 0xFFF | ||
| 371 | #define ALX_RXQ2_RXF_XON_THRESH_SHIFT 0 | ||
| 372 | /* Size = tx-packet(1522) + IPG(12) + SOF(8) + 64(Pause) + IPG(12) + SOF(8) + | ||
| 373 | * rx-packet(1522) + delay-of-link(64) | ||
| 374 | * = 3212. | ||
| 375 | */ | ||
| 376 | #define ALX_RXQ2_RXF_FLOW_CTRL_RSVD 3212 | ||
| 377 | |||
| 378 | #define ALX_DMA 0x15C0 | ||
| 379 | #define ALX_DMA_RCHNL_SEL_MASK 0x3 | ||
| 380 | #define ALX_DMA_RCHNL_SEL_SHIFT 26 | ||
| 381 | #define ALX_DMA_WDLY_CNT_MASK 0xF | ||
| 382 | #define ALX_DMA_WDLY_CNT_SHIFT 16 | ||
| 383 | #define ALX_DMA_WDLY_CNT_DEF 4 | ||
| 384 | #define ALX_DMA_RDLY_CNT_MASK 0x1F | ||
| 385 | #define ALX_DMA_RDLY_CNT_SHIFT 11 | ||
| 386 | #define ALX_DMA_RDLY_CNT_DEF 15 | ||
| 387 | /* bit10: 0:tpd with pri, 1: data */ | ||
| 388 | #define ALX_DMA_RREQ_PRI_DATA BIT(10) | ||
| 389 | #define ALX_DMA_RREQ_BLEN_MASK 0x7 | ||
| 390 | #define ALX_DMA_RREQ_BLEN_SHIFT 4 | ||
| 391 | #define ALX_DMA_RORDER_MODE_MASK 0x7 | ||
| 392 | #define ALX_DMA_RORDER_MODE_SHIFT 0 | ||
| 393 | #define ALX_DMA_RORDER_MODE_OUT 4 | ||
| 394 | |||
| 395 | #define ALX_WOL0 0x14A0 | ||
| 396 | #define ALX_WOL0_PME_LINK BIT(5) | ||
| 397 | #define ALX_WOL0_LINK_EN BIT(4) | ||
| 398 | #define ALX_WOL0_PME_MAGIC_EN BIT(3) | ||
| 399 | #define ALX_WOL0_MAGIC_EN BIT(2) | ||
| 400 | |||
| 401 | #define ALX_RFD_PIDX 0x15E0 | ||
| 402 | |||
| 403 | #define ALX_RFD_CIDX 0x15F8 | ||
| 404 | |||
| 405 | /* MIB */ | ||
| 406 | #define ALX_MIB_BASE 0x1700 | ||
| 407 | #define ALX_MIB_RX_OK (ALX_MIB_BASE + 0) | ||
| 408 | #define ALX_MIB_RX_ERRADDR (ALX_MIB_BASE + 92) | ||
| 409 | #define ALX_MIB_TX_OK (ALX_MIB_BASE + 96) | ||
| 410 | #define ALX_MIB_TX_MCCNT (ALX_MIB_BASE + 192) | ||
| 411 | |||
| 412 | #define ALX_RX_STATS_BIN ALX_MIB_RX_OK | ||
| 413 | #define ALX_RX_STATS_END ALX_MIB_RX_ERRADDR | ||
| 414 | #define ALX_TX_STATS_BIN ALX_MIB_TX_OK | ||
| 415 | #define ALX_TX_STATS_END ALX_MIB_TX_MCCNT | ||
| 416 | |||
| 417 | #define ALX_ISR 0x1600 | ||
| 418 | #define ALX_ISR_DIS BIT(31) | ||
| 419 | #define ALX_ISR_RX_Q7 BIT(30) | ||
| 420 | #define ALX_ISR_RX_Q6 BIT(29) | ||
| 421 | #define ALX_ISR_RX_Q5 BIT(28) | ||
| 422 | #define ALX_ISR_RX_Q4 BIT(27) | ||
| 423 | #define ALX_ISR_PCIE_LNKDOWN BIT(26) | ||
| 424 | #define ALX_ISR_RX_Q3 BIT(19) | ||
| 425 | #define ALX_ISR_RX_Q2 BIT(18) | ||
| 426 | #define ALX_ISR_RX_Q1 BIT(17) | ||
| 427 | #define ALX_ISR_RX_Q0 BIT(16) | ||
| 428 | #define ALX_ISR_TX_Q0 BIT(15) | ||
| 429 | #define ALX_ISR_PHY BIT(12) | ||
| 430 | #define ALX_ISR_DMAW BIT(10) | ||
| 431 | #define ALX_ISR_DMAR BIT(9) | ||
| 432 | #define ALX_ISR_TXF_UR BIT(8) | ||
| 433 | #define ALX_ISR_TX_Q3 BIT(7) | ||
| 434 | #define ALX_ISR_TX_Q2 BIT(6) | ||
| 435 | #define ALX_ISR_TX_Q1 BIT(5) | ||
| 436 | #define ALX_ISR_RFD_UR BIT(4) | ||
| 437 | #define ALX_ISR_RXF_OV BIT(3) | ||
| 438 | #define ALX_ISR_MANU BIT(2) | ||
| 439 | #define ALX_ISR_TIMER BIT(1) | ||
| 440 | #define ALX_ISR_SMB BIT(0) | ||
| 441 | |||
| 442 | #define ALX_IMR 0x1604 | ||
| 443 | |||
| 444 | /* re-send assert msg if SW no response */ | ||
| 445 | #define ALX_INT_RETRIG 0x1608 | ||
| 446 | /* 40ms */ | ||
| 447 | #define ALX_INT_RETRIG_TO 20000 | ||
| 448 | |||
| 449 | #define ALX_SMB_TIMER 0x15C4 | ||
| 450 | |||
| 451 | #define ALX_TINT_TPD_THRSHLD 0x15C8 | ||
| 452 | |||
| 453 | #define ALX_TINT_TIMER 0x15CC | ||
| 454 | |||
| 455 | #define ALX_CLK_GATE 0x1814 | ||
| 456 | #define ALX_CLK_GATE_RXMAC BIT(5) | ||
| 457 | #define ALX_CLK_GATE_TXMAC BIT(4) | ||
| 458 | #define ALX_CLK_GATE_RXQ BIT(3) | ||
| 459 | #define ALX_CLK_GATE_TXQ BIT(2) | ||
| 460 | #define ALX_CLK_GATE_DMAR BIT(1) | ||
| 461 | #define ALX_CLK_GATE_DMAW BIT(0) | ||
| 462 | #define ALX_CLK_GATE_ALL (ALX_CLK_GATE_RXMAC | \ | ||
| 463 | ALX_CLK_GATE_TXMAC | \ | ||
| 464 | ALX_CLK_GATE_RXQ | \ | ||
| 465 | ALX_CLK_GATE_TXQ | \ | ||
| 466 | ALX_CLK_GATE_DMAR | \ | ||
| 467 | ALX_CLK_GATE_DMAW) | ||
| 468 | |||
| 469 | /* interop between drivers */ | ||
| 470 | #define ALX_DRV 0x1804 | ||
| 471 | #define ALX_DRV_PHY_AUTO BIT(28) | ||
| 472 | #define ALX_DRV_PHY_1000 BIT(27) | ||
| 473 | #define ALX_DRV_PHY_100 BIT(26) | ||
| 474 | #define ALX_DRV_PHY_10 BIT(25) | ||
| 475 | #define ALX_DRV_PHY_DUPLEX BIT(24) | ||
| 476 | /* bit23: adv Pause */ | ||
| 477 | #define ALX_DRV_PHY_PAUSE BIT(23) | ||
| 478 | /* bit22: adv Asym Pause */ | ||
| 479 | #define ALX_DRV_PHY_MASK 0xFF | ||
| 480 | #define ALX_DRV_PHY_SHIFT 21 | ||
| 481 | #define ALX_DRV_PHY_UNKNOWN 0 | ||
| 482 | |||
| 483 | /* flag of phy inited */ | ||
| 484 | #define ALX_PHY_INITED 0x003F | ||
| 485 | |||
| 486 | /* reg 1830 ~ 186C for C0+, 16 bit map patterns and wake packet detection */ | ||
| 487 | #define ALX_WOL_CTRL2 0x1830 | ||
| 488 | #define ALX_WOL_CTRL2_DATA_STORE BIT(3) | ||
| 489 | #define ALX_WOL_CTRL2_PTRN_EVT BIT(2) | ||
| 490 | #define ALX_WOL_CTRL2_PME_PTRN_EN BIT(1) | ||
| 491 | #define ALX_WOL_CTRL2_PTRN_EN BIT(0) | ||
| 492 | |||
| 493 | #define ALX_WOL_CTRL3 0x1834 | ||
| 494 | #define ALX_WOL_CTRL3_PTRN_ADDR_MASK 0xFFFFF | ||
| 495 | #define ALX_WOL_CTRL3_PTRN_ADDR_SHIFT 0 | ||
| 496 | |||
| 497 | #define ALX_WOL_CTRL4 0x1838 | ||
| 498 | #define ALX_WOL_CTRL4_PT15_MATCH BIT(31) | ||
| 499 | #define ALX_WOL_CTRL4_PT14_MATCH BIT(30) | ||
| 500 | #define ALX_WOL_CTRL4_PT13_MATCH BIT(29) | ||
| 501 | #define ALX_WOL_CTRL4_PT12_MATCH BIT(28) | ||
| 502 | #define ALX_WOL_CTRL4_PT11_MATCH BIT(27) | ||
| 503 | #define ALX_WOL_CTRL4_PT10_MATCH BIT(26) | ||
| 504 | #define ALX_WOL_CTRL4_PT9_MATCH BIT(25) | ||
| 505 | #define ALX_WOL_CTRL4_PT8_MATCH BIT(24) | ||
| 506 | #define ALX_WOL_CTRL4_PT7_MATCH BIT(23) | ||
| 507 | #define ALX_WOL_CTRL4_PT6_MATCH BIT(22) | ||
| 508 | #define ALX_WOL_CTRL4_PT5_MATCH BIT(21) | ||
| 509 | #define ALX_WOL_CTRL4_PT4_MATCH BIT(20) | ||
| 510 | #define ALX_WOL_CTRL4_PT3_MATCH BIT(19) | ||
| 511 | #define ALX_WOL_CTRL4_PT2_MATCH BIT(18) | ||
| 512 | #define ALX_WOL_CTRL4_PT1_MATCH BIT(17) | ||
| 513 | #define ALX_WOL_CTRL4_PT0_MATCH BIT(16) | ||
| 514 | #define ALX_WOL_CTRL4_PT15_EN BIT(15) | ||
| 515 | #define ALX_WOL_CTRL4_PT14_EN BIT(14) | ||
| 516 | #define ALX_WOL_CTRL4_PT13_EN BIT(13) | ||
| 517 | #define ALX_WOL_CTRL4_PT12_EN BIT(12) | ||
| 518 | #define ALX_WOL_CTRL4_PT11_EN BIT(11) | ||
| 519 | #define ALX_WOL_CTRL4_PT10_EN BIT(10) | ||
| 520 | #define ALX_WOL_CTRL4_PT9_EN BIT(9) | ||
| 521 | #define ALX_WOL_CTRL4_PT8_EN BIT(8) | ||
| 522 | #define ALX_WOL_CTRL4_PT7_EN BIT(7) | ||
| 523 | #define ALX_WOL_CTRL4_PT6_EN BIT(6) | ||
| 524 | #define ALX_WOL_CTRL4_PT5_EN BIT(5) | ||
| 525 | #define ALX_WOL_CTRL4_PT4_EN BIT(4) | ||
| 526 | #define ALX_WOL_CTRL4_PT3_EN BIT(3) | ||
| 527 | #define ALX_WOL_CTRL4_PT2_EN BIT(2) | ||
| 528 | #define ALX_WOL_CTRL4_PT1_EN BIT(1) | ||
| 529 | #define ALX_WOL_CTRL4_PT0_EN BIT(0) | ||
| 530 | |||
| 531 | #define ALX_WOL_CTRL5 0x183C | ||
| 532 | #define ALX_WOL_CTRL5_PT3_LEN_MASK 0xFF | ||
| 533 | #define ALX_WOL_CTRL5_PT3_LEN_SHIFT 24 | ||
| 534 | #define ALX_WOL_CTRL5_PT2_LEN_MASK 0xFF | ||
| 535 | #define ALX_WOL_CTRL5_PT2_LEN_SHIFT 16 | ||
| 536 | #define ALX_WOL_CTRL5_PT1_LEN_MASK 0xFF | ||
| 537 | #define ALX_WOL_CTRL5_PT1_LEN_SHIFT 8 | ||
| 538 | #define ALX_WOL_CTRL5_PT0_LEN_MASK 0xFF | ||
| 539 | #define ALX_WOL_CTRL5_PT0_LEN_SHIFT 0 | ||
| 540 | |||
| 541 | #define ALX_WOL_CTRL6 0x1840 | ||
| 542 | #define ALX_WOL_CTRL5_PT7_LEN_MASK 0xFF | ||
| 543 | #define ALX_WOL_CTRL5_PT7_LEN_SHIFT 24 | ||
| 544 | #define ALX_WOL_CTRL5_PT6_LEN_MASK 0xFF | ||
| 545 | #define ALX_WOL_CTRL5_PT6_LEN_SHIFT 16 | ||
| 546 | #define ALX_WOL_CTRL5_PT5_LEN_MASK 0xFF | ||
| 547 | #define ALX_WOL_CTRL5_PT5_LEN_SHIFT 8 | ||
| 548 | #define ALX_WOL_CTRL5_PT4_LEN_MASK 0xFF | ||
| 549 | #define ALX_WOL_CTRL5_PT4_LEN_SHIFT 0 | ||
| 550 | |||
| 551 | #define ALX_WOL_CTRL7 0x1844 | ||
| 552 | #define ALX_WOL_CTRL5_PT11_LEN_MASK 0xFF | ||
| 553 | #define ALX_WOL_CTRL5_PT11_LEN_SHIFT 24 | ||
| 554 | #define ALX_WOL_CTRL5_PT10_LEN_MASK 0xFF | ||
| 555 | #define ALX_WOL_CTRL5_PT10_LEN_SHIFT 16 | ||
| 556 | #define ALX_WOL_CTRL5_PT9_LEN_MASK 0xFF | ||
| 557 | #define ALX_WOL_CTRL5_PT9_LEN_SHIFT 8 | ||
| 558 | #define ALX_WOL_CTRL5_PT8_LEN_MASK 0xFF | ||
| 559 | #define ALX_WOL_CTRL5_PT8_LEN_SHIFT 0 | ||
| 560 | |||
| 561 | #define ALX_WOL_CTRL8 0x1848 | ||
| 562 | #define ALX_WOL_CTRL5_PT15_LEN_MASK 0xFF | ||
| 563 | #define ALX_WOL_CTRL5_PT15_LEN_SHIFT 24 | ||
| 564 | #define ALX_WOL_CTRL5_PT14_LEN_MASK 0xFF | ||
| 565 | #define ALX_WOL_CTRL5_PT14_LEN_SHIFT 16 | ||
| 566 | #define ALX_WOL_CTRL5_PT13_LEN_MASK 0xFF | ||
| 567 | #define ALX_WOL_CTRL5_PT13_LEN_SHIFT 8 | ||
| 568 | #define ALX_WOL_CTRL5_PT12_LEN_MASK 0xFF | ||
| 569 | #define ALX_WOL_CTRL5_PT12_LEN_SHIFT 0 | ||
| 570 | |||
| 571 | #define ALX_ACER_FIXED_PTN0 0x1850 | ||
| 572 | #define ALX_ACER_FIXED_PTN0_MASK 0xFFFFFFFF | ||
| 573 | #define ALX_ACER_FIXED_PTN0_SHIFT 0 | ||
| 574 | |||
| 575 | #define ALX_ACER_FIXED_PTN1 0x1854 | ||
| 576 | #define ALX_ACER_FIXED_PTN1_MASK 0xFFFF | ||
| 577 | #define ALX_ACER_FIXED_PTN1_SHIFT 0 | ||
| 578 | |||
| 579 | #define ALX_ACER_RANDOM_NUM0 0x1858 | ||
| 580 | #define ALX_ACER_RANDOM_NUM0_MASK 0xFFFFFFFF | ||
| 581 | #define ALX_ACER_RANDOM_NUM0_SHIFT 0 | ||
| 582 | |||
| 583 | #define ALX_ACER_RANDOM_NUM1 0x185C | ||
| 584 | #define ALX_ACER_RANDOM_NUM1_MASK 0xFFFFFFFF | ||
| 585 | #define ALX_ACER_RANDOM_NUM1_SHIFT 0 | ||
| 586 | |||
| 587 | #define ALX_ACER_RANDOM_NUM2 0x1860 | ||
| 588 | #define ALX_ACER_RANDOM_NUM2_MASK 0xFFFFFFFF | ||
| 589 | #define ALX_ACER_RANDOM_NUM2_SHIFT 0 | ||
| 590 | |||
| 591 | #define ALX_ACER_RANDOM_NUM3 0x1864 | ||
| 592 | #define ALX_ACER_RANDOM_NUM3_MASK 0xFFFFFFFF | ||
| 593 | #define ALX_ACER_RANDOM_NUM3_SHIFT 0 | ||
| 594 | |||
| 595 | #define ALX_ACER_MAGIC 0x1868 | ||
| 596 | #define ALX_ACER_MAGIC_EN BIT(31) | ||
| 597 | #define ALX_ACER_MAGIC_PME_EN BIT(30) | ||
| 598 | #define ALX_ACER_MAGIC_MATCH BIT(29) | ||
| 599 | #define ALX_ACER_MAGIC_FF_CHECK BIT(10) | ||
| 600 | #define ALX_ACER_MAGIC_RAN_LEN_MASK 0x1F | ||
| 601 | #define ALX_ACER_MAGIC_RAN_LEN_SHIFT 5 | ||
| 602 | #define ALX_ACER_MAGIC_FIX_LEN_MASK 0x1F | ||
| 603 | #define ALX_ACER_MAGIC_FIX_LEN_SHIFT 0 | ||
| 604 | |||
| 605 | #define ALX_ACER_TIMER 0x186C | ||
| 606 | #define ALX_ACER_TIMER_EN BIT(31) | ||
| 607 | #define ALX_ACER_TIMER_PME_EN BIT(30) | ||
| 608 | #define ALX_ACER_TIMER_MATCH BIT(29) | ||
| 609 | #define ALX_ACER_TIMER_THRES_MASK 0x1FFFF | ||
| 610 | #define ALX_ACER_TIMER_THRES_SHIFT 0 | ||
| 611 | #define ALX_ACER_TIMER_THRES_DEF 1 | ||
| 612 | |||
| 613 | /* RSS definitions */ | ||
| 614 | #define ALX_RSS_KEY0 0x14B0 | ||
| 615 | #define ALX_RSS_KEY1 0x14B4 | ||
| 616 | #define ALX_RSS_KEY2 0x14B8 | ||
| 617 | #define ALX_RSS_KEY3 0x14BC | ||
| 618 | #define ALX_RSS_KEY4 0x14C0 | ||
| 619 | #define ALX_RSS_KEY5 0x14C4 | ||
| 620 | #define ALX_RSS_KEY6 0x14C8 | ||
| 621 | #define ALX_RSS_KEY7 0x14CC | ||
| 622 | #define ALX_RSS_KEY8 0x14D0 | ||
| 623 | #define ALX_RSS_KEY9 0x14D4 | ||
| 624 | |||
| 625 | #define ALX_RSS_IDT_TBL0 0x1B00 | ||
| 626 | |||
| 627 | #define ALX_MSI_MAP_TBL1 0x15D0 | ||
| 628 | #define ALX_MSI_MAP_TBL1_TXQ1_SHIFT 20 | ||
| 629 | #define ALX_MSI_MAP_TBL1_TXQ0_SHIFT 16 | ||
| 630 | #define ALX_MSI_MAP_TBL1_RXQ3_SHIFT 12 | ||
| 631 | #define ALX_MSI_MAP_TBL1_RXQ2_SHIFT 8 | ||
| 632 | #define ALX_MSI_MAP_TBL1_RXQ1_SHIFT 4 | ||
| 633 | #define ALX_MSI_MAP_TBL1_RXQ0_SHIFT 0 | ||
| 634 | |||
| 635 | #define ALX_MSI_MAP_TBL2 0x15D8 | ||
| 636 | #define ALX_MSI_MAP_TBL2_TXQ3_SHIFT 20 | ||
| 637 | #define ALX_MSI_MAP_TBL2_TXQ2_SHIFT 16 | ||
| 638 | #define ALX_MSI_MAP_TBL2_RXQ7_SHIFT 12 | ||
| 639 | #define ALX_MSI_MAP_TBL2_RXQ6_SHIFT 8 | ||
| 640 | #define ALX_MSI_MAP_TBL2_RXQ5_SHIFT 4 | ||
| 641 | #define ALX_MSI_MAP_TBL2_RXQ4_SHIFT 0 | ||
| 642 | |||
| 643 | #define ALX_MSI_ID_MAP 0x15D4 | ||
| 644 | |||
| 645 | #define ALX_MSI_RETRANS_TIMER 0x1920 | ||
| 646 | /* bit16: 1:line,0:standard */ | ||
| 647 | #define ALX_MSI_MASK_SEL_LINE BIT(16) | ||
| 648 | #define ALX_MSI_RETRANS_TM_MASK 0xFFFF | ||
| 649 | #define ALX_MSI_RETRANS_TM_SHIFT 0 | ||
| 650 | |||
| 651 | /* CR DMA ctrl */ | ||
| 652 | |||
| 653 | /* TX QoS */ | ||
| 654 | #define ALX_WRR 0x1938 | ||
| 655 | #define ALX_WRR_PRI_MASK 0x3 | ||
| 656 | #define ALX_WRR_PRI_SHIFT 29 | ||
| 657 | #define ALX_WRR_PRI_RESTRICT_NONE 3 | ||
| 658 | #define ALX_WRR_PRI3_MASK 0x1F | ||
| 659 | #define ALX_WRR_PRI3_SHIFT 24 | ||
| 660 | #define ALX_WRR_PRI2_MASK 0x1F | ||
| 661 | #define ALX_WRR_PRI2_SHIFT 16 | ||
| 662 | #define ALX_WRR_PRI1_MASK 0x1F | ||
| 663 | #define ALX_WRR_PRI1_SHIFT 8 | ||
| 664 | #define ALX_WRR_PRI0_MASK 0x1F | ||
| 665 | #define ALX_WRR_PRI0_SHIFT 0 | ||
| 666 | |||
| 667 | #define ALX_HQTPD 0x193C | ||
| 668 | #define ALX_HQTPD_BURST_EN BIT(31) | ||
| 669 | #define ALX_HQTPD_Q3_NUMPREF_MASK 0xF | ||
| 670 | #define ALX_HQTPD_Q3_NUMPREF_SHIFT 8 | ||
| 671 | #define ALX_HQTPD_Q2_NUMPREF_MASK 0xF | ||
| 672 | #define ALX_HQTPD_Q2_NUMPREF_SHIFT 4 | ||
| 673 | #define ALX_HQTPD_Q1_NUMPREF_MASK 0xF | ||
| 674 | #define ALX_HQTPD_Q1_NUMPREF_SHIFT 0 | ||
| 675 | |||
| 676 | #define ALX_MISC 0x19C0 | ||
| 677 | #define ALX_MISC_PSW_OCP_MASK 0x7 | ||
| 678 | #define ALX_MISC_PSW_OCP_SHIFT 21 | ||
| 679 | #define ALX_MISC_PSW_OCP_DEF 0x7 | ||
| 680 | #define ALX_MISC_ISO_EN BIT(12) | ||
| 681 | #define ALX_MISC_INTNLOSC_OPEN BIT(3) | ||
| 682 | |||
| 683 | #define ALX_MSIC2 0x19C8 | ||
| 684 | #define ALX_MSIC2_CALB_START BIT(0) | ||
| 685 | |||
| 686 | #define ALX_MISC3 0x19CC | ||
| 687 | /* bit1: 1:Software control 25M */ | ||
| 688 | #define ALX_MISC3_25M_BY_SW BIT(1) | ||
| 689 | /* bit0: 25M switch to intnl OSC */ | ||
| 690 | #define ALX_MISC3_25M_NOTO_INTNL BIT(0) | ||
| 691 | |||
| 692 | /* MSIX tbl in memory space */ | ||
| 693 | #define ALX_MSIX_ENTRY_BASE 0x2000 | ||
| 694 | |||
| 695 | /********************* PHY regs definition ***************************/ | ||
| 696 | |||
| 697 | /* PHY Specific Status Register */ | ||
| 698 | #define ALX_MII_GIGA_PSSR 0x11 | ||
| 699 | #define ALX_GIGA_PSSR_SPD_DPLX_RESOLVED 0x0800 | ||
| 700 | #define ALX_GIGA_PSSR_DPLX 0x2000 | ||
| 701 | #define ALX_GIGA_PSSR_SPEED 0xC000 | ||
| 702 | #define ALX_GIGA_PSSR_10MBS 0x0000 | ||
| 703 | #define ALX_GIGA_PSSR_100MBS 0x4000 | ||
| 704 | #define ALX_GIGA_PSSR_1000MBS 0x8000 | ||
| 705 | |||
| 706 | /* PHY Interrupt Enable Register */ | ||
| 707 | #define ALX_MII_IER 0x12 | ||
| 708 | #define ALX_IER_LINK_UP 0x0400 | ||
| 709 | #define ALX_IER_LINK_DOWN 0x0800 | ||
| 710 | |||
| 711 | /* PHY Interrupt Status Register */ | ||
| 712 | #define ALX_MII_ISR 0x13 | ||
| 713 | |||
| 714 | #define ALX_MII_DBG_ADDR 0x1D | ||
| 715 | #define ALX_MII_DBG_DATA 0x1E | ||
| 716 | |||
| 717 | /***************************** debug port *************************************/ | ||
| 718 | |||
| 719 | #define ALX_MIIDBG_ANACTRL 0x00 | ||
| 720 | #define ALX_ANACTRL_DEF 0x02EF | ||
| 721 | |||
| 722 | #define ALX_MIIDBG_SYSMODCTRL 0x04 | ||
| 723 | /* en half bias */ | ||
| 724 | #define ALX_SYSMODCTRL_IECHOADJ_DEF 0xBB8B | ||
| 725 | |||
| 726 | #define ALX_MIIDBG_SRDSYSMOD 0x05 | ||
| 727 | #define ALX_SRDSYSMOD_DEEMP_EN 0x0040 | ||
| 728 | #define ALX_SRDSYSMOD_DEF 0x2C46 | ||
| 729 | |||
| 730 | #define ALX_MIIDBG_HIBNEG 0x0B | ||
| 731 | #define ALX_HIBNEG_PSHIB_EN 0x8000 | ||
| 732 | #define ALX_HIBNEG_HIB_PSE 0x1000 | ||
| 733 | #define ALX_HIBNEG_DEF 0xBC40 | ||
| 734 | #define ALX_HIBNEG_NOHIB (ALX_HIBNEG_DEF & \ | ||
| 735 | ~(ALX_HIBNEG_PSHIB_EN | ALX_HIBNEG_HIB_PSE)) | ||
| 736 | |||
| 737 | #define ALX_MIIDBG_TST10BTCFG 0x12 | ||
| 738 | #define ALX_TST10BTCFG_DEF 0x4C04 | ||
| 739 | |||
| 740 | #define ALX_MIIDBG_AZ_ANADECT 0x15 | ||
| 741 | #define ALX_AZ_ANADECT_DEF 0x3220 | ||
| 742 | #define ALX_AZ_ANADECT_LONG 0x3210 | ||
| 743 | |||
| 744 | #define ALX_MIIDBG_MSE16DB 0x18 | ||
| 745 | #define ALX_MSE16DB_UP 0x05EA | ||
| 746 | #define ALX_MSE16DB_DOWN 0x02EA | ||
| 747 | |||
| 748 | #define ALX_MIIDBG_MSE20DB 0x1C | ||
| 749 | #define ALX_MSE20DB_TH_MASK 0x7F | ||
| 750 | #define ALX_MSE20DB_TH_SHIFT 2 | ||
| 751 | #define ALX_MSE20DB_TH_DEF 0x2E | ||
| 752 | #define ALX_MSE20DB_TH_HI 0x54 | ||
| 753 | |||
| 754 | #define ALX_MIIDBG_AGC 0x23 | ||
| 755 | #define ALX_AGC_2_VGA_MASK 0x3FU | ||
| 756 | #define ALX_AGC_2_VGA_SHIFT 8 | ||
| 757 | #define ALX_AGC_LONG1G_LIMT 40 | ||
| 758 | #define ALX_AGC_LONG100M_LIMT 44 | ||
| 759 | |||
| 760 | #define ALX_MIIDBG_LEGCYPS 0x29 | ||
| 761 | #define ALX_LEGCYPS_EN 0x8000 | ||
| 762 | #define ALX_LEGCYPS_DEF 0x129D | ||
| 763 | |||
| 764 | #define ALX_MIIDBG_TST100BTCFG 0x36 | ||
| 765 | #define ALX_TST100BTCFG_DEF 0xE12C | ||
| 766 | |||
| 767 | #define ALX_MIIDBG_GREENCFG 0x3B | ||
| 768 | #define ALX_GREENCFG_DEF 0x7078 | ||
| 769 | |||
| 770 | #define ALX_MIIDBG_GREENCFG2 0x3D | ||
| 771 | #define ALX_GREENCFG2_BP_GREEN 0x8000 | ||
| 772 | #define ALX_GREENCFG2_GATE_DFSE_EN 0x0080 | ||
| 773 | |||
| 774 | /******* dev 3 *********/ | ||
| 775 | #define ALX_MIIEXT_PCS 3 | ||
| 776 | |||
| 777 | #define ALX_MIIEXT_CLDCTRL3 0x8003 | ||
| 778 | #define ALX_CLDCTRL3_BP_CABLE1TH_DET_GT 0x8000 | ||
| 779 | |||
| 780 | #define ALX_MIIEXT_CLDCTRL5 0x8005 | ||
| 781 | #define ALX_CLDCTRL5_BP_VD_HLFBIAS 0x4000 | ||
| 782 | |||
| 783 | #define ALX_MIIEXT_CLDCTRL6 0x8006 | ||
| 784 | #define ALX_CLDCTRL6_CAB_LEN_MASK 0xFF | ||
| 785 | #define ALX_CLDCTRL6_CAB_LEN_SHIFT 0 | ||
| 786 | #define ALX_CLDCTRL6_CAB_LEN_SHORT1G 116 | ||
| 787 | #define ALX_CLDCTRL6_CAB_LEN_SHORT100M 152 | ||
| 788 | |||
| 789 | #define ALX_MIIEXT_VDRVBIAS 0x8062 | ||
| 790 | #define ALX_VDRVBIAS_DEF 0x3 | ||
| 791 | |||
| 792 | /********* dev 7 **********/ | ||
| 793 | #define ALX_MIIEXT_ANEG 7 | ||
| 794 | |||
| 795 | #define ALX_MIIEXT_LOCAL_EEEADV 0x3C | ||
| 796 | #define ALX_LOCAL_EEEADV_1000BT 0x0004 | ||
| 797 | #define ALX_LOCAL_EEEADV_100BT 0x0002 | ||
| 798 | |||
| 799 | #define ALX_MIIEXT_AFE 0x801A | ||
| 800 | #define ALX_AFE_10BT_100M_TH 0x0040 | ||
| 801 | |||
| 802 | #define ALX_MIIEXT_S3DIG10 0x8023 | ||
| 803 | /* bit0: 1:bypass 10BT rx fifo, 0:original 10BT rx */ | ||
| 804 | #define ALX_MIIEXT_S3DIG10_SL 0x0001 | ||
| 805 | #define ALX_MIIEXT_S3DIG10_DEF 0 | ||
| 806 | |||
| 807 | #define ALX_MIIEXT_NLP78 0x8027 | ||
| 808 | #define ALX_MIIEXT_NLP78_120M_DEF 0x8A05 | ||
| 809 | |||
| 810 | #endif | ||