aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/ethernet/amd/xgbe/xgbe-pci.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/net/ethernet/amd/xgbe/xgbe-pci.c')
-rw-r--r--drivers/net/ethernet/amd/xgbe/xgbe-pci.c36
1 files changed, 27 insertions, 9 deletions
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-pci.c b/drivers/net/ethernet/amd/xgbe/xgbe-pci.c
index 82d1f416ee2a..7b86240ecd5f 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-pci.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-pci.c
@@ -335,16 +335,33 @@ static int xgbe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
335 pdata->awcr = XGBE_DMA_PCI_AWCR; 335 pdata->awcr = XGBE_DMA_PCI_AWCR;
336 pdata->awarcr = XGBE_DMA_PCI_AWARCR; 336 pdata->awarcr = XGBE_DMA_PCI_AWARCR;
337 337
338 /* Read the port property registers */
339 pdata->pp0 = XP_IOREAD(pdata, XP_PROP_0);
340 pdata->pp1 = XP_IOREAD(pdata, XP_PROP_1);
341 pdata->pp2 = XP_IOREAD(pdata, XP_PROP_2);
342 pdata->pp3 = XP_IOREAD(pdata, XP_PROP_3);
343 pdata->pp4 = XP_IOREAD(pdata, XP_PROP_4);
344 if (netif_msg_probe(pdata)) {
345 dev_dbg(dev, "port property 0 = %#010x\n", pdata->pp0);
346 dev_dbg(dev, "port property 1 = %#010x\n", pdata->pp1);
347 dev_dbg(dev, "port property 2 = %#010x\n", pdata->pp2);
348 dev_dbg(dev, "port property 3 = %#010x\n", pdata->pp3);
349 dev_dbg(dev, "port property 4 = %#010x\n", pdata->pp4);
350 }
351
338 /* Set the maximum channels and queues */ 352 /* Set the maximum channels and queues */
339 reg = XP_IOREAD(pdata, XP_PROP_1); 353 pdata->tx_max_channel_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
340 pdata->tx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_DMA); 354 MAX_TX_DMA);
341 pdata->rx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_DMA); 355 pdata->rx_max_channel_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
342 pdata->tx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_QUEUES); 356 MAX_RX_DMA);
343 pdata->rx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_QUEUES); 357 pdata->tx_max_q_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
358 MAX_TX_QUEUES);
359 pdata->rx_max_q_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
360 MAX_RX_QUEUES);
344 if (netif_msg_probe(pdata)) { 361 if (netif_msg_probe(pdata)) {
345 dev_dbg(dev, "max tx/rx channel count = %u/%u\n", 362 dev_dbg(dev, "max tx/rx channel count = %u/%u\n",
346 pdata->tx_max_channel_count, 363 pdata->tx_max_channel_count,
347 pdata->tx_max_channel_count); 364 pdata->rx_max_channel_count);
348 dev_dbg(dev, "max tx/rx hw queue count = %u/%u\n", 365 dev_dbg(dev, "max tx/rx hw queue count = %u/%u\n",
349 pdata->tx_max_q_count, pdata->rx_max_q_count); 366 pdata->tx_max_q_count, pdata->rx_max_q_count);
350 } 367 }
@@ -353,12 +370,13 @@ static int xgbe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
353 xgbe_set_counts(pdata); 370 xgbe_set_counts(pdata);
354 371
355 /* Set the maximum fifo amounts */ 372 /* Set the maximum fifo amounts */
356 reg = XP_IOREAD(pdata, XP_PROP_2); 373 pdata->tx_max_fifo_size = XP_GET_BITS(pdata->pp2, XP_PROP_2,
357 pdata->tx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, TX_FIFO_SIZE); 374 TX_FIFO_SIZE);
358 pdata->tx_max_fifo_size *= 16384; 375 pdata->tx_max_fifo_size *= 16384;
359 pdata->tx_max_fifo_size = min(pdata->tx_max_fifo_size, 376 pdata->tx_max_fifo_size = min(pdata->tx_max_fifo_size,
360 pdata->vdata->tx_max_fifo_size); 377 pdata->vdata->tx_max_fifo_size);
361 pdata->rx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, RX_FIFO_SIZE); 378 pdata->rx_max_fifo_size = XP_GET_BITS(pdata->pp2, XP_PROP_2,
379 RX_FIFO_SIZE);
362 pdata->rx_max_fifo_size *= 16384; 380 pdata->rx_max_fifo_size *= 16384;
363 pdata->rx_max_fifo_size = min(pdata->rx_max_fifo_size, 381 pdata->rx_max_fifo_size = min(pdata->rx_max_fifo_size,
364 pdata->vdata->rx_max_fifo_size); 382 pdata->vdata->rx_max_fifo_size);