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-rw-r--r--drivers/net/dsa/mv88e6060.c114
-rw-r--r--drivers/net/dsa/mv88e6060.h111
2 files changed, 149 insertions, 76 deletions
diff --git a/drivers/net/dsa/mv88e6060.c b/drivers/net/dsa/mv88e6060.c
index 9093577755f6..0527f485c3dc 100644
--- a/drivers/net/dsa/mv88e6060.c
+++ b/drivers/net/dsa/mv88e6060.c
@@ -15,9 +15,7 @@
15#include <linux/netdevice.h> 15#include <linux/netdevice.h>
16#include <linux/phy.h> 16#include <linux/phy.h>
17#include <net/dsa.h> 17#include <net/dsa.h>
18 18#include "mv88e6060.h"
19#define REG_PORT(p) (8 + (p))
20#define REG_GLOBAL 0x0f
21 19
22static int reg_read(struct dsa_switch *ds, int addr, int reg) 20static int reg_read(struct dsa_switch *ds, int addr, int reg)
23{ 21{
@@ -67,13 +65,14 @@ static char *mv88e6060_probe(struct device *host_dev, int sw_addr)
67 if (bus == NULL) 65 if (bus == NULL)
68 return NULL; 66 return NULL;
69 67
70 ret = mdiobus_read(bus, sw_addr + REG_PORT(0), 0x03); 68 ret = mdiobus_read(bus, sw_addr + REG_PORT(0), PORT_SWITCH_ID);
71 if (ret >= 0) { 69 if (ret >= 0) {
72 if (ret == 0x0600) 70 if (ret == PORT_SWITCH_ID_6060)
73 return "Marvell 88E6060 (A0)"; 71 return "Marvell 88E6060 (A0)";
74 if (ret == 0x0601 || ret == 0x0602) 72 if (ret == PORT_SWITCH_ID_6060_R1 ||
73 ret == PORT_SWITCH_ID_6060_R2)
75 return "Marvell 88E6060 (B0)"; 74 return "Marvell 88E6060 (B0)";
76 if ((ret & 0xfff0) == 0x0600) 75 if ((ret & PORT_SWITCH_ID_6060_MASK) == PORT_SWITCH_ID_6060)
77 return "Marvell 88E6060"; 76 return "Marvell 88E6060";
78 } 77 }
79 78
@@ -87,22 +86,26 @@ static int mv88e6060_switch_reset(struct dsa_switch *ds)
87 unsigned long timeout; 86 unsigned long timeout;
88 87
89 /* Set all ports to the disabled state. */ 88 /* Set all ports to the disabled state. */
90 for (i = 0; i < 6; i++) { 89 for (i = 0; i < MV88E6060_PORTS; i++) {
91 ret = REG_READ(REG_PORT(i), 0x04); 90 ret = REG_READ(REG_PORT(i), PORT_CONTROL);
92 REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc); 91 REG_WRITE(REG_PORT(i), PORT_CONTROL,
92 ret & ~PORT_CONTROL_STATE_MASK);
93 } 93 }
94 94
95 /* Wait for transmit queues to drain. */ 95 /* Wait for transmit queues to drain. */
96 usleep_range(2000, 4000); 96 usleep_range(2000, 4000);
97 97
98 /* Reset the switch. */ 98 /* Reset the switch. */
99 REG_WRITE(REG_GLOBAL, 0x0a, 0xa130); 99 REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
100 GLOBAL_ATU_CONTROL_SWRESET |
101 GLOBAL_ATU_CONTROL_ATUSIZE_1024 |
102 GLOBAL_ATU_CONTROL_ATE_AGE_5MIN);
100 103
101 /* Wait up to one second for reset to complete. */ 104 /* Wait up to one second for reset to complete. */
102 timeout = jiffies + 1 * HZ; 105 timeout = jiffies + 1 * HZ;
103 while (time_before(jiffies, timeout)) { 106 while (time_before(jiffies, timeout)) {
104 ret = REG_READ(REG_GLOBAL, 0x00); 107 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
105 if ((ret & 0x8000) == 0x0000) 108 if (ret & GLOBAL_STATUS_INIT_READY)
106 break; 109 break;
107 110
108 usleep_range(1000, 2000); 111 usleep_range(1000, 2000);
@@ -119,13 +122,15 @@ static int mv88e6060_setup_global(struct dsa_switch *ds)
119 * set the maximum frame size to 1536 bytes, and mask all 122 * set the maximum frame size to 1536 bytes, and mask all
120 * interrupt sources. 123 * interrupt sources.
121 */ 124 */
122 REG_WRITE(REG_GLOBAL, 0x04, 0x0800); 125 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, GLOBAL_CONTROL_MAX_FRAME_1536);
123 126
124 /* Enable automatic address learning, set the address 127 /* Enable automatic address learning, set the address
125 * database size to 1024 entries, and set the default aging 128 * database size to 1024 entries, and set the default aging
126 * time to 5 minutes. 129 * time to 5 minutes.
127 */ 130 */
128 REG_WRITE(REG_GLOBAL, 0x0a, 0x2130); 131 REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
132 GLOBAL_ATU_CONTROL_ATUSIZE_1024 |
133 GLOBAL_ATU_CONTROL_ATE_AGE_5MIN);
129 134
130 return 0; 135 return 0;
131} 136}
@@ -139,25 +144,30 @@ static int mv88e6060_setup_port(struct dsa_switch *ds, int p)
139 * state to Forwarding. Additionally, if this is the CPU 144 * state to Forwarding. Additionally, if this is the CPU
140 * port, enable Ingress and Egress Trailer tagging mode. 145 * port, enable Ingress and Egress Trailer tagging mode.
141 */ 146 */
142 REG_WRITE(addr, 0x04, dsa_is_cpu_port(ds, p) ? 0x4103 : 0x0003); 147 REG_WRITE(addr, PORT_CONTROL,
148 dsa_is_cpu_port(ds, p) ?
149 PORT_CONTROL_TRAILER |
150 PORT_CONTROL_INGRESS_MODE |
151 PORT_CONTROL_STATE_FORWARDING :
152 PORT_CONTROL_STATE_FORWARDING);
143 153
144 /* Port based VLAN map: give each port its own address 154 /* Port based VLAN map: give each port its own address
145 * database, allow the CPU port to talk to each of the 'real' 155 * database, allow the CPU port to talk to each of the 'real'
146 * ports, and allow each of the 'real' ports to only talk to 156 * ports, and allow each of the 'real' ports to only talk to
147 * the CPU port. 157 * the CPU port.
148 */ 158 */
149 REG_WRITE(addr, 0x06, 159 REG_WRITE(addr, PORT_VLAN_MAP,
150 ((p & 0xf) << 12) | 160 ((p & 0xf) << PORT_VLAN_MAP_DBNUM_SHIFT) |
151 (dsa_is_cpu_port(ds, p) ? 161 (dsa_is_cpu_port(ds, p) ?
152 ds->phys_port_mask : 162 ds->phys_port_mask :
153 (1 << ds->dst->cpu_port))); 163 BIT(ds->dst->cpu_port)));
154 164
155 /* Port Association Vector: when learning source addresses 165 /* Port Association Vector: when learning source addresses
156 * of packets, add the address to the address database using 166 * of packets, add the address to the address database using
157 * a port bitmap that has only the bit for this port set and 167 * a port bitmap that has only the bit for this port set and
158 * the other bits clear. 168 * the other bits clear.
159 */ 169 */
160 REG_WRITE(addr, 0x0b, 1 << p); 170 REG_WRITE(addr, PORT_ASSOC_VECTOR, BIT(p));
161 171
162 return 0; 172 return 0;
163} 173}
@@ -177,7 +187,7 @@ static int mv88e6060_setup(struct dsa_switch *ds)
177 if (ret < 0) 187 if (ret < 0)
178 return ret; 188 return ret;
179 189
180 for (i = 0; i < 6; i++) { 190 for (i = 0; i < MV88E6060_PORTS; i++) {
181 ret = mv88e6060_setup_port(ds, i); 191 ret = mv88e6060_setup_port(ds, i);
182 if (ret < 0) 192 if (ret < 0)
183 return ret; 193 return ret;
@@ -188,16 +198,17 @@ static int mv88e6060_setup(struct dsa_switch *ds)
188 198
189static int mv88e6060_set_addr(struct dsa_switch *ds, u8 *addr) 199static int mv88e6060_set_addr(struct dsa_switch *ds, u8 *addr)
190{ 200{
191 REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) | addr[1]); 201 /* Use the same MAC Address as FD Pause frames for all ports */
192 REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) | addr[3]); 202 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 9) | addr[1]);
193 REG_WRITE(REG_GLOBAL, 0x03, (addr[4] << 8) | addr[5]); 203 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
204 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
194 205
195 return 0; 206 return 0;
196} 207}
197 208
198static int mv88e6060_port_to_phy_addr(int port) 209static int mv88e6060_port_to_phy_addr(int port)
199{ 210{
200 if (port >= 0 && port <= 5) 211 if (port >= 0 && port < MV88E6060_PORTS)
201 return port; 212 return port;
202 return -1; 213 return -1;
203} 214}
@@ -225,54 +236,6 @@ mv88e6060_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
225 return reg_write(ds, addr, regnum, val); 236 return reg_write(ds, addr, regnum, val);
226} 237}
227 238
228static void mv88e6060_poll_link(struct dsa_switch *ds)
229{
230 int i;
231
232 for (i = 0; i < DSA_MAX_PORTS; i++) {
233 struct net_device *dev;
234 int uninitialized_var(port_status);
235 int link;
236 int speed;
237 int duplex;
238 int fc;
239
240 dev = ds->ports[i];
241 if (dev == NULL)
242 continue;
243
244 link = 0;
245 if (dev->flags & IFF_UP) {
246 port_status = reg_read(ds, REG_PORT(i), 0x00);
247 if (port_status < 0)
248 continue;
249
250 link = !!(port_status & 0x1000);
251 }
252
253 if (!link) {
254 if (netif_carrier_ok(dev)) {
255 netdev_info(dev, "link down\n");
256 netif_carrier_off(dev);
257 }
258 continue;
259 }
260
261 speed = (port_status & 0x0100) ? 100 : 10;
262 duplex = (port_status & 0x0200) ? 1 : 0;
263 fc = ((port_status & 0xc000) == 0xc000) ? 1 : 0;
264
265 if (!netif_carrier_ok(dev)) {
266 netdev_info(dev,
267 "link up, %d Mb/s, %s duplex, flow control %sabled\n",
268 speed,
269 duplex ? "full" : "half",
270 fc ? "en" : "dis");
271 netif_carrier_on(dev);
272 }
273 }
274}
275
276static struct dsa_switch_driver mv88e6060_switch_driver = { 239static struct dsa_switch_driver mv88e6060_switch_driver = {
277 .tag_protocol = DSA_TAG_PROTO_TRAILER, 240 .tag_protocol = DSA_TAG_PROTO_TRAILER,
278 .probe = mv88e6060_probe, 241 .probe = mv88e6060_probe,
@@ -280,7 +243,6 @@ static struct dsa_switch_driver mv88e6060_switch_driver = {
280 .set_addr = mv88e6060_set_addr, 243 .set_addr = mv88e6060_set_addr,
281 .phy_read = mv88e6060_phy_read, 244 .phy_read = mv88e6060_phy_read,
282 .phy_write = mv88e6060_phy_write, 245 .phy_write = mv88e6060_phy_write,
283 .poll_link = mv88e6060_poll_link,
284}; 246};
285 247
286static int __init mv88e6060_init(void) 248static int __init mv88e6060_init(void)
diff --git a/drivers/net/dsa/mv88e6060.h b/drivers/net/dsa/mv88e6060.h
new file mode 100644
index 000000000000..cc9b2ed4aff4
--- /dev/null
+++ b/drivers/net/dsa/mv88e6060.h
@@ -0,0 +1,111 @@
1/*
2 * drivers/net/dsa/mv88e6060.h - Marvell 88e6060 switch chip support
3 * Copyright (c) 2015 Neil Armstrong
4 *
5 * Based on mv88e6xxx.h
6 * Copyright (c) 2008 Marvell Semiconductor
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#ifndef __MV88E6060_H
15#define __MV88E6060_H
16
17#define MV88E6060_PORTS 6
18
19#define REG_PORT(p) (0x8 + (p))
20#define PORT_STATUS 0x00
21#define PORT_STATUS_PAUSE_EN BIT(15)
22#define PORT_STATUS_MY_PAUSE BIT(14)
23#define PORT_STATUS_FC (PORT_STATUS_MY_PAUSE | PORT_STATUS_PAUSE_EN)
24#define PORT_STATUS_RESOLVED BIT(13)
25#define PORT_STATUS_LINK BIT(12)
26#define PORT_STATUS_PORTMODE BIT(11)
27#define PORT_STATUS_PHYMODE BIT(10)
28#define PORT_STATUS_DUPLEX BIT(9)
29#define PORT_STATUS_SPEED BIT(8)
30#define PORT_SWITCH_ID 0x03
31#define PORT_SWITCH_ID_6060 0x0600
32#define PORT_SWITCH_ID_6060_MASK 0xfff0
33#define PORT_SWITCH_ID_6060_R1 0x0601
34#define PORT_SWITCH_ID_6060_R2 0x0602
35#define PORT_CONTROL 0x04
36#define PORT_CONTROL_FORCE_FLOW_CTRL BIT(15)
37#define PORT_CONTROL_TRAILER BIT(14)
38#define PORT_CONTROL_HEADER BIT(11)
39#define PORT_CONTROL_INGRESS_MODE BIT(8)
40#define PORT_CONTROL_VLAN_TUNNEL BIT(7)
41#define PORT_CONTROL_STATE_MASK 0x03
42#define PORT_CONTROL_STATE_DISABLED 0x00
43#define PORT_CONTROL_STATE_BLOCKING 0x01
44#define PORT_CONTROL_STATE_LEARNING 0x02
45#define PORT_CONTROL_STATE_FORWARDING 0x03
46#define PORT_VLAN_MAP 0x06
47#define PORT_VLAN_MAP_DBNUM_SHIFT 12
48#define PORT_VLAN_MAP_TABLE_MASK 0x1f
49#define PORT_ASSOC_VECTOR 0x0b
50#define PORT_ASSOC_VECTOR_MONITOR BIT(15)
51#define PORT_ASSOC_VECTOR_PAV_MASK 0x1f
52#define PORT_RX_CNTR 0x10
53#define PORT_TX_CNTR 0x11
54
55#define REG_GLOBAL 0x0f
56#define GLOBAL_STATUS 0x00
57#define GLOBAL_STATUS_SW_MODE_MASK (0x3 << 12)
58#define GLOBAL_STATUS_SW_MODE_0 (0x0 << 12)
59#define GLOBAL_STATUS_SW_MODE_1 (0x1 << 12)
60#define GLOBAL_STATUS_SW_MODE_2 (0x2 << 12)
61#define GLOBAL_STATUS_SW_MODE_3 (0x3 << 12)
62#define GLOBAL_STATUS_INIT_READY BIT(11)
63#define GLOBAL_STATUS_ATU_FULL BIT(3)
64#define GLOBAL_STATUS_ATU_DONE BIT(2)
65#define GLOBAL_STATUS_PHY_INT BIT(1)
66#define GLOBAL_STATUS_EEINT BIT(0)
67#define GLOBAL_MAC_01 0x01
68#define GLOBAL_MAC_01_DIFF_ADDR BIT(8)
69#define GLOBAL_MAC_23 0x02
70#define GLOBAL_MAC_45 0x03
71#define GLOBAL_CONTROL 0x04
72#define GLOBAL_CONTROL_DISCARD_EXCESS BIT(13)
73#define GLOBAL_CONTROL_MAX_FRAME_1536 BIT(10)
74#define GLOBAL_CONTROL_RELOAD_EEPROM BIT(9)
75#define GLOBAL_CONTROL_CTRMODE BIT(8)
76#define GLOBAL_CONTROL_ATU_FULL_EN BIT(3)
77#define GLOBAL_CONTROL_ATU_DONE_EN BIT(2)
78#define GLOBAL_CONTROL_PHYINT_EN BIT(1)
79#define GLOBAL_CONTROL_EEPROM_DONE_EN BIT(0)
80#define GLOBAL_ATU_CONTROL 0x0a
81#define GLOBAL_ATU_CONTROL_SWRESET BIT(15)
82#define GLOBAL_ATU_CONTROL_LEARNDIS BIT(14)
83#define GLOBAL_ATU_CONTROL_ATUSIZE_256 (0x0 << 12)
84#define GLOBAL_ATU_CONTROL_ATUSIZE_512 (0x1 << 12)
85#define GLOBAL_ATU_CONTROL_ATUSIZE_1024 (0x2 << 12)
86#define GLOBAL_ATU_CONTROL_ATE_AGE_SHIFT 4
87#define GLOBAL_ATU_CONTROL_ATE_AGE_MASK (0xff << 4)
88#define GLOBAL_ATU_CONTROL_ATE_AGE_5MIN (0x13 << 4)
89#define GLOBAL_ATU_OP 0x0b
90#define GLOBAL_ATU_OP_BUSY BIT(15)
91#define GLOBAL_ATU_OP_NOP (0 << 12)
92#define GLOBAL_ATU_OP_FLUSH_ALL ((1 << 12) | GLOBAL_ATU_OP_BUSY)
93#define GLOBAL_ATU_OP_FLUSH_UNLOCKED ((2 << 12) | GLOBAL_ATU_OP_BUSY)
94#define GLOBAL_ATU_OP_LOAD_DB ((3 << 12) | GLOBAL_ATU_OP_BUSY)
95#define GLOBAL_ATU_OP_GET_NEXT_DB ((4 << 12) | GLOBAL_ATU_OP_BUSY)
96#define GLOBAL_ATU_OP_FLUSH_DB ((5 << 12) | GLOBAL_ATU_OP_BUSY)
97#define GLOBAL_ATU_OP_FLUSH_UNLOCKED_DB ((6 << 12) | GLOBAL_ATU_OP_BUSY)
98#define GLOBAL_ATU_DATA 0x0c
99#define GLOBAL_ATU_DATA_PORT_VECTOR_MASK 0x3f0
100#define GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT 4
101#define GLOBAL_ATU_DATA_STATE_MASK 0x0f
102#define GLOBAL_ATU_DATA_STATE_UNUSED 0x00
103#define GLOBAL_ATU_DATA_STATE_UC_STATIC 0x0e
104#define GLOBAL_ATU_DATA_STATE_UC_LOCKED 0x0f
105#define GLOBAL_ATU_DATA_STATE_MC_STATIC 0x07
106#define GLOBAL_ATU_DATA_STATE_MC_LOCKED 0x0e
107#define GLOBAL_ATU_MAC_01 0x0d
108#define GLOBAL_ATU_MAC_23 0x0e
109#define GLOBAL_ATU_MAC_45 0x0f
110
111#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-05-31 05:39:02 -0400