diff options
Diffstat (limited to 'drivers/misc/pci_endpoint_test.c')
-rw-r--r-- | drivers/misc/pci_endpoint_test.c | 81 |
1 files changed, 50 insertions, 31 deletions
diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c index 7b370466a227..35fbfbd73a6d 100644 --- a/drivers/misc/pci_endpoint_test.c +++ b/drivers/misc/pci_endpoint_test.c | |||
@@ -35,38 +35,43 @@ | |||
35 | 35 | ||
36 | #include <uapi/linux/pcitest.h> | 36 | #include <uapi/linux/pcitest.h> |
37 | 37 | ||
38 | #define DRV_MODULE_NAME "pci-endpoint-test" | 38 | #define DRV_MODULE_NAME "pci-endpoint-test" |
39 | 39 | ||
40 | #define PCI_ENDPOINT_TEST_MAGIC 0x0 | 40 | #define IRQ_TYPE_LEGACY 0 |
41 | 41 | #define IRQ_TYPE_MSI 1 | |
42 | #define PCI_ENDPOINT_TEST_COMMAND 0x4 | 42 | |
43 | #define COMMAND_RAISE_LEGACY_IRQ BIT(0) | 43 | #define PCI_ENDPOINT_TEST_MAGIC 0x0 |
44 | #define COMMAND_RAISE_MSI_IRQ BIT(1) | 44 | |
45 | #define MSI_NUMBER_SHIFT 2 | 45 | #define PCI_ENDPOINT_TEST_COMMAND 0x4 |
46 | /* 6 bits for MSI number */ | 46 | #define COMMAND_RAISE_LEGACY_IRQ BIT(0) |
47 | #define COMMAND_READ BIT(8) | 47 | #define COMMAND_RAISE_MSI_IRQ BIT(1) |
48 | #define COMMAND_WRITE BIT(9) | 48 | /* BIT(2) is reserved for raising MSI-X IRQ command */ |
49 | #define COMMAND_COPY BIT(10) | 49 | #define COMMAND_READ BIT(3) |
50 | 50 | #define COMMAND_WRITE BIT(4) | |
51 | #define PCI_ENDPOINT_TEST_STATUS 0x8 | 51 | #define COMMAND_COPY BIT(5) |
52 | #define STATUS_READ_SUCCESS BIT(0) | 52 | |
53 | #define STATUS_READ_FAIL BIT(1) | 53 | #define PCI_ENDPOINT_TEST_STATUS 0x8 |
54 | #define STATUS_WRITE_SUCCESS BIT(2) | 54 | #define STATUS_READ_SUCCESS BIT(0) |
55 | #define STATUS_WRITE_FAIL BIT(3) | 55 | #define STATUS_READ_FAIL BIT(1) |
56 | #define STATUS_COPY_SUCCESS BIT(4) | 56 | #define STATUS_WRITE_SUCCESS BIT(2) |
57 | #define STATUS_COPY_FAIL BIT(5) | 57 | #define STATUS_WRITE_FAIL BIT(3) |
58 | #define STATUS_IRQ_RAISED BIT(6) | 58 | #define STATUS_COPY_SUCCESS BIT(4) |
59 | #define STATUS_SRC_ADDR_INVALID BIT(7) | 59 | #define STATUS_COPY_FAIL BIT(5) |
60 | #define STATUS_DST_ADDR_INVALID BIT(8) | 60 | #define STATUS_IRQ_RAISED BIT(6) |
61 | 61 | #define STATUS_SRC_ADDR_INVALID BIT(7) | |
62 | #define PCI_ENDPOINT_TEST_LOWER_SRC_ADDR 0xc | 62 | #define STATUS_DST_ADDR_INVALID BIT(8) |
63 | |||
64 | #define PCI_ENDPOINT_TEST_LOWER_SRC_ADDR 0x0c | ||
63 | #define PCI_ENDPOINT_TEST_UPPER_SRC_ADDR 0x10 | 65 | #define PCI_ENDPOINT_TEST_UPPER_SRC_ADDR 0x10 |
64 | 66 | ||
65 | #define PCI_ENDPOINT_TEST_LOWER_DST_ADDR 0x14 | 67 | #define PCI_ENDPOINT_TEST_LOWER_DST_ADDR 0x14 |
66 | #define PCI_ENDPOINT_TEST_UPPER_DST_ADDR 0x18 | 68 | #define PCI_ENDPOINT_TEST_UPPER_DST_ADDR 0x18 |
67 | 69 | ||
68 | #define PCI_ENDPOINT_TEST_SIZE 0x1c | 70 | #define PCI_ENDPOINT_TEST_SIZE 0x1c |
69 | #define PCI_ENDPOINT_TEST_CHECKSUM 0x20 | 71 | #define PCI_ENDPOINT_TEST_CHECKSUM 0x20 |
72 | |||
73 | #define PCI_ENDPOINT_TEST_IRQ_TYPE 0x24 | ||
74 | #define PCI_ENDPOINT_TEST_IRQ_NUMBER 0x28 | ||
70 | 75 | ||
71 | static DEFINE_IDA(pci_endpoint_test_ida); | 76 | static DEFINE_IDA(pci_endpoint_test_ida); |
72 | 77 | ||
@@ -179,6 +184,9 @@ static bool pci_endpoint_test_legacy_irq(struct pci_endpoint_test *test) | |||
179 | { | 184 | { |
180 | u32 val; | 185 | u32 val; |
181 | 186 | ||
187 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, | ||
188 | IRQ_TYPE_LEGACY); | ||
189 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 0); | ||
182 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND, | 190 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND, |
183 | COMMAND_RAISE_LEGACY_IRQ); | 191 | COMMAND_RAISE_LEGACY_IRQ); |
184 | val = wait_for_completion_timeout(&test->irq_raised, | 192 | val = wait_for_completion_timeout(&test->irq_raised, |
@@ -195,8 +203,10 @@ static bool pci_endpoint_test_msi_irq(struct pci_endpoint_test *test, | |||
195 | u32 val; | 203 | u32 val; |
196 | struct pci_dev *pdev = test->pdev; | 204 | struct pci_dev *pdev = test->pdev; |
197 | 205 | ||
206 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, | ||
207 | IRQ_TYPE_MSI); | ||
208 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, msi_num); | ||
198 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND, | 209 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND, |
199 | msi_num << MSI_NUMBER_SHIFT | | ||
200 | COMMAND_RAISE_MSI_IRQ); | 210 | COMMAND_RAISE_MSI_IRQ); |
201 | val = wait_for_completion_timeout(&test->irq_raised, | 211 | val = wait_for_completion_timeout(&test->irq_raised, |
202 | msecs_to_jiffies(1000)); | 212 | msecs_to_jiffies(1000)); |
@@ -281,8 +291,11 @@ static bool pci_endpoint_test_copy(struct pci_endpoint_test *test, size_t size) | |||
281 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, | 291 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, |
282 | size); | 292 | size); |
283 | 293 | ||
294 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, | ||
295 | no_msi ? IRQ_TYPE_LEGACY : IRQ_TYPE_MSI); | ||
296 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1); | ||
284 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND, | 297 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND, |
285 | 1 << MSI_NUMBER_SHIFT | COMMAND_COPY); | 298 | COMMAND_COPY); |
286 | 299 | ||
287 | wait_for_completion(&test->irq_raised); | 300 | wait_for_completion(&test->irq_raised); |
288 | 301 | ||
@@ -348,8 +361,11 @@ static bool pci_endpoint_test_write(struct pci_endpoint_test *test, size_t size) | |||
348 | 361 | ||
349 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size); | 362 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size); |
350 | 363 | ||
364 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, | ||
365 | no_msi ? IRQ_TYPE_LEGACY : IRQ_TYPE_MSI); | ||
366 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1); | ||
351 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND, | 367 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND, |
352 | 1 << MSI_NUMBER_SHIFT | COMMAND_READ); | 368 | COMMAND_READ); |
353 | 369 | ||
354 | wait_for_completion(&test->irq_raised); | 370 | wait_for_completion(&test->irq_raised); |
355 | 371 | ||
@@ -403,8 +419,11 @@ static bool pci_endpoint_test_read(struct pci_endpoint_test *test, size_t size) | |||
403 | 419 | ||
404 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size); | 420 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size); |
405 | 421 | ||
422 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, | ||
423 | no_msi ? IRQ_TYPE_LEGACY : IRQ_TYPE_MSI); | ||
424 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1); | ||
406 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND, | 425 | pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND, |
407 | 1 << MSI_NUMBER_SHIFT | COMMAND_WRITE); | 426 | COMMAND_WRITE); |
408 | 427 | ||
409 | wait_for_completion(&test->irq_raised); | 428 | wait_for_completion(&test->irq_raised); |
410 | 429 | ||