1 files changed, 8 insertions, 2 deletions

diff --git a/drivers/misc/mei/hw-me.c b/drivers/misc/mei/hw-me.c
index 25b1997a62cb..e2fb44cc5c37 100644
--- a/drivers/misc/mei/hw-me.c
+++ b/drivers/misc/mei/hw-me.c
@@ -189,8 +189,11 @@ static int mei_me_fw_status(struct mei_device *dev,
 
         fw_status->count = fw_src->count;
         for (i = 0; i < fw_src->count && i < MEI_FW_STATUS_MAX; i++) {
-                ret = pci_read_config_dword(pdev,
-                        fw_src->status[i], &fw_status->status[i]);
+                ret = pci_read_config_dword(pdev, fw_src->status[i],
+                                            &fw_status->status[i]);
+                trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HSF_X",
+                                       fw_src->status[i],
+                                       fw_status->status[i]);
                 if (ret)
                         return ret;
         }
@@ -215,6 +218,7 @@ static void mei_me_hw_config(struct mei_device *dev)
 
         reg = 0;
         pci_read_config_dword(pdev, PCI_CFG_HFS_1, &reg);
+        trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HFS_1", PCI_CFG_HFS_1, reg);
         hw->d0i3_supported =
                 ((reg & PCI_CFG_HFS_1_D0I3_MSK) == PCI_CFG_HFS_1_D0I3_MSK);
 
@@ -1248,6 +1252,7 @@ static bool mei_me_fw_type_nm(struct pci_dev *pdev)
         u32 reg;
 
         pci_read_config_dword(pdev, PCI_CFG_HFS_2, &reg);
+        trace_mei_pci_cfg_read(&pdev->dev, "PCI_CFG_HFS_2", PCI_CFG_HFS_2, reg);
         /* make sure that bit 9 (NM) is up and bit 10 (DM) is down */
         return (reg & 0x600) == 0x200;
 }
@@ -1260,6 +1265,7 @@ static bool mei_me_fw_type_sps(struct pci_dev *pdev)
         u32 reg;
         /* Read ME FW Status check for SPS Firmware */
         pci_read_config_dword(pdev, PCI_CFG_HFS_1, &reg);
+        trace_mei_pci_cfg_read(&pdev->dev, "PCI_CFG_HFS_1", PCI_CFG_HFS_1, reg);
         /* if bits [19:16] = 15, running SPS Firmware */
         return (reg & 0xf0000) == 0xf0000;
 }