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path: root/drivers/misc/cxl/pci.c
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Diffstat (limited to 'drivers/misc/cxl/pci.c')
-rw-r--r--drivers/misc/cxl/pci.c12
1 files changed, 8 insertions, 4 deletions
diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
index d152e2de8c93..6f0c4ac4b649 100644
--- a/drivers/misc/cxl/pci.c
+++ b/drivers/misc/cxl/pci.c
@@ -379,7 +379,7 @@ static int calc_capp_routing(struct pci_dev *dev, u64 *chipid, u64 *capp_unit_id
379 379
380static int init_implementation_adapter_psl_regs(struct cxl *adapter, struct pci_dev *dev) 380static int init_implementation_adapter_psl_regs(struct cxl *adapter, struct pci_dev *dev)
381{ 381{
382 u64 psl_dsnctl; 382 u64 psl_dsnctl, psl_fircntl;
383 u64 chipid; 383 u64 chipid;
384 u64 capp_unit_id; 384 u64 capp_unit_id;
385 int rc; 385 int rc;
@@ -398,8 +398,11 @@ static int init_implementation_adapter_psl_regs(struct cxl *adapter, struct pci_
398 cxl_p1_write(adapter, CXL_PSL_RESLCKTO, 0x20000000200ULL); 398 cxl_p1_write(adapter, CXL_PSL_RESLCKTO, 0x20000000200ULL);
399 /* snoop write mask */ 399 /* snoop write mask */
400 cxl_p1_write(adapter, CXL_PSL_SNWRALLOC, 0x00000000FFFFFFFFULL); 400 cxl_p1_write(adapter, CXL_PSL_SNWRALLOC, 0x00000000FFFFFFFFULL);
401 /* set fir_accum */ 401 /* set fir_cntl to recommended value for production env */
402 cxl_p1_write(adapter, CXL_PSL_FIR_CNTL, 0x0800000000000000ULL); 402 psl_fircntl = (0x2ULL << (63-3)); /* ce_report */
403 psl_fircntl |= (0x1ULL << (63-6)); /* FIR_report */
404 psl_fircntl |= 0x1ULL; /* ce_thresh */
405 cxl_p1_write(adapter, CXL_PSL_FIR_CNTL, psl_fircntl);
403 /* for debugging with trace arrays */ 406 /* for debugging with trace arrays */
404 cxl_p1_write(adapter, CXL_PSL_TRACE, 0x0000FF7C00000000ULL); 407 cxl_p1_write(adapter, CXL_PSL_TRACE, 0x0000FF7C00000000ULL);
405 408
@@ -1521,14 +1524,15 @@ static const struct cxl_service_layer_ops xsl_ops = {
1521 .write_timebase_ctrl = write_timebase_ctrl_xsl, 1524 .write_timebase_ctrl = write_timebase_ctrl_xsl,
1522 .timebase_read = timebase_read_xsl, 1525 .timebase_read = timebase_read_xsl,
1523 .capi_mode = OPAL_PHB_CAPI_MODE_DMA, 1526 .capi_mode = OPAL_PHB_CAPI_MODE_DMA,
1524 .min_pe = 1, /* Workaround for Mellanox CX4 HW bug */
1525}; 1527};
1526 1528
1527static void set_sl_ops(struct cxl *adapter, struct pci_dev *dev) 1529static void set_sl_ops(struct cxl *adapter, struct pci_dev *dev)
1528{ 1530{
1529 if (dev->vendor == PCI_VENDOR_ID_MELLANOX && dev->device == 0x1013) { 1531 if (dev->vendor == PCI_VENDOR_ID_MELLANOX && dev->device == 0x1013) {
1532 /* Mellanox CX-4 */
1530 dev_info(&adapter->dev, "Device uses an XSL\n"); 1533 dev_info(&adapter->dev, "Device uses an XSL\n");
1531 adapter->native->sl_ops = &xsl_ops; 1534 adapter->native->sl_ops = &xsl_ops;
1535 adapter->min_pe = 1; /* Workaround for CX-4 hardware bug */
1532 } else { 1536 } else {
1533 dev_info(&adapter->dev, "Device uses a PSL\n"); 1537 dev_info(&adapter->dev, "Device uses a PSL\n");
1534 adapter->native->sl_ops = &psl_ops; 1538 adapter->native->sl_ops = &psl_ops;