diff options
Diffstat (limited to 'drivers/media/video/tvp7002.c')
| -rw-r--r-- | drivers/media/video/tvp7002.c | 15 |
1 files changed, 5 insertions, 10 deletions
diff --git a/drivers/media/video/tvp7002.c b/drivers/media/video/tvp7002.c index b799851bf3d0..7875e80cb2ff 100644 --- a/drivers/media/video/tvp7002.c +++ b/drivers/media/video/tvp7002.c | |||
| @@ -28,6 +28,7 @@ | |||
| 28 | #include <linux/i2c.h> | 28 | #include <linux/i2c.h> |
| 29 | #include <linux/slab.h> | 29 | #include <linux/slab.h> |
| 30 | #include <linux/videodev2.h> | 30 | #include <linux/videodev2.h> |
| 31 | #include <linux/module.h> | ||
| 31 | #include <media/tvp7002.h> | 32 | #include <media/tvp7002.h> |
| 32 | #include <media/v4l2-device.h> | 33 | #include <media/v4l2-device.h> |
| 33 | #include <media/v4l2-chip-ident.h> | 34 | #include <media/v4l2-chip-ident.h> |
| @@ -128,7 +129,7 @@ static const struct i2c_reg_value tvp7002_init_default[] = { | |||
| 128 | { TVP7002_ADC_SETUP, 0x50, TVP7002_WRITE }, | 129 | { TVP7002_ADC_SETUP, 0x50, TVP7002_WRITE }, |
| 129 | { TVP7002_COARSE_CLAMP_CTL, 0x00, TVP7002_WRITE }, | 130 | { TVP7002_COARSE_CLAMP_CTL, 0x00, TVP7002_WRITE }, |
| 130 | { TVP7002_SOG_CLAMP, 0x80, TVP7002_WRITE }, | 131 | { TVP7002_SOG_CLAMP, 0x80, TVP7002_WRITE }, |
| 131 | { TVP7002_RGB_COARSE_CLAMP_CTL, 0x00, TVP7002_WRITE }, | 132 | { TVP7002_RGB_COARSE_CLAMP_CTL, 0x8c, TVP7002_WRITE }, |
| 132 | { TVP7002_SOG_COARSE_CLAMP_CTL, 0x04, TVP7002_WRITE }, | 133 | { TVP7002_SOG_COARSE_CLAMP_CTL, 0x04, TVP7002_WRITE }, |
| 133 | { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE }, | 134 | { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE }, |
| 134 | { 0x32, 0x18, TVP7002_RESERVED }, | 135 | { 0x32, 0x18, TVP7002_RESERVED }, |
| @@ -182,7 +183,6 @@ static const struct i2c_reg_value tvp7002_parms_480P[] = { | |||
| 182 | { TVP7002_HPLL_FDBK_DIV_MSBS, 0x35, TVP7002_WRITE }, | 183 | { TVP7002_HPLL_FDBK_DIV_MSBS, 0x35, TVP7002_WRITE }, |
| 183 | { TVP7002_HPLL_FDBK_DIV_LSBS, 0xa0, TVP7002_WRITE }, | 184 | { TVP7002_HPLL_FDBK_DIV_LSBS, 0xa0, TVP7002_WRITE }, |
| 184 | { TVP7002_HPLL_CRTL, 0x02, TVP7002_WRITE }, | 185 | { TVP7002_HPLL_CRTL, 0x02, TVP7002_WRITE }, |
| 185 | { TVP7002_HPLL_PHASE_SEL, 0x14, TVP7002_WRITE }, | ||
| 186 | { TVP7002_AVID_START_PIXEL_LSBS, 0x91, TVP7002_WRITE }, | 186 | { TVP7002_AVID_START_PIXEL_LSBS, 0x91, TVP7002_WRITE }, |
| 187 | { TVP7002_AVID_START_PIXEL_MSBS, 0x00, TVP7002_WRITE }, | 187 | { TVP7002_AVID_START_PIXEL_MSBS, 0x00, TVP7002_WRITE }, |
| 188 | { TVP7002_AVID_STOP_PIXEL_LSBS, 0x0B, TVP7002_WRITE }, | 188 | { TVP7002_AVID_STOP_PIXEL_LSBS, 0x0B, TVP7002_WRITE }, |
| @@ -204,7 +204,6 @@ static const struct i2c_reg_value tvp7002_parms_576P[] = { | |||
| 204 | { TVP7002_HPLL_FDBK_DIV_MSBS, 0x36, TVP7002_WRITE }, | 204 | { TVP7002_HPLL_FDBK_DIV_MSBS, 0x36, TVP7002_WRITE }, |
| 205 | { TVP7002_HPLL_FDBK_DIV_LSBS, 0x00, TVP7002_WRITE }, | 205 | { TVP7002_HPLL_FDBK_DIV_LSBS, 0x00, TVP7002_WRITE }, |
| 206 | { TVP7002_HPLL_CRTL, 0x18, TVP7002_WRITE }, | 206 | { TVP7002_HPLL_CRTL, 0x18, TVP7002_WRITE }, |
| 207 | { TVP7002_HPLL_PHASE_SEL, 0x14, TVP7002_WRITE }, | ||
| 208 | { TVP7002_AVID_START_PIXEL_LSBS, 0x9B, TVP7002_WRITE }, | 207 | { TVP7002_AVID_START_PIXEL_LSBS, 0x9B, TVP7002_WRITE }, |
| 209 | { TVP7002_AVID_START_PIXEL_MSBS, 0x00, TVP7002_WRITE }, | 208 | { TVP7002_AVID_START_PIXEL_MSBS, 0x00, TVP7002_WRITE }, |
| 210 | { TVP7002_AVID_STOP_PIXEL_LSBS, 0x0F, TVP7002_WRITE }, | 209 | { TVP7002_AVID_STOP_PIXEL_LSBS, 0x0F, TVP7002_WRITE }, |
| @@ -226,7 +225,6 @@ static const struct i2c_reg_value tvp7002_parms_1080I60[] = { | |||
| 226 | { TVP7002_HPLL_FDBK_DIV_MSBS, 0x89, TVP7002_WRITE }, | 225 | { TVP7002_HPLL_FDBK_DIV_MSBS, 0x89, TVP7002_WRITE }, |
| 227 | { TVP7002_HPLL_FDBK_DIV_LSBS, 0x80, TVP7002_WRITE }, | 226 | { TVP7002_HPLL_FDBK_DIV_LSBS, 0x80, TVP7002_WRITE }, |
| 228 | { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE }, | 227 | { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE }, |
| 229 | { TVP7002_HPLL_PHASE_SEL, 0x14, TVP7002_WRITE }, | ||
| 230 | { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE }, | 228 | { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE }, |
| 231 | { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE }, | 229 | { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE }, |
| 232 | { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE }, | 230 | { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE }, |
| @@ -248,7 +246,6 @@ static const struct i2c_reg_value tvp7002_parms_1080P60[] = { | |||
| 248 | { TVP7002_HPLL_FDBK_DIV_MSBS, 0x89, TVP7002_WRITE }, | 246 | { TVP7002_HPLL_FDBK_DIV_MSBS, 0x89, TVP7002_WRITE }, |
| 249 | { TVP7002_HPLL_FDBK_DIV_LSBS, 0x80, TVP7002_WRITE }, | 247 | { TVP7002_HPLL_FDBK_DIV_LSBS, 0x80, TVP7002_WRITE }, |
| 250 | { TVP7002_HPLL_CRTL, 0xE0, TVP7002_WRITE }, | 248 | { TVP7002_HPLL_CRTL, 0xE0, TVP7002_WRITE }, |
| 251 | { TVP7002_HPLL_PHASE_SEL, 0x14, TVP7002_WRITE }, | ||
| 252 | { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE }, | 249 | { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE }, |
| 253 | { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE }, | 250 | { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE }, |
| 254 | { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE }, | 251 | { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE }, |
| @@ -270,7 +267,6 @@ static const struct i2c_reg_value tvp7002_parms_1080I50[] = { | |||
| 270 | { TVP7002_HPLL_FDBK_DIV_MSBS, 0xa5, TVP7002_WRITE }, | 267 | { TVP7002_HPLL_FDBK_DIV_MSBS, 0xa5, TVP7002_WRITE }, |
| 271 | { TVP7002_HPLL_FDBK_DIV_LSBS, 0x00, TVP7002_WRITE }, | 268 | { TVP7002_HPLL_FDBK_DIV_LSBS, 0x00, TVP7002_WRITE }, |
| 272 | { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE }, | 269 | { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE }, |
| 273 | { TVP7002_HPLL_PHASE_SEL, 0x14, TVP7002_WRITE }, | ||
| 274 | { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE }, | 270 | { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE }, |
| 275 | { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE }, | 271 | { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE }, |
| 276 | { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE }, | 272 | { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE }, |
| @@ -292,7 +288,6 @@ static const struct i2c_reg_value tvp7002_parms_720P60[] = { | |||
| 292 | { TVP7002_HPLL_FDBK_DIV_MSBS, 0x67, TVP7002_WRITE }, | 288 | { TVP7002_HPLL_FDBK_DIV_MSBS, 0x67, TVP7002_WRITE }, |
| 293 | { TVP7002_HPLL_FDBK_DIV_LSBS, 0x20, TVP7002_WRITE }, | 289 | { TVP7002_HPLL_FDBK_DIV_LSBS, 0x20, TVP7002_WRITE }, |
| 294 | { TVP7002_HPLL_CRTL, 0xa0, TVP7002_WRITE }, | 290 | { TVP7002_HPLL_CRTL, 0xa0, TVP7002_WRITE }, |
| 295 | { TVP7002_HPLL_PHASE_SEL, 0x16, TVP7002_WRITE }, | ||
| 296 | { TVP7002_AVID_START_PIXEL_LSBS, 0x47, TVP7002_WRITE }, | 291 | { TVP7002_AVID_START_PIXEL_LSBS, 0x47, TVP7002_WRITE }, |
| 297 | { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE }, | 292 | { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE }, |
| 298 | { TVP7002_AVID_STOP_PIXEL_LSBS, 0x4B, TVP7002_WRITE }, | 293 | { TVP7002_AVID_STOP_PIXEL_LSBS, 0x4B, TVP7002_WRITE }, |
| @@ -314,7 +309,6 @@ static const struct i2c_reg_value tvp7002_parms_720P50[] = { | |||
| 314 | { TVP7002_HPLL_FDBK_DIV_MSBS, 0x7b, TVP7002_WRITE }, | 309 | { TVP7002_HPLL_FDBK_DIV_MSBS, 0x7b, TVP7002_WRITE }, |
| 315 | { TVP7002_HPLL_FDBK_DIV_LSBS, 0xc0, TVP7002_WRITE }, | 310 | { TVP7002_HPLL_FDBK_DIV_LSBS, 0xc0, TVP7002_WRITE }, |
| 316 | { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE }, | 311 | { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE }, |
| 317 | { TVP7002_HPLL_PHASE_SEL, 0x16, TVP7002_WRITE }, | ||
| 318 | { TVP7002_AVID_START_PIXEL_LSBS, 0x47, TVP7002_WRITE }, | 312 | { TVP7002_AVID_START_PIXEL_LSBS, 0x47, TVP7002_WRITE }, |
| 319 | { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE }, | 313 | { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE }, |
| 320 | { TVP7002_AVID_STOP_PIXEL_LSBS, 0x4B, TVP7002_WRITE }, | 314 | { TVP7002_AVID_STOP_PIXEL_LSBS, 0x4B, TVP7002_WRITE }, |
| @@ -687,6 +681,9 @@ static int tvp7002_query_dv_preset(struct v4l2_subdev *sd, | |||
| 687 | u8 cpl_msb; | 681 | u8 cpl_msb; |
| 688 | int index; | 682 | int index; |
| 689 | 683 | ||
| 684 | /* Return invalid preset if no active input is detected */ | ||
| 685 | qpreset->preset = V4L2_DV_INVALID; | ||
| 686 | |||
| 690 | device = to_tvp7002(sd); | 687 | device = to_tvp7002(sd); |
| 691 | 688 | ||
| 692 | /* Read standards from device registers */ | 689 | /* Read standards from device registers */ |
| @@ -720,8 +717,6 @@ static int tvp7002_query_dv_preset(struct v4l2_subdev *sd, | |||
| 720 | if (index == NUM_PRESETS) { | 717 | if (index == NUM_PRESETS) { |
| 721 | v4l2_dbg(1, debug, sd, "detection failed: lpf = %x, cpl = %x\n", | 718 | v4l2_dbg(1, debug, sd, "detection failed: lpf = %x, cpl = %x\n", |
| 722 | lpfr, cpln); | 719 | lpfr, cpln); |
| 723 | /* Could not detect a signal, so return the 'invalid' preset */ | ||
| 724 | qpreset->preset = V4L2_DV_INVALID; | ||
| 725 | return 0; | 720 | return 0; |
| 726 | } | 721 | } |
| 727 | 722 | ||
