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path: root/drivers/media/usb/dvb-usb/dib0700_devices.c
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Diffstat (limited to 'drivers/media/usb/dvb-usb/dib0700_devices.c')
-rw-r--r--drivers/media/usb/dvb-usb/dib0700_devices.c465
1 files changed, 222 insertions, 243 deletions
diff --git a/drivers/media/usb/dvb-usb/dib0700_devices.c b/drivers/media/usb/dvb-usb/dib0700_devices.c
index 11798426fa88..f08136052f9c 100644
--- a/drivers/media/usb/dvb-usb/dib0700_devices.c
+++ b/drivers/media/usb/dvb-usb/dib0700_devices.c
@@ -1431,13 +1431,22 @@ static int dib8090_get_adc_power(struct dvb_frontend *fe)
1431 return dib8000_get_adc_power(fe, 1); 1431 return dib8000_get_adc_power(fe, 1);
1432} 1432}
1433 1433
1434static void dib8090_agc_control(struct dvb_frontend *fe, u8 restart)
1435{
1436 deb_info("AGC control callback: %i\n", restart);
1437 dib0090_dcc_freq(fe, restart);
1438
1439 if (restart == 0) /* before AGC startup */
1440 dib0090_set_dc_servo(fe, 1);
1441}
1442
1434static struct dib8000_config dib809x_dib8000_config[2] = { 1443static struct dib8000_config dib809x_dib8000_config[2] = {
1435 { 1444 {
1436 .output_mpeg2_in_188_bytes = 1, 1445 .output_mpeg2_in_188_bytes = 1,
1437 1446
1438 .agc_config_count = 2, 1447 .agc_config_count = 2,
1439 .agc = dib8090_agc_config, 1448 .agc = dib8090_agc_config,
1440 .agc_control = dib0090_dcc_freq, 1449 .agc_control = dib8090_agc_control,
1441 .pll = &dib8090_pll_config_12mhz, 1450 .pll = &dib8090_pll_config_12mhz,
1442 .tuner_is_baseband = 1, 1451 .tuner_is_baseband = 1,
1443 1452
@@ -1456,7 +1465,7 @@ static struct dib8000_config dib809x_dib8000_config[2] = {
1456 1465
1457 .agc_config_count = 2, 1466 .agc_config_count = 2,
1458 .agc = dib8090_agc_config, 1467 .agc = dib8090_agc_config,
1459 .agc_control = dib0090_dcc_freq, 1468 .agc_control = dib8090_agc_control,
1460 .pll = &dib8090_pll_config_12mhz, 1469 .pll = &dib8090_pll_config_12mhz,
1461 .tuner_is_baseband = 1, 1470 .tuner_is_baseband = 1,
1462 1471
@@ -1504,28 +1513,89 @@ static struct dib0090_config dib809x_dib0090_config = {
1504 .fref_clock_ratio = 6, 1513 .fref_clock_ratio = 6,
1505}; 1514};
1506 1515
1516static u8 dib8090_compute_pll_parameters(struct dvb_frontend *fe)
1517{
1518 u8 optimal_pll_ratio = 20;
1519 u32 freq_adc, ratio, rest, max = 0;
1520 u8 pll_ratio;
1521
1522 for (pll_ratio = 17; pll_ratio <= 20; pll_ratio++) {
1523 freq_adc = 12 * pll_ratio * (1 << 8) / 16;
1524 ratio = ((fe->dtv_property_cache.frequency / 1000) * (1 << 8) / 1000) / freq_adc;
1525 rest = ((fe->dtv_property_cache.frequency / 1000) * (1 << 8) / 1000) - ratio * freq_adc;
1526
1527 if (rest > freq_adc / 2)
1528 rest = freq_adc - rest;
1529 deb_info("PLL ratio=%i rest=%i\n", pll_ratio, rest);
1530 if ((rest > max) && (rest > 717)) {
1531 optimal_pll_ratio = pll_ratio;
1532 max = rest;
1533 }
1534 }
1535 deb_info("optimal PLL ratio=%i\n", optimal_pll_ratio);
1536
1537 return optimal_pll_ratio;
1538}
1539
1507static int dib8096_set_param_override(struct dvb_frontend *fe) 1540static int dib8096_set_param_override(struct dvb_frontend *fe)
1508{ 1541{
1509 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1510 struct dvb_usb_adapter *adap = fe->dvb->priv; 1542 struct dvb_usb_adapter *adap = fe->dvb->priv;
1511 struct dib0700_adapter_state *state = adap->priv; 1543 struct dib0700_adapter_state *state = adap->priv;
1512 u8 band = BAND_OF_FREQUENCY(p->frequency/1000); 1544 u8 pll_ratio, band = BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000);
1513 u16 target; 1545 u16 target, ltgain, rf_gain_limit;
1546 u32 timf;
1514 int ret = 0; 1547 int ret = 0;
1515 enum frontend_tune_state tune_state = CT_SHUTDOWN; 1548 enum frontend_tune_state tune_state = CT_SHUTDOWN;
1516 u16 ltgain, rf_gain_limit; 1549
1550 switch (band) {
1551 default:
1552 deb_info("Warning : Rf frequency (%iHz) is not in the supported range, using VHF switch ", fe->dtv_property_cache.frequency);
1553 case BAND_VHF:
1554 dib8000_set_gpio(fe, 3, 0, 1);
1555 break;
1556 case BAND_UHF:
1557 dib8000_set_gpio(fe, 3, 0, 0);
1558 break;
1559 }
1517 1560
1518 ret = state->set_param_save(fe); 1561 ret = state->set_param_save(fe);
1519 if (ret < 0) 1562 if (ret < 0)
1520 return ret; 1563 return ret;
1521 1564
1522 target = (dib0090_get_wbd_target(fe) * 8 * 18 / 33 + 1) / 2; 1565 if (fe->dtv_property_cache.bandwidth_hz != 6000000) {
1523 dib8000_set_wbd_ref(fe, target); 1566 deb_info("only 6MHz bandwidth is supported\n");
1567 return -EINVAL;
1568 }
1569
1570 /** Update PLL if needed ratio **/
1571 dib8000_update_pll(fe, &dib8090_pll_config_12mhz, fe->dtv_property_cache.bandwidth_hz / 1000, 0);
1572
1573 /** Get optimize PLL ratio to remove spurious **/
1574 pll_ratio = dib8090_compute_pll_parameters(fe);
1575 if (pll_ratio == 17)
1576 timf = 21387946;
1577 else if (pll_ratio == 18)
1578 timf = 20199727;
1579 else if (pll_ratio == 19)
1580 timf = 19136583;
1581 else
1582 timf = 18179756;
1583
1584 /** Update ratio **/
1585 dib8000_update_pll(fe, &dib8090_pll_config_12mhz, fe->dtv_property_cache.bandwidth_hz / 1000, pll_ratio);
1524 1586
1587 dib8000_ctrl_timf(fe, DEMOD_TIMF_SET, timf);
1588
1589 if (band != BAND_CBAND) {
1590 /* dib0090_get_wbd_target is returning any possible temperature compensated wbd-target */
1591 target = (dib0090_get_wbd_target(fe) * 8 * 18 / 33 + 1) / 2;
1592 dib8000_set_wbd_ref(fe, target);
1593 }
1525 1594
1526 if (band == BAND_CBAND) { 1595 if (band == BAND_CBAND) {
1527 deb_info("tuning in CBAND - soft-AGC startup\n"); 1596 deb_info("tuning in CBAND - soft-AGC startup\n");
1528 dib0090_set_tune_state(fe, CT_AGC_START); 1597 dib0090_set_tune_state(fe, CT_AGC_START);
1598
1529 do { 1599 do {
1530 ret = dib0090_gain_control(fe); 1600 ret = dib0090_gain_control(fe);
1531 msleep(ret); 1601 msleep(ret);
@@ -1534,14 +1604,17 @@ static int dib8096_set_param_override(struct dvb_frontend *fe)
1534 dib8000_set_gpio(fe, 6, 0, 1); 1604 dib8000_set_gpio(fe, 6, 0, 1);
1535 else if (tune_state == CT_AGC_STEP_1) { 1605 else if (tune_state == CT_AGC_STEP_1) {
1536 dib0090_get_current_gain(fe, NULL, NULL, &rf_gain_limit, &ltgain); 1606 dib0090_get_current_gain(fe, NULL, NULL, &rf_gain_limit, &ltgain);
1537 if (rf_gain_limit == 0) 1607 if (rf_gain_limit < 2000) /* activate the external attenuator in case of very high input power */
1538 dib8000_set_gpio(fe, 6, 0, 0); 1608 dib8000_set_gpio(fe, 6, 0, 0);
1539 } 1609 }
1540 } while (tune_state < CT_AGC_STOP); 1610 } while (tune_state < CT_AGC_STOP);
1611
1612 deb_info("switching to PWM AGC\n");
1541 dib0090_pwm_gain_reset(fe); 1613 dib0090_pwm_gain_reset(fe);
1542 dib8000_pwm_agc_reset(fe); 1614 dib8000_pwm_agc_reset(fe);
1543 dib8000_set_tune_state(fe, CT_DEMOD_START); 1615 dib8000_set_tune_state(fe, CT_DEMOD_START);
1544 } else { 1616 } else {
1617 /* for everything else than CBAND we are using standard AGC */
1545 deb_info("not tuning in CBAND - standard AGC startup\n"); 1618 deb_info("not tuning in CBAND - standard AGC startup\n");
1546 dib0090_pwm_gain_reset(fe); 1619 dib0090_pwm_gain_reset(fe);
1547 } 1620 }
@@ -1814,21 +1887,92 @@ struct dibx090p_adc {
1814 u32 pll_prediv; /* New loopdiv */ 1887 u32 pll_prediv; /* New loopdiv */
1815}; 1888};
1816 1889
1817struct dibx090p_adc dib8090p_adc_tab[] = { 1890struct dibx090p_best_adc {
1818 { 50000, 17043521, 16, 3}, /* 64 MHz */ 1891 u32 timf;
1819 {878000, 20199729, 9, 1}, /* 60 MHz */ 1892 u32 pll_loopdiv;
1820 {0xffffffff, 0, 0, 0}, /* 60 MHz */ 1893 u32 pll_prediv;
1821}; 1894};
1822 1895
1896static int dib8096p_get_best_sampling(struct dvb_frontend *fe, struct dibx090p_best_adc *adc)
1897{
1898 u8 spur = 0, prediv = 0, loopdiv = 0, min_prediv = 1, max_prediv = 1;
1899 u16 xtal = 12000;
1900 u16 fcp_min = 1900; /* PLL, Minimum Frequency of phase comparator (KHz) */
1901 u16 fcp_max = 20000; /* PLL, Maximum Frequency of phase comparator (KHz) */
1902 u32 fmem_max = 140000; /* 140MHz max SDRAM freq */
1903 u32 fdem_min = 66000;
1904 u32 fcp = 0, fs = 0, fdem = 0, fmem = 0;
1905 u32 harmonic_id = 0;
1906
1907 adc->timf = 0;
1908 adc->pll_loopdiv = loopdiv;
1909 adc->pll_prediv = prediv;
1910
1911 deb_info("bandwidth = %d", fe->dtv_property_cache.bandwidth_hz);
1912
1913 /* Find Min and Max prediv */
1914 while ((xtal / max_prediv) >= fcp_min)
1915 max_prediv++;
1916
1917 max_prediv--;
1918 min_prediv = max_prediv;
1919 while ((xtal / min_prediv) <= fcp_max) {
1920 min_prediv--;
1921 if (min_prediv == 1)
1922 break;
1923 }
1924 deb_info("MIN prediv = %d : MAX prediv = %d", min_prediv, max_prediv);
1925
1926 min_prediv = 1;
1927
1928 for (prediv = min_prediv; prediv < max_prediv; prediv++) {
1929 fcp = xtal / prediv;
1930 if (fcp > fcp_min && fcp < fcp_max) {
1931 for (loopdiv = 1; loopdiv < 64; loopdiv++) {
1932 fmem = ((xtal/prediv) * loopdiv);
1933 fdem = fmem / 2;
1934 fs = fdem / 4;
1935
1936 /* test min/max system restrictions */
1937 if ((fdem >= fdem_min) && (fmem <= fmem_max) && (fs >= fe->dtv_property_cache.bandwidth_hz / 1000)) {
1938 spur = 0;
1939 /* test fs harmonics positions */
1940 for (harmonic_id = (fe->dtv_property_cache.frequency / (1000 * fs)); harmonic_id <= ((fe->dtv_property_cache.frequency / (1000 * fs)) + 1); harmonic_id++) {
1941 if (((fs * harmonic_id) >= (fe->dtv_property_cache.frequency / 1000 - (fe->dtv_property_cache.bandwidth_hz / 2000))) && ((fs * harmonic_id) <= (fe->dtv_property_cache.frequency / 1000 + (fe->dtv_property_cache.bandwidth_hz / 2000)))) {
1942 spur = 1;
1943 break;
1944 }
1945 }
1946
1947 if (!spur) {
1948 adc->pll_loopdiv = loopdiv;
1949 adc->pll_prediv = prediv;
1950 adc->timf = (4260880253U / fdem) * (1 << 8);
1951 adc->timf += ((4260880253U % fdem) << 8) / fdem;
1952
1953 deb_info("RF %6d; BW %6d; Xtal %6d; Fmem %6d; Fdem %6d; Fs %6d; Prediv %2d; Loopdiv %2d; Timf %8d;", fe->dtv_property_cache.frequency, fe->dtv_property_cache.bandwidth_hz, xtal, fmem, fdem, fs, prediv, loopdiv, adc->timf);
1954 break;
1955 }
1956 }
1957 }
1958 }
1959 if (!spur)
1960 break;
1961 }
1962
1963 if (adc->pll_loopdiv == 0 && adc->pll_prediv == 0)
1964 return -EINVAL;
1965 return 0;
1966}
1967
1823static int dib8096p_agc_startup(struct dvb_frontend *fe) 1968static int dib8096p_agc_startup(struct dvb_frontend *fe)
1824{ 1969{
1825 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1826 struct dvb_usb_adapter *adap = fe->dvb->priv; 1970 struct dvb_usb_adapter *adap = fe->dvb->priv;
1827 struct dib0700_adapter_state *state = adap->priv; 1971 struct dib0700_adapter_state *state = adap->priv;
1828 struct dibx000_bandwidth_config pll; 1972 struct dibx000_bandwidth_config pll;
1973 struct dibx090p_best_adc adc;
1829 u16 target; 1974 u16 target;
1830 int better_sampling_freq = 0, ret; 1975 int ret;
1831 struct dibx090p_adc *adc_table = &dib8090p_adc_tab[0];
1832 1976
1833 ret = state->set_param_save(fe); 1977 ret = state->set_param_save(fe);
1834 if (ret < 0) 1978 if (ret < 0)
@@ -1841,23 +1985,27 @@ static int dib8096p_agc_startup(struct dvb_frontend *fe)
1841 target = (dib0090_get_wbd_target(fe) * 8 + 1) / 2; 1985 target = (dib0090_get_wbd_target(fe) * 8 + 1) / 2;
1842 dib8000_set_wbd_ref(fe, target); 1986 dib8000_set_wbd_ref(fe, target);
1843 1987
1988 if (dib8096p_get_best_sampling(fe, &adc) == 0) {
1989 pll.pll_ratio = adc.pll_loopdiv;
1990 pll.pll_prediv = adc.pll_prediv;
1844 1991
1845 while (p->frequency / 1000 > adc_table->freq) { 1992 dib0700_set_i2c_speed(adap->dev, 200);
1846 better_sampling_freq = 1; 1993 dib8000_update_pll(fe, &pll, fe->dtv_property_cache.bandwidth_hz / 1000, 0);
1847 adc_table++; 1994 dib8000_ctrl_timf(fe, DEMOD_TIMF_SET, adc.timf);
1848 } 1995 dib0700_set_i2c_speed(adap->dev, 1000);
1849
1850 if ((adc_table->freq != 0xffffffff) && better_sampling_freq) {
1851 pll.pll_ratio = adc_table->pll_loopdiv;
1852 pll.pll_prediv = adc_table->pll_prediv;
1853 dib8000_update_pll(fe, &pll);
1854 dib8000_ctrl_timf(fe, DEMOD_TIMF_SET, adc_table->timf);
1855 } 1996 }
1856 return 0; 1997 return 0;
1857} 1998}
1858 1999
1859static int tfe8096p_frontend_attach(struct dvb_usb_adapter *adap) 2000static int tfe8096p_frontend_attach(struct dvb_usb_adapter *adap)
1860{ 2001{
2002 struct dib0700_state *st = adap->dev->priv;
2003 u32 fw_version;
2004
2005 dib0700_get_version(adap->dev, NULL, NULL, &fw_version, NULL);
2006 if (fw_version >= 0x10200)
2007 st->fw_use_new_i2c_api = 1;
2008
1861 dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 1); 2009 dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 1);
1862 msleep(20); 2010 msleep(20);
1863 dib0700_set_gpio(adap->dev, GPIO9, GPIO_OUT, 1); 2011 dib0700_set_gpio(adap->dev, GPIO9, GPIO_OUT, 1);
@@ -2242,13 +2390,7 @@ static int nim9090md_tuner_attach(struct dvb_usb_adapter *adap)
2242} 2390}
2243 2391
2244/* NIM7090 */ 2392/* NIM7090 */
2245struct dib7090p_best_adc { 2393static int dib7090p_get_best_sampling(struct dvb_frontend *fe , struct dibx090p_best_adc *adc)
2246 u32 timf;
2247 u32 pll_loopdiv;
2248 u32 pll_prediv;
2249};
2250
2251static int dib7090p_get_best_sampling(struct dvb_frontend *fe , struct dib7090p_best_adc *adc)
2252{ 2394{
2253 u8 spur = 0, prediv = 0, loopdiv = 0, min_prediv = 1, max_prediv = 1; 2395 u8 spur = 0, prediv = 0, loopdiv = 0, min_prediv = 1, max_prediv = 1;
2254 2396
@@ -2327,7 +2469,7 @@ static int dib7090_agc_startup(struct dvb_frontend *fe)
2327 struct dib0700_adapter_state *state = adap->priv; 2469 struct dib0700_adapter_state *state = adap->priv;
2328 struct dibx000_bandwidth_config pll; 2470 struct dibx000_bandwidth_config pll;
2329 u16 target; 2471 u16 target;
2330 struct dib7090p_best_adc adc; 2472 struct dibx090p_best_adc adc;
2331 int ret; 2473 int ret;
2332 2474
2333 ret = state->set_param_save(fe); 2475 ret = state->set_param_save(fe);
@@ -2357,36 +2499,16 @@ static int dib7090_agc_restart(struct dvb_frontend *fe, u8 restart)
2357 return 0; 2499 return 0;
2358} 2500}
2359 2501
2360static int dib7090e_update_lna(struct dvb_frontend *fe, u16 agc_global) 2502static int tfe7790p_update_lna(struct dvb_frontend *fe, u16 agc_global)
2361{ 2503{
2362 u16 agc1 = 0, agc2, wbd = 0, wbd_target, wbd_offset, threshold_agc1; 2504 deb_info("update LNA: agc global=%i", agc_global);
2363 s16 wbd_delta;
2364 2505
2365 if ((fe->dtv_property_cache.frequency) < 400000000) 2506 if (agc_global < 25000) {
2366 threshold_agc1 = 25000; 2507 dib7000p_set_gpio(fe, 8, 0, 0);
2367 else 2508 dib7000p_set_agc1_min(fe, 0);
2368 threshold_agc1 = 30000;
2369
2370 wbd_target = (dib0090_get_wbd_target(fe)*8+1)/2;
2371 wbd_offset = dib0090_get_wbd_offset(fe);
2372 dib7000p_get_agc_values(fe, NULL, &agc1, &agc2, &wbd);
2373 wbd_delta = (s16)wbd - (((s16)wbd_offset+10)*4) ;
2374
2375 deb_info("update lna, agc_global=%d agc1=%d agc2=%d",
2376 agc_global, agc1, agc2);
2377 deb_info("update lna, wbd=%d wbd target=%d wbd offset=%d wbd delta=%d",
2378 wbd, wbd_target, wbd_offset, wbd_delta);
2379
2380 if ((agc1 < threshold_agc1) && (wbd_delta > 0)) {
2381 dib0090_set_switch(fe, 1, 1, 1);
2382 dib0090_set_vga(fe, 0);
2383 dib0090_update_rframp_7090(fe, 0);
2384 dib0090_update_tuning_table_7090(fe, 0);
2385 } else { 2509 } else {
2386 dib0090_set_vga(fe, 1); 2510 dib7000p_set_gpio(fe, 8, 0, 1);
2387 dib0090_update_rframp_7090(fe, 1); 2511 dib7000p_set_agc1_min(fe, 32768);
2388 dib0090_update_tuning_table_7090(fe, 1);
2389 dib0090_set_switch(fe, 0, 0, 0);
2390 } 2512 }
2391 2513
2392 return 0; 2514 return 0;
@@ -2400,15 +2522,6 @@ static struct dib0090_wbd_slope dib7090_wbd_table[] = {
2400 { 0xFFFF, 0, 0, 0, 0, 0}, 2522 { 0xFFFF, 0, 0, 0, 0, 0},
2401}; 2523};
2402 2524
2403static struct dib0090_wbd_slope dib7090e_wbd_table[] = {
2404 { 380, 81, 850, 64, 540, 4},
2405 { 700, 51, 866, 21, 320, 4},
2406 { 860, 48, 666, 18, 330, 6},
2407 {1700, 0, 250, 0, 100, 6},
2408 {2600, 0, 250, 0, 100, 6},
2409 { 0xFFFF, 0, 0, 0, 0, 0},
2410};
2411
2412static struct dibx000_agc_config dib7090_agc_config[2] = { 2525static struct dibx000_agc_config dib7090_agc_config[2] = {
2413 { 2526 {
2414 .band_caps = BAND_UHF, 2527 .band_caps = BAND_UHF,
@@ -2428,7 +2541,7 @@ static struct dibx000_agc_config dib7090_agc_config[2] = {
2428 .wbd_alpha = 5, 2541 .wbd_alpha = 5,
2429 2542
2430 .agc1_max = 65535, 2543 .agc1_max = 65535,
2431 .agc1_min = 0, 2544 .agc1_min = 32768,
2432 2545
2433 .agc2_max = 65535, 2546 .agc2_max = 65535,
2434 .agc2_min = 0, 2547 .agc2_min = 0,
@@ -2505,7 +2618,7 @@ static struct dib7000p_config nim7090_dib7000p_config = {
2505 .output_mpeg2_in_188_bytes = 1, 2618 .output_mpeg2_in_188_bytes = 1,
2506 .hostbus_diversity = 1, 2619 .hostbus_diversity = 1,
2507 .tuner_is_baseband = 1, 2620 .tuner_is_baseband = 1,
2508 .update_lna = NULL, 2621 .update_lna = tfe7790p_update_lna, /* GPIO used is the same as TFE7790 */
2509 2622
2510 .agc_config_count = 2, 2623 .agc_config_count = 2,
2511 .agc = dib7090_agc_config, 2624 .agc = dib7090_agc_config,
@@ -2529,12 +2642,26 @@ static struct dib7000p_config nim7090_dib7000p_config = {
2529 .enMpegOutput = 1, 2642 .enMpegOutput = 1,
2530}; 2643};
2531 2644
2645static int tfe7090p_pvr_update_lna(struct dvb_frontend *fe, u16 agc_global)
2646{
2647 deb_info("TFE7090P-PVR update LNA: agc global=%i", agc_global);
2648 if (agc_global < 25000) {
2649 dib7000p_set_gpio(fe, 5, 0, 0);
2650 dib7000p_set_agc1_min(fe, 0);
2651 } else {
2652 dib7000p_set_gpio(fe, 5, 0, 1);
2653 dib7000p_set_agc1_min(fe, 32768);
2654 }
2655
2656 return 0;
2657}
2658
2532static struct dib7000p_config tfe7090pvr_dib7000p_config[2] = { 2659static struct dib7000p_config tfe7090pvr_dib7000p_config[2] = {
2533 { 2660 {
2534 .output_mpeg2_in_188_bytes = 1, 2661 .output_mpeg2_in_188_bytes = 1,
2535 .hostbus_diversity = 1, 2662 .hostbus_diversity = 1,
2536 .tuner_is_baseband = 1, 2663 .tuner_is_baseband = 1,
2537 .update_lna = NULL, 2664 .update_lna = tfe7090p_pvr_update_lna,
2538 2665
2539 .agc_config_count = 2, 2666 .agc_config_count = 2,
2540 .agc = dib7090_agc_config, 2667 .agc = dib7090_agc_config,
@@ -2561,7 +2688,7 @@ static struct dib7000p_config tfe7090pvr_dib7000p_config[2] = {
2561 .output_mpeg2_in_188_bytes = 1, 2688 .output_mpeg2_in_188_bytes = 1,
2562 .hostbus_diversity = 1, 2689 .hostbus_diversity = 1,
2563 .tuner_is_baseband = 1, 2690 .tuner_is_baseband = 1,
2564 .update_lna = NULL, 2691 .update_lna = tfe7090p_pvr_update_lna,
2565 2692
2566 .agc_config_count = 2, 2693 .agc_config_count = 2,
2567 .agc = dib7090_agc_config, 2694 .agc = dib7090_agc_config,
@@ -2587,34 +2714,6 @@ static struct dib7000p_config tfe7090pvr_dib7000p_config[2] = {
2587 } 2714 }
2588}; 2715};
2589 2716
2590static struct dib7000p_config tfe7090e_dib7000p_config = {
2591 .output_mpeg2_in_188_bytes = 1,
2592 .hostbus_diversity = 1,
2593 .tuner_is_baseband = 1,
2594 .update_lna = dib7090e_update_lna,
2595
2596 .agc_config_count = 2,
2597 .agc = dib7090_agc_config,
2598
2599 .bw = &dib7090_clock_config_12_mhz,
2600
2601 .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
2602 .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
2603 .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
2604
2605 .pwm_freq_div = 0,
2606
2607 .agc_control = dib7090_agc_restart,
2608
2609 .spur_protect = 0,
2610 .disable_sample_and_hold = 0,
2611 .enable_current_mirror = 0,
2612 .diversity_delay = 0,
2613
2614 .output_mode = OUTMODE_MPEG2_FIFO,
2615 .enMpegOutput = 1,
2616};
2617
2618static const struct dib0090_config nim7090_dib0090_config = { 2717static const struct dib0090_config nim7090_dib0090_config = {
2619 .io.clock_khz = 12000, 2718 .io.clock_khz = 12000,
2620 .io.pll_bypass = 0, 2719 .io.pll_bypass = 0,
@@ -2649,47 +2748,11 @@ static const struct dib0090_config nim7090_dib0090_config = {
2649 .in_soc = 1, 2748 .in_soc = 1,
2650}; 2749};
2651 2750
2652static const struct dib0090_config tfe7090e_dib0090_config = { 2751static struct dib7000p_config tfe7790p_dib7000p_config = {
2653 .io.clock_khz = 12000,
2654 .io.pll_bypass = 0,
2655 .io.pll_range = 0,
2656 .io.pll_prediv = 3,
2657 .io.pll_loopdiv = 6,
2658 .io.adc_clock_ratio = 0,
2659 .io.pll_int_loop_filt = 0,
2660 .reset = dib7090_tuner_sleep,
2661 .sleep = dib7090_tuner_sleep,
2662
2663 .freq_offset_khz_uhf = 0,
2664 .freq_offset_khz_vhf = 0,
2665
2666 .get_adc_power = dib7090_get_adc_power,
2667
2668 .clkouttobamse = 1,
2669 .analog_output = 0,
2670
2671 .wbd_vhf_offset = 0,
2672 .wbd_cband_offset = 0,
2673 .use_pwm_agc = 1,
2674 .clkoutdrive = 0,
2675
2676 .fref_clock_ratio = 0,
2677
2678 .wbd = dib7090e_wbd_table,
2679
2680 .ls_cfg_pad_drv = 0,
2681 .data_tx_drv = 0,
2682 .low_if = NULL,
2683 .in_soc = 1,
2684 .force_cband_input = 1,
2685 .is_dib7090e = 1,
2686};
2687
2688static struct dib7000p_config tfe7790e_dib7000p_config = {
2689 .output_mpeg2_in_188_bytes = 1, 2752 .output_mpeg2_in_188_bytes = 1,
2690 .hostbus_diversity = 1, 2753 .hostbus_diversity = 1,
2691 .tuner_is_baseband = 1, 2754 .tuner_is_baseband = 1,
2692 .update_lna = dib7090e_update_lna, 2755 .update_lna = tfe7790p_update_lna,
2693 2756
2694 .agc_config_count = 2, 2757 .agc_config_count = 2,
2695 .agc = dib7090_agc_config, 2758 .agc = dib7090_agc_config,
@@ -2713,7 +2776,7 @@ static struct dib7000p_config tfe7790e_dib7000p_config = {
2713 .enMpegOutput = 1, 2776 .enMpegOutput = 1,
2714}; 2777};
2715 2778
2716static const struct dib0090_config tfe7790e_dib0090_config = { 2779static const struct dib0090_config tfe7790p_dib0090_config = {
2717 .io.clock_khz = 12000, 2780 .io.clock_khz = 12000,
2718 .io.pll_bypass = 0, 2781 .io.pll_bypass = 0,
2719 .io.pll_range = 0, 2782 .io.pll_range = 0,
@@ -2739,14 +2802,14 @@ static const struct dib0090_config tfe7790e_dib0090_config = {
2739 2802
2740 .fref_clock_ratio = 0, 2803 .fref_clock_ratio = 0,
2741 2804
2742 .wbd = dib7090e_wbd_table, 2805 .wbd = dib7090_wbd_table,
2743 2806
2744 .ls_cfg_pad_drv = 0, 2807 .ls_cfg_pad_drv = 0,
2745 .data_tx_drv = 0, 2808 .data_tx_drv = 0,
2746 .low_if = NULL, 2809 .low_if = NULL,
2747 .in_soc = 1, 2810 .in_soc = 1,
2748 .force_cband_input = 1, 2811 .force_cband_input = 0,
2749 .is_dib7090e = 1, 2812 .is_dib7090e = 0,
2750 .force_crystal_mode = 1, 2813 .force_crystal_mode = 1,
2751}; 2814};
2752 2815
@@ -2942,37 +3005,11 @@ static int tfe7090pvr_tuner1_attach(struct dvb_usb_adapter *adap)
2942 return 0; 3005 return 0;
2943} 3006}
2944 3007
2945static int tfe7090e_frontend_attach(struct dvb_usb_adapter *adap) 3008static int tfe7790p_frontend_attach(struct dvb_usb_adapter *adap)
2946{
2947 dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 1);
2948 msleep(20);
2949 dib0700_set_gpio(adap->dev, GPIO9, GPIO_OUT, 1);
2950 dib0700_set_gpio(adap->dev, GPIO4, GPIO_OUT, 1);
2951 dib0700_set_gpio(adap->dev, GPIO7, GPIO_OUT, 1);
2952 dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 0);
2953
2954 msleep(20);
2955 dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 1);
2956 msleep(20);
2957 dib0700_set_gpio(adap->dev, GPIO0, GPIO_OUT, 1);
2958
2959 if (dib7000p_i2c_enumeration(&adap->dev->i2c_adap,
2960 1, 0x10, &tfe7090e_dib7000p_config) != 0) {
2961 err("%s: dib7000p_i2c_enumeration failed. Cannot continue\n",
2962 __func__);
2963 return -ENODEV;
2964 }
2965 adap->fe_adap[0].fe = dvb_attach(dib7000p_attach, &adap->dev->i2c_adap,
2966 0x80, &tfe7090e_dib7000p_config);
2967
2968 return adap->fe_adap[0].fe == NULL ? -ENODEV : 0;
2969}
2970
2971static int tfe7790e_frontend_attach(struct dvb_usb_adapter *adap)
2972{ 3009{
2973 struct dib0700_state *st = adap->dev->priv; 3010 struct dib0700_state *st = adap->dev->priv;
2974 3011
2975 /* The TFE7790E requires the dib0700 to not be in master mode */ 3012 /* The TFE7790P requires the dib0700 to not be in master mode */
2976 st->disable_streaming_master_mode = 1; 3013 st->disable_streaming_master_mode = 1;
2977 3014
2978 dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 1); 3015 dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 1);
@@ -2988,42 +3025,25 @@ static int tfe7790e_frontend_attach(struct dvb_usb_adapter *adap)
2988 dib0700_set_gpio(adap->dev, GPIO0, GPIO_OUT, 1); 3025 dib0700_set_gpio(adap->dev, GPIO0, GPIO_OUT, 1);
2989 3026
2990 if (dib7000p_i2c_enumeration(&adap->dev->i2c_adap, 3027 if (dib7000p_i2c_enumeration(&adap->dev->i2c_adap,
2991 1, 0x10, &tfe7790e_dib7000p_config) != 0) { 3028 1, 0x10, &tfe7790p_dib7000p_config) != 0) {
2992 err("%s: dib7000p_i2c_enumeration failed. Cannot continue\n", 3029 err("%s: dib7000p_i2c_enumeration failed. Cannot continue\n",
2993 __func__); 3030 __func__);
2994 return -ENODEV; 3031 return -ENODEV;
2995 } 3032 }
2996 adap->fe_adap[0].fe = dvb_attach(dib7000p_attach, &adap->dev->i2c_adap, 3033 adap->fe_adap[0].fe = dvb_attach(dib7000p_attach, &adap->dev->i2c_adap,
2997 0x80, &tfe7790e_dib7000p_config); 3034 0x80, &tfe7790p_dib7000p_config);
2998 3035
2999 return adap->fe_adap[0].fe == NULL ? -ENODEV : 0; 3036 return adap->fe_adap[0].fe == NULL ? -ENODEV : 0;
3000} 3037}
3001 3038
3002static int tfe7790e_tuner_attach(struct dvb_usb_adapter *adap) 3039static int tfe7790p_tuner_attach(struct dvb_usb_adapter *adap)
3003{
3004 struct dib0700_adapter_state *st = adap->priv;
3005 struct i2c_adapter *tun_i2c =
3006 dib7090_get_i2c_tuner(adap->fe_adap[0].fe);
3007
3008 if (dvb_attach(dib0090_register, adap->fe_adap[0].fe, tun_i2c,
3009 &tfe7790e_dib0090_config) == NULL)
3010 return -ENODEV;
3011
3012 dib7000p_set_gpio(adap->fe_adap[0].fe, 8, 0, 1);
3013
3014 st->set_param_save = adap->fe_adap[0].fe->ops.tuner_ops.set_params;
3015 adap->fe_adap[0].fe->ops.tuner_ops.set_params = dib7090_agc_startup;
3016 return 0;
3017}
3018
3019static int tfe7090e_tuner_attach(struct dvb_usb_adapter *adap)
3020{ 3040{
3021 struct dib0700_adapter_state *st = adap->priv; 3041 struct dib0700_adapter_state *st = adap->priv;
3022 struct i2c_adapter *tun_i2c = 3042 struct i2c_adapter *tun_i2c =
3023 dib7090_get_i2c_tuner(adap->fe_adap[0].fe); 3043 dib7090_get_i2c_tuner(adap->fe_adap[0].fe);
3024 3044
3025 if (dvb_attach(dib0090_register, adap->fe_adap[0].fe, tun_i2c, 3045 if (dvb_attach(dib0090_register, adap->fe_adap[0].fe, tun_i2c,
3026 &tfe7090e_dib0090_config) == NULL) 3046 &tfe7790p_dib0090_config) == NULL)
3027 return -ENODEV; 3047 return -ENODEV;
3028 3048
3029 dib7000p_set_gpio(adap->fe_adap[0].fe, 8, 0, 1); 3049 dib7000p_set_gpio(adap->fe_adap[0].fe, 8, 0, 1);
@@ -3566,10 +3586,9 @@ struct usb_device_id dib0700_usb_id_table[] = {
3566/* 75 */{ USB_DEVICE(USB_VID_MEDION, USB_PID_CREATIX_CTX1921) }, 3586/* 75 */{ USB_DEVICE(USB_VID_MEDION, USB_PID_CREATIX_CTX1921) },
3567 { USB_DEVICE(USB_VID_PINNACLE, USB_PID_PINNACLE_PCTV340E) }, 3587 { USB_DEVICE(USB_VID_PINNACLE, USB_PID_PINNACLE_PCTV340E) },
3568 { USB_DEVICE(USB_VID_PINNACLE, USB_PID_PINNACLE_PCTV340E_SE) }, 3588 { USB_DEVICE(USB_VID_PINNACLE, USB_PID_PINNACLE_PCTV340E_SE) },
3569 { USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_TFE7090E) }, 3589 { USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_TFE7790P) },
3570 { USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_TFE7790E) }, 3590 { USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_TFE8096P) },
3571/* 80 */{ USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_TFE8096P) }, 3591/* 80 */{ USB_DEVICE(USB_VID_ELGATO, USB_PID_ELGATO_EYETV_DTT_2) },
3572 { USB_DEVICE(USB_VID_ELGATO, USB_PID_ELGATO_EYETV_DTT_2) },
3573 { 0 } /* Terminating entry */ 3592 { 0 } /* Terminating entry */
3574}; 3593};
3575MODULE_DEVICE_TABLE(usb, dib0700_usb_id_table); 3594MODULE_DEVICE_TABLE(usb, dib0700_usb_id_table);
@@ -3880,7 +3899,7 @@ struct dvb_usb_device_properties dib0700_devices[] = {
3880 { NULL }, 3899 { NULL },
3881 }, 3900 },
3882 { "Elgato EyeTV DTT rev. 2", 3901 { "Elgato EyeTV DTT rev. 2",
3883 { &dib0700_usb_id_table[81], NULL }, 3902 { &dib0700_usb_id_table[80], NULL },
3884 { NULL }, 3903 { NULL },
3885 }, 3904 },
3886 }, 3905 },
@@ -4697,48 +4716,8 @@ struct dvb_usb_device_properties dib0700_devices[] = {
4697 .pid_filter_count = 32, 4716 .pid_filter_count = 32,
4698 .pid_filter = stk70x0p_pid_filter, 4717 .pid_filter = stk70x0p_pid_filter,
4699 .pid_filter_ctrl = stk70x0p_pid_filter_ctrl, 4718 .pid_filter_ctrl = stk70x0p_pid_filter_ctrl,
4700 .frontend_attach = tfe7090e_frontend_attach, 4719 .frontend_attach = tfe7790p_frontend_attach,
4701 .tuner_attach = tfe7090e_tuner_attach, 4720 .tuner_attach = tfe7790p_tuner_attach,
4702
4703 DIB0700_DEFAULT_STREAMING_CONFIG(0x02),
4704 } },
4705
4706 .size_of_priv =
4707 sizeof(struct dib0700_adapter_state),
4708 },
4709 },
4710
4711 .num_device_descs = 1,
4712 .devices = {
4713 { "DiBcom TFE7090E reference design",
4714 { &dib0700_usb_id_table[78], NULL },
4715 { NULL },
4716 },
4717 },
4718
4719 .rc.core = {
4720 .rc_interval = DEFAULT_RC_INTERVAL,
4721 .rc_codes = RC_MAP_DIB0700_RC5_TABLE,
4722 .module_name = "dib0700",
4723 .rc_query = dib0700_rc_query_old_firmware,
4724 .allowed_protos = RC_BIT_RC5 |
4725 RC_BIT_RC6_MCE |
4726 RC_BIT_NEC,
4727 .change_protocol = dib0700_change_protocol,
4728 },
4729 }, { DIB0700_DEFAULT_DEVICE_PROPERTIES,
4730 .num_adapters = 1,
4731 .adapter = {
4732 {
4733 .num_frontends = 1,
4734 .fe = {{
4735 .caps = DVB_USB_ADAP_HAS_PID_FILTER |
4736 DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
4737 .pid_filter_count = 32,
4738 .pid_filter = stk70x0p_pid_filter,
4739 .pid_filter_ctrl = stk70x0p_pid_filter_ctrl,
4740 .frontend_attach = tfe7790e_frontend_attach,
4741 .tuner_attach = tfe7790e_tuner_attach,
4742 4721
4743 DIB0700_DEFAULT_STREAMING_CONFIG(0x03), 4722 DIB0700_DEFAULT_STREAMING_CONFIG(0x03),
4744 } }, 4723 } },
@@ -4750,8 +4729,8 @@ struct dvb_usb_device_properties dib0700_devices[] = {
4750 4729
4751 .num_device_descs = 1, 4730 .num_device_descs = 1,
4752 .devices = { 4731 .devices = {
4753 { "DiBcom TFE7790E reference design", 4732 { "DiBcom TFE7790P reference design",
4754 { &dib0700_usb_id_table[79], NULL }, 4733 { &dib0700_usb_id_table[78], NULL },
4755 { NULL }, 4734 { NULL },
4756 }, 4735 },
4757 }, 4736 },
@@ -4792,7 +4771,7 @@ struct dvb_usb_device_properties dib0700_devices[] = {
4792 .num_device_descs = 1, 4771 .num_device_descs = 1,
4793 .devices = { 4772 .devices = {
4794 { "DiBcom TFE8096P reference design", 4773 { "DiBcom TFE8096P reference design",
4795 { &dib0700_usb_id_table[80], NULL }, 4774 { &dib0700_usb_id_table[79], NULL },
4796 { NULL }, 4775 { NULL },
4797 }, 4776 },
4798 }, 4777 },