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-rw-r--r--drivers/media/platform/renesas-ceu.c1677
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diff --git a/drivers/media/platform/renesas-ceu.c b/drivers/media/platform/renesas-ceu.c
new file mode 100644
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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * V4L2 Driver for Renesas Capture Engine Unit (CEU) interface
4 * Copyright (C) 2017-2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
5 *
6 * Based on soc-camera driver "soc_camera/sh_mobile_ceu_camera.c"
7 * Copyright (C) 2008 Magnus Damm
8 *
9 * Based on V4L2 Driver for PXA camera host - "pxa_camera.c",
10 * Copyright (C) 2006, Sascha Hauer, Pengutronix
11 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
12 */
13
14#include <linux/delay.h>
15#include <linux/device.h>
16#include <linux/dma-mapping.h>
17#include <linux/err.h>
18#include <linux/errno.h>
19#include <linux/interrupt.h>
20#include <linux/io.h>
21#include <linux/kernel.h>
22#include <linux/mm.h>
23#include <linux/module.h>
24#include <linux/of.h>
25#include <linux/of_device.h>
26#include <linux/of_graph.h>
27#include <linux/platform_device.h>
28#include <linux/pm_runtime.h>
29#include <linux/slab.h>
30#include <linux/time.h>
31#include <linux/videodev2.h>
32
33#include <media/v4l2-async.h>
34#include <media/v4l2-common.h>
35#include <media/v4l2-ctrls.h>
36#include <media/v4l2-dev.h>
37#include <media/v4l2-device.h>
38#include <media/v4l2-event.h>
39#include <media/v4l2-fwnode.h>
40#include <media/v4l2-image-sizes.h>
41#include <media/v4l2-ioctl.h>
42#include <media/v4l2-mediabus.h>
43#include <media/videobuf2-dma-contig.h>
44
45#include <media/drv-intf/renesas-ceu.h>
46
47#define DRIVER_NAME "renesas-ceu"
48
49/* CEU registers offsets and masks. */
50#define CEU_CAPSR 0x00 /* Capture start register */
51#define CEU_CAPCR 0x04 /* Capture control register */
52#define CEU_CAMCR 0x08 /* Capture interface control register */
53#define CEU_CAMOR 0x10 /* Capture interface offset register */
54#define CEU_CAPWR 0x14 /* Capture interface width register */
55#define CEU_CAIFR 0x18 /* Capture interface input format register */
56#define CEU_CRCNTR 0x28 /* CEU register control register */
57#define CEU_CRCMPR 0x2c /* CEU register forcible control register */
58#define CEU_CFLCR 0x30 /* Capture filter control register */
59#define CEU_CFSZR 0x34 /* Capture filter size clip register */
60#define CEU_CDWDR 0x38 /* Capture destination width register */
61#define CEU_CDAYR 0x3c /* Capture data address Y register */
62#define CEU_CDACR 0x40 /* Capture data address C register */
63#define CEU_CFWCR 0x5c /* Firewall operation control register */
64#define CEU_CDOCR 0x64 /* Capture data output control register */
65#define CEU_CEIER 0x70 /* Capture event interrupt enable register */
66#define CEU_CETCR 0x74 /* Capture event flag clear register */
67#define CEU_CSTSR 0x7c /* Capture status register */
68#define CEU_CSRTR 0x80 /* Capture software reset register */
69
70/* Data synchronous fetch mode. */
71#define CEU_CAMCR_JPEG BIT(4)
72
73/* Input components ordering: CEU_CAMCR.DTARY field. */
74#define CEU_CAMCR_DTARY_8_UYVY (0x00 << 8)
75#define CEU_CAMCR_DTARY_8_VYUY (0x01 << 8)
76#define CEU_CAMCR_DTARY_8_YUYV (0x02 << 8)
77#define CEU_CAMCR_DTARY_8_YVYU (0x03 << 8)
78/* TODO: input components ordering for 16 bits input. */
79
80/* Bus transfer MTU. */
81#define CEU_CAPCR_BUS_WIDTH256 (0x3 << 20)
82
83/* Bus width configuration. */
84#define CEU_CAMCR_DTIF_16BITS BIT(12)
85
86/* No downsampling to planar YUV420 in image fetch mode. */
87#define CEU_CDOCR_NO_DOWSAMPLE BIT(4)
88
89/* Swap all input data in 8-bit, 16-bits and 32-bits units (Figure 46.45). */
90#define CEU_CDOCR_SWAP_ENDIANNESS (7)
91
92/* Capture reset and enable bits. */
93#define CEU_CAPSR_CPKIL BIT(16)
94#define CEU_CAPSR_CE BIT(0)
95
96/* CEU operating flag bit. */
97#define CEU_CAPCR_CTNCP BIT(16)
98#define CEU_CSTRST_CPTON BIT(0)
99
100/* Platform specific IRQ source flags. */
101#define CEU_CETCR_ALL_IRQS_RZ 0x397f313
102#define CEU_CETCR_ALL_IRQS_SH4 0x3d7f313
103
104/* Prohibited register access interrupt bit. */
105#define CEU_CETCR_IGRW BIT(4)
106/* One-frame capture end interrupt. */
107#define CEU_CEIER_CPE BIT(0)
108/* VBP error. */
109#define CEU_CEIER_VBP BIT(20)
110#define CEU_CEIER_MASK (CEU_CEIER_CPE | CEU_CEIER_VBP)
111
112#define CEU_MAX_WIDTH 2560
113#define CEU_MAX_HEIGHT 1920
114#define CEU_MAX_BPL 8188
115#define CEU_W_MAX(w) ((w) < CEU_MAX_WIDTH ? (w) : CEU_MAX_WIDTH)
116#define CEU_H_MAX(h) ((h) < CEU_MAX_HEIGHT ? (h) : CEU_MAX_HEIGHT)
117
118/*
119 * ceu_bus_fmt - describe a 8-bits yuyv format the sensor can produce
120 *
121 * @mbus_code: bus format code
122 * @fmt_order: CEU_CAMCR.DTARY ordering of input components (Y, Cb, Cr)
123 * @fmt_order_swap: swapped CEU_CAMCR.DTARY ordering of input components
124 * (Y, Cr, Cb)
125 * @swapped: does Cr appear before Cb?
126 * @bps: number of bits sent over bus for each sample
127 * @bpp: number of bits per pixels unit
128 */
129struct ceu_mbus_fmt {
130 u32 mbus_code;
131 u32 fmt_order;
132 u32 fmt_order_swap;
133 bool swapped;
134 u8 bps;
135 u8 bpp;
136};
137
138/*
139 * ceu_buffer - Link vb2 buffer to the list of available buffers.
140 */
141struct ceu_buffer {
142 struct vb2_v4l2_buffer vb;
143 struct list_head queue;
144};
145
146static inline struct ceu_buffer *vb2_to_ceu(struct vb2_v4l2_buffer *vbuf)
147{
148 return container_of(vbuf, struct ceu_buffer, vb);
149}
150
151/*
152 * ceu_subdev - Wraps v4l2 sub-device and provides async subdevice.
153 */
154struct ceu_subdev {
155 struct v4l2_subdev *v4l2_sd;
156 struct v4l2_async_subdev asd;
157
158 /* per-subdevice mbus configuration options */
159 unsigned int mbus_flags;
160 struct ceu_mbus_fmt mbus_fmt;
161};
162
163static struct ceu_subdev *to_ceu_subdev(struct v4l2_async_subdev *asd)
164{
165 return container_of(asd, struct ceu_subdev, asd);
166}
167
168/*
169 * ceu_device - CEU device instance
170 */
171struct ceu_device {
172 struct device *dev;
173 struct video_device vdev;
174 struct v4l2_device v4l2_dev;
175
176 /* subdevices descriptors */
177 struct ceu_subdev *subdevs;
178 /* the subdevice currently in use */
179 struct ceu_subdev *sd;
180 unsigned int sd_index;
181 unsigned int num_sd;
182
183 /* platform specific mask with all IRQ sources flagged */
184 u32 irq_mask;
185
186 /* currently configured field and pixel format */
187 enum v4l2_field field;
188 struct v4l2_pix_format_mplane v4l2_pix;
189
190 /* async subdev notification helpers */
191 struct v4l2_async_notifier notifier;
192 /* pointers to "struct ceu_subdevice -> asd" */
193 struct v4l2_async_subdev **asds;
194
195 /* vb2 queue, capture buffer list and active buffer pointer */
196 struct vb2_queue vb2_vq;
197 struct list_head capture;
198 struct vb2_v4l2_buffer *active;
199 unsigned int sequence;
200
201 /* mlock - lock access to interface reset and vb2 queue */
202 struct mutex mlock;
203
204 /* lock - lock access to capture buffer queue and active buffer */
205 spinlock_t lock;
206
207 /* base - CEU memory base address */
208 void __iomem *base;
209};
210
211static inline struct ceu_device *v4l2_to_ceu(struct v4l2_device *v4l2_dev)
212{
213 return container_of(v4l2_dev, struct ceu_device, v4l2_dev);
214}
215
216/* --- CEU memory output formats --- */
217
218/*
219 * ceu_fmt - describe a memory output format supported by CEU interface.
220 *
221 * @fourcc: memory layout fourcc format code
222 * @bpp: number of bits for each pixel stored in memory
223 */
224struct ceu_fmt {
225 u32 fourcc;
226 u32 bpp;
227};
228
229/*
230 * ceu_format_list - List of supported memory output formats
231 *
232 * If sensor provides any YUYV bus format, all the following planar memory
233 * formats are available thanks to CEU re-ordering and sub-sampling
234 * capabilities.
235 */
236static const struct ceu_fmt ceu_fmt_list[] = {
237 {
238 .fourcc = V4L2_PIX_FMT_NV16,
239 .bpp = 16,
240 },
241 {
242 .fourcc = V4L2_PIX_FMT_NV61,
243 .bpp = 16,
244 },
245 {
246 .fourcc = V4L2_PIX_FMT_NV12,
247 .bpp = 12,
248 },
249 {
250 .fourcc = V4L2_PIX_FMT_NV21,
251 .bpp = 12,
252 },
253 {
254 .fourcc = V4L2_PIX_FMT_YUYV,
255 .bpp = 16,
256 },
257};
258
259static const struct ceu_fmt *get_ceu_fmt_from_fourcc(unsigned int fourcc)
260{
261 const struct ceu_fmt *fmt = &ceu_fmt_list[0];
262 unsigned int i;
263
264 for (i = 0; i < ARRAY_SIZE(ceu_fmt_list); i++, fmt++)
265 if (fmt->fourcc == fourcc)
266 return fmt;
267
268 return NULL;
269}
270
271static bool ceu_fmt_mplane(struct v4l2_pix_format_mplane *pix)
272{
273 switch (pix->pixelformat) {
274 case V4L2_PIX_FMT_YUYV:
275 return false;
276 case V4L2_PIX_FMT_NV16:
277 case V4L2_PIX_FMT_NV61:
278 case V4L2_PIX_FMT_NV12:
279 case V4L2_PIX_FMT_NV21:
280 return true;
281 default:
282 return false;
283 }
284}
285
286/* --- CEU HW operations --- */
287
288static void ceu_write(struct ceu_device *priv, unsigned int reg_offs, u32 data)
289{
290 iowrite32(data, priv->base + reg_offs);
291}
292
293static u32 ceu_read(struct ceu_device *priv, unsigned int reg_offs)
294{
295 return ioread32(priv->base + reg_offs);
296}
297
298/*
299 * ceu_soft_reset() - Software reset the CEU interface.
300 * @ceu_device: CEU device.
301 *
302 * Returns 0 for success, -EIO for error.
303 */
304static int ceu_soft_reset(struct ceu_device *ceudev)
305{
306 unsigned int i;
307
308 ceu_write(ceudev, CEU_CAPSR, CEU_CAPSR_CPKIL);
309
310 for (i = 0; i < 100; i++) {
311 if (!(ceu_read(ceudev, CEU_CSTSR) & CEU_CSTRST_CPTON))
312 break;
313 udelay(1);
314 }
315
316 if (i == 100) {
317 dev_err(ceudev->dev, "soft reset time out\n");
318 return -EIO;
319 }
320
321 for (i = 0; i < 100; i++) {
322 if (!(ceu_read(ceudev, CEU_CAPSR) & CEU_CAPSR_CPKIL))
323 return 0;
324 udelay(1);
325 }
326
327 /* If we get here, CEU has not reset properly. */
328 return -EIO;
329}
330
331/* --- CEU Capture Operations --- */
332
333/*
334 * ceu_hw_config() - Configure CEU interface registers.
335 */
336static int ceu_hw_config(struct ceu_device *ceudev)
337{
338 u32 camcr, cdocr, cfzsr, cdwdr, capwr;
339 struct v4l2_pix_format_mplane *pix = &ceudev->v4l2_pix;
340 struct ceu_subdev *ceu_sd = ceudev->sd;
341 struct ceu_mbus_fmt *mbus_fmt = &ceu_sd->mbus_fmt;
342 unsigned int mbus_flags = ceu_sd->mbus_flags;
343
344 /* Start configuring CEU registers */
345 ceu_write(ceudev, CEU_CAIFR, 0);
346 ceu_write(ceudev, CEU_CFWCR, 0);
347 ceu_write(ceudev, CEU_CRCNTR, 0);
348 ceu_write(ceudev, CEU_CRCMPR, 0);
349
350 /* Set the frame capture period for both image capture and data sync. */
351 capwr = (pix->height << 16) | pix->width * mbus_fmt->bpp / 8;
352
353 /*
354 * Swap input data endianness by default.
355 * In data fetch mode bytes are received in chunks of 8 bytes.
356 * D0, D1, D2, D3, D4, D5, D6, D7 (D0 received first)
357 * The data is however by default written to memory in reverse order:
358 * D7, D6, D5, D4, D3, D2, D1, D0 (D7 written to lowest byte)
359 *
360 * Use CEU_CDOCR[2:0] to swap data ordering.
361 */
362 cdocr = CEU_CDOCR_SWAP_ENDIANNESS;
363
364 /*
365 * Configure CAMCR and CDOCR:
366 * match input components ordering with memory output format and
367 * handle downsampling to YUV420.
368 *
369 * If the memory output planar format is 'swapped' (Cr before Cb) and
370 * input format is not, use the swapped version of CAMCR.DTARY.
371 *
372 * If the memory output planar format is not 'swapped' (Cb before Cr)
373 * and input format is, use the swapped version of CAMCR.DTARY.
374 *
375 * CEU by default downsample to planar YUV420 (CDCOR[4] = 0).
376 * If output is planar YUV422 set CDOCR[4] = 1
377 *
378 * No downsample for data fetch sync mode.
379 */
380 switch (pix->pixelformat) {
381 /* Data fetch sync mode */
382 case V4L2_PIX_FMT_YUYV:
383 /* TODO: handle YUYV permutations through DTARY bits. */
384 camcr = CEU_CAMCR_JPEG;
385 cdocr |= CEU_CDOCR_NO_DOWSAMPLE;
386 cfzsr = (pix->height << 16) | pix->width;
387 cdwdr = pix->plane_fmt[0].bytesperline;
388 break;
389
390 /* Non-swapped planar image capture mode. */
391 case V4L2_PIX_FMT_NV16:
392 cdocr |= CEU_CDOCR_NO_DOWSAMPLE;
393 /* fall-through */
394 case V4L2_PIX_FMT_NV12:
395 if (mbus_fmt->swapped)
396 camcr = mbus_fmt->fmt_order_swap;
397 else
398 camcr = mbus_fmt->fmt_order;
399
400 cfzsr = (pix->height << 16) | pix->width;
401 cdwdr = pix->width;
402 break;
403
404 /* Swapped planar image capture mode. */
405 case V4L2_PIX_FMT_NV61:
406 cdocr |= CEU_CDOCR_NO_DOWSAMPLE;
407 /* fall-through */
408 case V4L2_PIX_FMT_NV21:
409 if (mbus_fmt->swapped)
410 camcr = mbus_fmt->fmt_order;
411 else
412 camcr = mbus_fmt->fmt_order_swap;
413
414 cfzsr = (pix->height << 16) | pix->width;
415 cdwdr = pix->width;
416 break;
417
418 default:
419 return -EINVAL;
420 }
421
422 camcr |= mbus_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW ? 1 << 1 : 0;
423 camcr |= mbus_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW ? 1 << 0 : 0;
424
425 /* TODO: handle 16 bit bus width with DTIF bit in CAMCR */
426 ceu_write(ceudev, CEU_CAMCR, camcr);
427 ceu_write(ceudev, CEU_CDOCR, cdocr);
428 ceu_write(ceudev, CEU_CAPCR, CEU_CAPCR_BUS_WIDTH256);
429
430 /*
431 * TODO: make CAMOR offsets configurable.
432 * CAMOR wants to know the number of blanks between a VS/HS signal
433 * and valid data. This value should actually come from the sensor...
434 */
435 ceu_write(ceudev, CEU_CAMOR, 0);
436
437 /* TODO: 16 bit bus width require re-calculation of cdwdr and cfzsr */
438 ceu_write(ceudev, CEU_CAPWR, capwr);
439 ceu_write(ceudev, CEU_CFSZR, cfzsr);
440 ceu_write(ceudev, CEU_CDWDR, cdwdr);
441
442 return 0;
443}
444
445/*
446 * ceu_capture() - Trigger start of a capture sequence.
447 *
448 * Program the CEU DMA registers with addresses where to transfer image data.
449 */
450static int ceu_capture(struct ceu_device *ceudev)
451{
452 struct v4l2_pix_format_mplane *pix = &ceudev->v4l2_pix;
453 dma_addr_t phys_addr_top;
454
455 phys_addr_top =
456 vb2_dma_contig_plane_dma_addr(&ceudev->active->vb2_buf, 0);
457 ceu_write(ceudev, CEU_CDAYR, phys_addr_top);
458
459 /* Ignore CbCr plane for non multi-planar image formats. */
460 if (ceu_fmt_mplane(pix)) {
461 phys_addr_top =
462 vb2_dma_contig_plane_dma_addr(&ceudev->active->vb2_buf,
463 1);
464 ceu_write(ceudev, CEU_CDACR, phys_addr_top);
465 }
466
467 /*
468 * Trigger new capture start: once for each frame, as we work in
469 * one-frame capture mode.
470 */
471 ceu_write(ceudev, CEU_CAPSR, CEU_CAPSR_CE);
472
473 return 0;
474}
475
476static irqreturn_t ceu_irq(int irq, void *data)
477{
478 struct ceu_device *ceudev = data;
479 struct vb2_v4l2_buffer *vbuf;
480 struct ceu_buffer *buf;
481 u32 status;
482
483 /* Clean interrupt status. */
484 status = ceu_read(ceudev, CEU_CETCR);
485 ceu_write(ceudev, CEU_CETCR, ~ceudev->irq_mask);
486
487 /* Unexpected interrupt. */
488 if (!(status & CEU_CEIER_MASK))
489 return IRQ_NONE;
490
491 spin_lock(&ceudev->lock);
492
493 /* Stale interrupt from a released buffer, ignore it. */
494 vbuf = ceudev->active;
495 if (!vbuf) {
496 spin_unlock(&ceudev->lock);
497 return IRQ_HANDLED;
498 }
499
500 /*
501 * When a VBP interrupt occurs, no capture end interrupt will occur
502 * and the image of that frame is not captured correctly.
503 */
504 if (status & CEU_CEIER_VBP) {
505 dev_err(ceudev->dev, "VBP interrupt: abort capture\n");
506 goto error_irq_out;
507 }
508
509 /* Prepare to return the 'previous' buffer. */
510 vbuf->vb2_buf.timestamp = ktime_get_ns();
511 vbuf->sequence = ceudev->sequence++;
512 vbuf->field = ceudev->field;
513
514 /* Prepare a new 'active' buffer and trigger a new capture. */
515 if (!list_empty(&ceudev->capture)) {
516 buf = list_first_entry(&ceudev->capture, struct ceu_buffer,
517 queue);
518 list_del(&buf->queue);
519 ceudev->active = &buf->vb;
520
521 ceu_capture(ceudev);
522 }
523
524 /* Return the 'previous' buffer. */
525 vb2_buffer_done(&vbuf->vb2_buf, VB2_BUF_STATE_DONE);
526
527 spin_unlock(&ceudev->lock);
528
529 return IRQ_HANDLED;
530
531error_irq_out:
532 /* Return the 'previous' buffer and all queued ones. */
533 vb2_buffer_done(&vbuf->vb2_buf, VB2_BUF_STATE_ERROR);
534
535 list_for_each_entry(buf, &ceudev->capture, queue)
536 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
537
538 spin_unlock(&ceudev->lock);
539
540 return IRQ_HANDLED;
541}
542
543/* --- CEU Videobuf2 operations --- */
544
545static void ceu_update_plane_sizes(struct v4l2_plane_pix_format *plane,
546 unsigned int bpl, unsigned int szimage)
547{
548 memset(plane, 0, sizeof(*plane));
549
550 plane->sizeimage = szimage;
551 if (plane->bytesperline < bpl || plane->bytesperline > CEU_MAX_BPL)
552 plane->bytesperline = bpl;
553}
554
555/*
556 * ceu_calc_plane_sizes() - Fill per-plane 'struct v4l2_plane_pix_format'
557 * information according to the currently configured
558 * pixel format.
559 * @ceu_device: CEU device.
560 * @ceu_fmt: Active image format.
561 * @pix: Pixel format information (store line width and image sizes)
562 */
563static void ceu_calc_plane_sizes(struct ceu_device *ceudev,
564 const struct ceu_fmt *ceu_fmt,
565 struct v4l2_pix_format_mplane *pix)
566{
567 unsigned int bpl, szimage;
568
569 switch (pix->pixelformat) {
570 case V4L2_PIX_FMT_YUYV:
571 pix->num_planes = 1;
572 bpl = pix->width * ceu_fmt->bpp / 8;
573 szimage = pix->height * bpl;
574 ceu_update_plane_sizes(&pix->plane_fmt[0], bpl, szimage);
575 break;
576
577 case V4L2_PIX_FMT_NV12:
578 case V4L2_PIX_FMT_NV21:
579 pix->num_planes = 2;
580 bpl = pix->width;
581 szimage = pix->height * pix->width;
582 ceu_update_plane_sizes(&pix->plane_fmt[0], bpl, szimage);
583 ceu_update_plane_sizes(&pix->plane_fmt[1], bpl, szimage / 2);
584 break;
585
586 case V4L2_PIX_FMT_NV16:
587 case V4L2_PIX_FMT_NV61:
588 default:
589 pix->num_planes = 2;
590 bpl = pix->width;
591 szimage = pix->height * pix->width;
592 ceu_update_plane_sizes(&pix->plane_fmt[0], bpl, szimage);
593 ceu_update_plane_sizes(&pix->plane_fmt[1], bpl, szimage);
594 break;
595 }
596}
597
598/*
599 * ceu_vb2_setup() - is called to check whether the driver can accept the
600 * requested number of buffers and to fill in plane sizes
601 * for the current frame format, if required.
602 */
603static int ceu_vb2_setup(struct vb2_queue *vq, unsigned int *count,
604 unsigned int *num_planes, unsigned int sizes[],
605 struct device *alloc_devs[])
606{
607 struct ceu_device *ceudev = vb2_get_drv_priv(vq);
608 struct v4l2_pix_format_mplane *pix = &ceudev->v4l2_pix;
609 unsigned int i;
610
611 /* num_planes is set: just check plane sizes. */
612 if (*num_planes) {
613 for (i = 0; i < pix->num_planes; i++)
614 if (sizes[i] < pix->plane_fmt[i].sizeimage)
615 return -EINVAL;
616
617 return 0;
618 }
619
620 /* num_planes not set: called from REQBUFS, just set plane sizes. */
621 *num_planes = pix->num_planes;
622 for (i = 0; i < pix->num_planes; i++)
623 sizes[i] = pix->plane_fmt[i].sizeimage;
624
625 return 0;
626}
627
628static void ceu_vb2_queue(struct vb2_buffer *vb)
629{
630 struct ceu_device *ceudev = vb2_get_drv_priv(vb->vb2_queue);
631 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
632 struct ceu_buffer *buf = vb2_to_ceu(vbuf);
633 unsigned long irqflags;
634
635 spin_lock_irqsave(&ceudev->lock, irqflags);
636 list_add_tail(&buf->queue, &ceudev->capture);
637 spin_unlock_irqrestore(&ceudev->lock, irqflags);
638}
639
640static int ceu_vb2_prepare(struct vb2_buffer *vb)
641{
642 struct ceu_device *ceudev = vb2_get_drv_priv(vb->vb2_queue);
643 struct v4l2_pix_format_mplane *pix = &ceudev->v4l2_pix;
644 unsigned int i;
645
646 for (i = 0; i < pix->num_planes; i++) {
647 if (vb2_plane_size(vb, i) < pix->plane_fmt[i].sizeimage) {
648 dev_err(ceudev->dev,
649 "Plane size too small (%lu < %u)\n",
650 vb2_plane_size(vb, i),
651 pix->plane_fmt[i].sizeimage);
652 return -EINVAL;
653 }
654
655 vb2_set_plane_payload(vb, i, pix->plane_fmt[i].sizeimage);
656 }
657
658 return 0;
659}
660
661static int ceu_start_streaming(struct vb2_queue *vq, unsigned int count)
662{
663 struct ceu_device *ceudev = vb2_get_drv_priv(vq);
664 struct v4l2_subdev *v4l2_sd = ceudev->sd->v4l2_sd;
665 struct ceu_buffer *buf;
666 unsigned long irqflags;
667 int ret;
668
669 /* Program the CEU interface according to the CEU image format. */
670 ret = ceu_hw_config(ceudev);
671 if (ret)
672 goto error_return_bufs;
673
674 ret = v4l2_subdev_call(v4l2_sd, video, s_stream, 1);
675 if (ret && ret != -ENOIOCTLCMD) {
676 dev_dbg(ceudev->dev,
677 "Subdevice failed to start streaming: %d\n", ret);
678 goto error_return_bufs;
679 }
680
681 spin_lock_irqsave(&ceudev->lock, irqflags);
682 ceudev->sequence = 0;
683
684 /* Grab the first available buffer and trigger the first capture. */
685 buf = list_first_entry(&ceudev->capture, struct ceu_buffer,
686 queue);
687 if (!buf) {
688 spin_unlock_irqrestore(&ceudev->lock, irqflags);
689 dev_dbg(ceudev->dev,
690 "No buffer available for capture.\n");
691 goto error_stop_sensor;
692 }
693
694 list_del(&buf->queue);
695 ceudev->active = &buf->vb;
696
697 /* Clean and program interrupts for first capture. */
698 ceu_write(ceudev, CEU_CETCR, ~ceudev->irq_mask);
699 ceu_write(ceudev, CEU_CEIER, CEU_CEIER_MASK);
700
701 ceu_capture(ceudev);
702
703 spin_unlock_irqrestore(&ceudev->lock, irqflags);
704
705 return 0;
706
707error_stop_sensor:
708 v4l2_subdev_call(v4l2_sd, video, s_stream, 0);
709
710error_return_bufs:
711 spin_lock_irqsave(&ceudev->lock, irqflags);
712 list_for_each_entry(buf, &ceudev->capture, queue)
713 vb2_buffer_done(&ceudev->active->vb2_buf,
714 VB2_BUF_STATE_QUEUED);
715 ceudev->active = NULL;
716 spin_unlock_irqrestore(&ceudev->lock, irqflags);
717
718 return ret;
719}
720
721static void ceu_stop_streaming(struct vb2_queue *vq)
722{
723 struct ceu_device *ceudev = vb2_get_drv_priv(vq);
724 struct v4l2_subdev *v4l2_sd = ceudev->sd->v4l2_sd;
725 struct ceu_buffer *buf;
726 unsigned long irqflags;
727
728 /* Clean and disable interrupt sources. */
729 ceu_write(ceudev, CEU_CETCR,
730 ceu_read(ceudev, CEU_CETCR) & ceudev->irq_mask);
731 ceu_write(ceudev, CEU_CEIER, CEU_CEIER_MASK);
732
733 v4l2_subdev_call(v4l2_sd, video, s_stream, 0);
734
735 spin_lock_irqsave(&ceudev->lock, irqflags);
736 if (ceudev->active) {
737 vb2_buffer_done(&ceudev->active->vb2_buf,
738 VB2_BUF_STATE_ERROR);
739 ceudev->active = NULL;
740 }
741
742 /* Release all queued buffers. */
743 list_for_each_entry(buf, &ceudev->capture, queue)
744 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
745 INIT_LIST_HEAD(&ceudev->capture);
746
747 spin_unlock_irqrestore(&ceudev->lock, irqflags);
748
749 ceu_soft_reset(ceudev);
750}
751
752static const struct vb2_ops ceu_vb2_ops = {
753 .queue_setup = ceu_vb2_setup,
754 .buf_queue = ceu_vb2_queue,
755 .buf_prepare = ceu_vb2_prepare,
756 .wait_prepare = vb2_ops_wait_prepare,
757 .wait_finish = vb2_ops_wait_finish,
758 .start_streaming = ceu_start_streaming,
759 .stop_streaming = ceu_stop_streaming,
760};
761
762/* --- CEU image formats handling --- */
763
764/*
765 * ceu_try_fmt() - test format on CEU and sensor
766 * @ceudev: The CEU device.
767 * @v4l2_fmt: format to test.
768 *
769 * Returns 0 for success, < 0 for errors.
770 */
771static int ceu_try_fmt(struct ceu_device *ceudev, struct v4l2_format *v4l2_fmt)
772{
773 struct ceu_subdev *ceu_sd = ceudev->sd;
774 struct v4l2_pix_format_mplane *pix = &v4l2_fmt->fmt.pix_mp;
775 struct v4l2_subdev *v4l2_sd = ceu_sd->v4l2_sd;
776 struct v4l2_subdev_pad_config pad_cfg;
777 const struct ceu_fmt *ceu_fmt;
778 int ret;
779
780 struct v4l2_subdev_format sd_format = {
781 .which = V4L2_SUBDEV_FORMAT_TRY,
782 };
783
784 switch (pix->pixelformat) {
785 case V4L2_PIX_FMT_YUYV:
786 case V4L2_PIX_FMT_NV16:
787 case V4L2_PIX_FMT_NV61:
788 case V4L2_PIX_FMT_NV12:
789 case V4L2_PIX_FMT_NV21:
790 break;
791
792 default:
793 pix->pixelformat = V4L2_PIX_FMT_NV16;
794 break;
795 }
796
797 ceu_fmt = get_ceu_fmt_from_fourcc(pix->pixelformat);
798
799 /* CFSZR requires height and width to be 4-pixel aligned. */
800 v4l_bound_align_image(&pix->width, 2, CEU_MAX_WIDTH, 4,
801 &pix->height, 4, CEU_MAX_HEIGHT, 4, 0);
802
803 /*
804 * Set format on sensor sub device: bus format used to produce memory
805 * format is selected at initialization time.
806 */
807 v4l2_fill_mbus_format_mplane(&sd_format.format, pix);
808 ret = v4l2_subdev_call(v4l2_sd, pad, set_fmt, &pad_cfg, &sd_format);
809 if (ret)
810 return ret;
811
812 /* Apply size returned by sensor as the CEU can't scale. */
813 v4l2_fill_pix_format_mplane(pix, &sd_format.format);
814
815 /* Calculate per-plane sizes based on image format. */
816 ceu_calc_plane_sizes(ceudev, ceu_fmt, pix);
817
818 return 0;
819}
820
821/*
822 * ceu_set_fmt() - Apply the supplied format to both sensor and CEU
823 */
824static int ceu_set_fmt(struct ceu_device *ceudev, struct v4l2_format *v4l2_fmt)
825{
826 struct ceu_subdev *ceu_sd = ceudev->sd;
827 struct v4l2_subdev *v4l2_sd = ceu_sd->v4l2_sd;
828 int ret;
829
830 struct v4l2_subdev_format format = {
831 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
832 };
833
834 ret = ceu_try_fmt(ceudev, v4l2_fmt);
835 if (ret)
836 return ret;
837
838 v4l2_fill_mbus_format_mplane(&format.format, &v4l2_fmt->fmt.pix_mp);
839 ret = v4l2_subdev_call(v4l2_sd, pad, set_fmt, NULL, &format);
840 if (ret)
841 return ret;
842
843 ceudev->v4l2_pix = v4l2_fmt->fmt.pix_mp;
844 ceudev->field = V4L2_FIELD_NONE;
845
846 return 0;
847}
848
849/*
850 * ceu_set_default_fmt() - Apply default NV16 memory output format with VGA
851 * sizes.
852 */
853static int ceu_set_default_fmt(struct ceu_device *ceudev)
854{
855 int ret;
856
857 struct v4l2_format v4l2_fmt = {
858 .type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
859 .fmt.pix_mp = {
860 .width = VGA_WIDTH,
861 .height = VGA_HEIGHT,
862 .field = V4L2_FIELD_NONE,
863 .pixelformat = V4L2_PIX_FMT_NV16,
864 .num_planes = 2,
865 .plane_fmt = {
866 [0] = {
867 .sizeimage = VGA_WIDTH * VGA_HEIGHT * 2,
868 .bytesperline = VGA_WIDTH * 2,
869 },
870 [1] = {
871 .sizeimage = VGA_WIDTH * VGA_HEIGHT * 2,
872 .bytesperline = VGA_WIDTH * 2,
873 },
874 },
875 },
876 };
877
878 ret = ceu_try_fmt(ceudev, &v4l2_fmt);
879 if (ret)
880 return ret;
881
882 ceudev->v4l2_pix = v4l2_fmt.fmt.pix_mp;
883 ceudev->field = V4L2_FIELD_NONE;
884
885 return 0;
886}
887
888/*
889 * ceu_init_mbus_fmt() - Query sensor for supported formats and initialize
890 * CEU media bus format used to produce memory formats.
891 *
892 * Find out if sensor can produce a permutation of 8-bits YUYV bus format.
893 * From a single 8-bits YUYV bus format the CEU can produce several memory
894 * output formats:
895 * - NV[12|21|16|61] through image fetch mode;
896 * - YUYV422 if sensor provides YUYV422
897 *
898 * TODO: Other YUYV422 permutations through data fetch sync mode and DTARY
899 * TODO: Binary data (eg. JPEG) and raw formats through data fetch sync mode
900 */
901static int ceu_init_mbus_fmt(struct ceu_device *ceudev)
902{
903 struct ceu_subdev *ceu_sd = ceudev->sd;
904 struct ceu_mbus_fmt *mbus_fmt = &ceu_sd->mbus_fmt;
905 struct v4l2_subdev *v4l2_sd = ceu_sd->v4l2_sd;
906 bool yuyv_bus_fmt = false;
907
908 struct v4l2_subdev_mbus_code_enum sd_mbus_fmt = {
909 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
910 .index = 0,
911 };
912
913 /* Find out if sensor can produce any permutation of 8-bits YUYV422. */
914 while (!yuyv_bus_fmt &&
915 !v4l2_subdev_call(v4l2_sd, pad, enum_mbus_code,
916 NULL, &sd_mbus_fmt)) {
917 switch (sd_mbus_fmt.code) {
918 case MEDIA_BUS_FMT_YUYV8_2X8:
919 case MEDIA_BUS_FMT_YVYU8_2X8:
920 case MEDIA_BUS_FMT_UYVY8_2X8:
921 case MEDIA_BUS_FMT_VYUY8_2X8:
922 yuyv_bus_fmt = true;
923 break;
924 default:
925 /*
926 * Only support 8-bits YUYV bus formats at the moment;
927 *
928 * TODO: add support for binary formats (data sync
929 * fetch mode).
930 */
931 break;
932 }
933
934 sd_mbus_fmt.index++;
935 }
936
937 if (!yuyv_bus_fmt)
938 return -ENXIO;
939
940 /*
941 * Save the first encountered YUYV format as "mbus_fmt" and use it
942 * to output all planar YUV422 and YUV420 (NV*) formats to memory as
943 * well as for data synch fetch mode (YUYV - YVYU etc. ).
944 */
945 mbus_fmt->mbus_code = sd_mbus_fmt.code;
946 mbus_fmt->bps = 8;
947
948 /* Annotate the selected bus format components ordering. */
949 switch (sd_mbus_fmt.code) {
950 case MEDIA_BUS_FMT_YUYV8_2X8:
951 mbus_fmt->fmt_order = CEU_CAMCR_DTARY_8_YUYV;
952 mbus_fmt->fmt_order_swap = CEU_CAMCR_DTARY_8_YVYU;
953 mbus_fmt->swapped = false;
954 mbus_fmt->bpp = 16;
955 break;
956
957 case MEDIA_BUS_FMT_YVYU8_2X8:
958 mbus_fmt->fmt_order = CEU_CAMCR_DTARY_8_YVYU;
959 mbus_fmt->fmt_order_swap = CEU_CAMCR_DTARY_8_YUYV;
960 mbus_fmt->swapped = true;
961 mbus_fmt->bpp = 16;
962 break;
963
964 case MEDIA_BUS_FMT_UYVY8_2X8:
965 mbus_fmt->fmt_order = CEU_CAMCR_DTARY_8_UYVY;
966 mbus_fmt->fmt_order_swap = CEU_CAMCR_DTARY_8_VYUY;
967 mbus_fmt->swapped = false;
968 mbus_fmt->bpp = 16;
969 break;
970
971 case MEDIA_BUS_FMT_VYUY8_2X8:
972 mbus_fmt->fmt_order = CEU_CAMCR_DTARY_8_VYUY;
973 mbus_fmt->fmt_order_swap = CEU_CAMCR_DTARY_8_UYVY;
974 mbus_fmt->swapped = true;
975 mbus_fmt->bpp = 16;
976 break;
977 }
978
979 return 0;
980}
981
982/* --- Runtime PM Handlers --- */
983
984/*
985 * ceu_runtime_resume() - soft-reset the interface and turn sensor power on.
986 */
987static int __maybe_unused ceu_runtime_resume(struct device *dev)
988{
989 struct ceu_device *ceudev = dev_get_drvdata(dev);
990 struct v4l2_subdev *v4l2_sd = ceudev->sd->v4l2_sd;
991
992 v4l2_subdev_call(v4l2_sd, core, s_power, 1);
993
994 ceu_soft_reset(ceudev);
995
996 return 0;
997}
998
999/*
1000 * ceu_runtime_suspend() - disable capture and interrupts and soft-reset.
1001 * Turn sensor power off.
1002 */
1003static int __maybe_unused ceu_runtime_suspend(struct device *dev)
1004{
1005 struct ceu_device *ceudev = dev_get_drvdata(dev);
1006 struct v4l2_subdev *v4l2_sd = ceudev->sd->v4l2_sd;
1007
1008 v4l2_subdev_call(v4l2_sd, core, s_power, 0);
1009
1010 ceu_write(ceudev, CEU_CEIER, 0);
1011 ceu_soft_reset(ceudev);
1012
1013 return 0;
1014}
1015
1016/* --- File Operations --- */
1017
1018static int ceu_open(struct file *file)
1019{
1020 struct ceu_device *ceudev = video_drvdata(file);
1021 int ret;
1022
1023 ret = v4l2_fh_open(file);
1024 if (ret)
1025 return ret;
1026
1027 mutex_lock(&ceudev->mlock);
1028 /* Causes soft-reset and sensor power on on first open */
1029 pm_runtime_get_sync(ceudev->dev);
1030 mutex_unlock(&ceudev->mlock);
1031
1032 return 0;
1033}
1034
1035static int ceu_release(struct file *file)
1036{
1037 struct ceu_device *ceudev = video_drvdata(file);
1038
1039 vb2_fop_release(file);
1040
1041 mutex_lock(&ceudev->mlock);
1042 /* Causes soft-reset and sensor power down on last close */
1043 pm_runtime_put(ceudev->dev);
1044 mutex_unlock(&ceudev->mlock);
1045
1046 return 0;
1047}
1048
1049static const struct v4l2_file_operations ceu_fops = {
1050 .owner = THIS_MODULE,
1051 .open = ceu_open,
1052 .release = ceu_release,
1053 .unlocked_ioctl = video_ioctl2,
1054 .mmap = vb2_fop_mmap,
1055 .poll = vb2_fop_poll,
1056};
1057
1058/* --- Video Device IOCTLs --- */
1059
1060static int ceu_querycap(struct file *file, void *priv,
1061 struct v4l2_capability *cap)
1062{
1063 struct ceu_device *ceudev = video_drvdata(file);
1064
1065 strlcpy(cap->card, "Renesas CEU", sizeof(cap->card));
1066 strlcpy(cap->driver, DRIVER_NAME, sizeof(cap->driver));
1067 snprintf(cap->bus_info, sizeof(cap->bus_info),
1068 "platform:renesas-ceu-%s", dev_name(ceudev->dev));
1069
1070 return 0;
1071}
1072
1073static int ceu_enum_fmt_vid_cap(struct file *file, void *priv,
1074 struct v4l2_fmtdesc *f)
1075{
1076 const struct ceu_fmt *fmt;
1077
1078 if (f->index >= ARRAY_SIZE(ceu_fmt_list))
1079 return -EINVAL;
1080
1081 fmt = &ceu_fmt_list[f->index];
1082 f->pixelformat = fmt->fourcc;
1083
1084 return 0;
1085}
1086
1087static int ceu_try_fmt_vid_cap(struct file *file, void *priv,
1088 struct v4l2_format *f)
1089{
1090 struct ceu_device *ceudev = video_drvdata(file);
1091
1092 return ceu_try_fmt(ceudev, f);
1093}
1094
1095static int ceu_s_fmt_vid_cap(struct file *file, void *priv,
1096 struct v4l2_format *f)
1097{
1098 struct ceu_device *ceudev = video_drvdata(file);
1099
1100 if (vb2_is_streaming(&ceudev->vb2_vq))
1101 return -EBUSY;
1102
1103 return ceu_set_fmt(ceudev, f);
1104}
1105
1106static int ceu_g_fmt_vid_cap(struct file *file, void *priv,
1107 struct v4l2_format *f)
1108{
1109 struct ceu_device *ceudev = video_drvdata(file);
1110
1111 f->fmt.pix_mp = ceudev->v4l2_pix;
1112
1113 return 0;
1114}
1115
1116static int ceu_enum_input(struct file *file, void *priv,
1117 struct v4l2_input *inp)
1118{
1119 struct ceu_device *ceudev = video_drvdata(file);
1120 struct ceu_subdev *ceusd;
1121
1122 if (inp->index >= ceudev->num_sd)
1123 return -EINVAL;
1124
1125 ceusd = &ceudev->subdevs[inp->index];
1126
1127 inp->type = V4L2_INPUT_TYPE_CAMERA;
1128 inp->std = 0;
1129 snprintf(inp->name, sizeof(inp->name), "Camera%u: %s",
1130 inp->index, ceusd->v4l2_sd->name);
1131
1132 return 0;
1133}
1134
1135static int ceu_g_input(struct file *file, void *priv, unsigned int *i)
1136{
1137 struct ceu_device *ceudev = video_drvdata(file);
1138
1139 *i = ceudev->sd_index;
1140
1141 return 0;
1142}
1143
1144static int ceu_s_input(struct file *file, void *priv, unsigned int i)
1145{
1146 struct ceu_device *ceudev = video_drvdata(file);
1147 struct ceu_subdev *ceu_sd_old;
1148 int ret;
1149
1150 if (i >= ceudev->num_sd)
1151 return -EINVAL;
1152
1153 if (vb2_is_streaming(&ceudev->vb2_vq))
1154 return -EBUSY;
1155
1156 if (i == ceudev->sd_index)
1157 return 0;
1158
1159 ceu_sd_old = ceudev->sd;
1160 ceudev->sd = &ceudev->subdevs[i];
1161
1162 /*
1163 * Make sure we can generate output image formats and apply
1164 * default one.
1165 */
1166 ret = ceu_init_mbus_fmt(ceudev);
1167 if (ret) {
1168 ceudev->sd = ceu_sd_old;
1169 return -EINVAL;
1170 }
1171
1172 ret = ceu_set_default_fmt(ceudev);
1173 if (ret) {
1174 ceudev->sd = ceu_sd_old;
1175 return -EINVAL;
1176 }
1177
1178 /* Now that we're sure we can use the sensor, power off the old one. */
1179 v4l2_subdev_call(ceu_sd_old->v4l2_sd, core, s_power, 0);
1180 v4l2_subdev_call(ceudev->sd->v4l2_sd, core, s_power, 1);
1181
1182 ceudev->sd_index = i;
1183
1184 return 0;
1185}
1186
1187static int ceu_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
1188{
1189 struct ceu_device *ceudev = video_drvdata(file);
1190
1191 return v4l2_g_parm_cap(video_devdata(file), ceudev->sd->v4l2_sd, a);
1192}
1193
1194static int ceu_s_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
1195{
1196 struct ceu_device *ceudev = video_drvdata(file);
1197
1198 return v4l2_s_parm_cap(video_devdata(file), ceudev->sd->v4l2_sd, a);
1199}
1200
1201static int ceu_enum_framesizes(struct file *file, void *fh,
1202 struct v4l2_frmsizeenum *fsize)
1203{
1204 struct ceu_device *ceudev = video_drvdata(file);
1205 struct ceu_subdev *ceu_sd = ceudev->sd;
1206 const struct ceu_fmt *ceu_fmt;
1207 struct v4l2_subdev *v4l2_sd = ceu_sd->v4l2_sd;
1208 int ret;
1209
1210 struct v4l2_subdev_frame_size_enum fse = {
1211 .code = ceu_sd->mbus_fmt.mbus_code,
1212 .index = fsize->index,
1213 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1214 };
1215
1216 /* Just check if user supplied pixel format is supported. */
1217 ceu_fmt = get_ceu_fmt_from_fourcc(fsize->pixel_format);
1218 if (!ceu_fmt)
1219 return -EINVAL;
1220
1221 ret = v4l2_subdev_call(v4l2_sd, pad, enum_frame_size,
1222 NULL, &fse);
1223 if (ret)
1224 return ret;
1225
1226 fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
1227 fsize->discrete.width = CEU_W_MAX(fse.max_width);
1228 fsize->discrete.height = CEU_H_MAX(fse.max_height);
1229
1230 return 0;
1231}
1232
1233static int ceu_enum_frameintervals(struct file *file, void *fh,
1234 struct v4l2_frmivalenum *fival)
1235{
1236 struct ceu_device *ceudev = video_drvdata(file);
1237 struct ceu_subdev *ceu_sd = ceudev->sd;
1238 const struct ceu_fmt *ceu_fmt;
1239 struct v4l2_subdev *v4l2_sd = ceu_sd->v4l2_sd;
1240 int ret;
1241
1242 struct v4l2_subdev_frame_interval_enum fie = {
1243 .code = ceu_sd->mbus_fmt.mbus_code,
1244 .index = fival->index,
1245 .width = fival->width,
1246 .height = fival->height,
1247 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1248 };
1249
1250 /* Just check if user supplied pixel format is supported. */
1251 ceu_fmt = get_ceu_fmt_from_fourcc(fival->pixel_format);
1252 if (!ceu_fmt)
1253 return -EINVAL;
1254
1255 ret = v4l2_subdev_call(v4l2_sd, pad, enum_frame_interval, NULL,
1256 &fie);
1257 if (ret)
1258 return ret;
1259
1260 fival->type = V4L2_FRMIVAL_TYPE_DISCRETE;
1261 fival->discrete = fie.interval;
1262
1263 return 0;
1264}
1265
1266static const struct v4l2_ioctl_ops ceu_ioctl_ops = {
1267 .vidioc_querycap = ceu_querycap,
1268
1269 .vidioc_enum_fmt_vid_cap_mplane = ceu_enum_fmt_vid_cap,
1270 .vidioc_try_fmt_vid_cap_mplane = ceu_try_fmt_vid_cap,
1271 .vidioc_s_fmt_vid_cap_mplane = ceu_s_fmt_vid_cap,
1272 .vidioc_g_fmt_vid_cap_mplane = ceu_g_fmt_vid_cap,
1273
1274 .vidioc_enum_input = ceu_enum_input,
1275 .vidioc_g_input = ceu_g_input,
1276 .vidioc_s_input = ceu_s_input,
1277
1278 .vidioc_reqbufs = vb2_ioctl_reqbufs,
1279 .vidioc_querybuf = vb2_ioctl_querybuf,
1280 .vidioc_qbuf = vb2_ioctl_qbuf,
1281 .vidioc_expbuf = vb2_ioctl_expbuf,
1282 .vidioc_dqbuf = vb2_ioctl_dqbuf,
1283 .vidioc_create_bufs = vb2_ioctl_create_bufs,
1284 .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
1285 .vidioc_streamon = vb2_ioctl_streamon,
1286 .vidioc_streamoff = vb2_ioctl_streamoff,
1287
1288 .vidioc_g_parm = ceu_g_parm,
1289 .vidioc_s_parm = ceu_s_parm,
1290 .vidioc_enum_framesizes = ceu_enum_framesizes,
1291 .vidioc_enum_frameintervals = ceu_enum_frameintervals,
1292
1293 .vidioc_log_status = v4l2_ctrl_log_status,
1294 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1295 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1296};
1297
1298/*
1299 * ceu_vdev_release() - release CEU video device memory when last reference
1300 * to this driver is closed
1301 */
1302static void ceu_vdev_release(struct video_device *vdev)
1303{
1304 struct ceu_device *ceudev = video_get_drvdata(vdev);
1305
1306 kfree(ceudev);
1307}
1308
1309static int ceu_notify_bound(struct v4l2_async_notifier *notifier,
1310 struct v4l2_subdev *v4l2_sd,
1311 struct v4l2_async_subdev *asd)
1312{
1313 struct v4l2_device *v4l2_dev = notifier->v4l2_dev;
1314 struct ceu_device *ceudev = v4l2_to_ceu(v4l2_dev);
1315 struct ceu_subdev *ceu_sd = to_ceu_subdev(asd);
1316
1317 ceu_sd->v4l2_sd = v4l2_sd;
1318 ceudev->num_sd++;
1319
1320 return 0;
1321}
1322
1323static int ceu_notify_complete(struct v4l2_async_notifier *notifier)
1324{
1325 struct v4l2_device *v4l2_dev = notifier->v4l2_dev;
1326 struct ceu_device *ceudev = v4l2_to_ceu(v4l2_dev);
1327 struct video_device *vdev = &ceudev->vdev;
1328 struct vb2_queue *q = &ceudev->vb2_vq;
1329 struct v4l2_subdev *v4l2_sd;
1330 int ret;
1331
1332 /* Initialize vb2 queue. */
1333 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
1334 q->io_modes = VB2_MMAP | VB2_DMABUF;
1335 q->drv_priv = ceudev;
1336 q->ops = &ceu_vb2_ops;
1337 q->mem_ops = &vb2_dma_contig_memops;
1338 q->buf_struct_size = sizeof(struct ceu_buffer);
1339 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1340 q->min_buffers_needed = 2;
1341 q->lock = &ceudev->mlock;
1342 q->dev = ceudev->v4l2_dev.dev;
1343
1344 ret = vb2_queue_init(q);
1345 if (ret)
1346 return ret;
1347
1348 /*
1349 * Make sure at least one sensor is primary and use it to initialize
1350 * ceu formats.
1351 */
1352 if (!ceudev->sd) {
1353 ceudev->sd = &ceudev->subdevs[0];
1354 ceudev->sd_index = 0;
1355 }
1356
1357 v4l2_sd = ceudev->sd->v4l2_sd;
1358
1359 ret = ceu_init_mbus_fmt(ceudev);
1360 if (ret)
1361 return ret;
1362
1363 ret = ceu_set_default_fmt(ceudev);
1364 if (ret)
1365 return ret;
1366
1367 /* Register the video device. */
1368 strncpy(vdev->name, DRIVER_NAME, strlen(DRIVER_NAME));
1369 vdev->v4l2_dev = v4l2_dev;
1370 vdev->lock = &ceudev->mlock;
1371 vdev->queue = &ceudev->vb2_vq;
1372 vdev->ctrl_handler = v4l2_sd->ctrl_handler;
1373 vdev->fops = &ceu_fops;
1374 vdev->ioctl_ops = &ceu_ioctl_ops;
1375 vdev->release = ceu_vdev_release;
1376 vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE_MPLANE |
1377 V4L2_CAP_STREAMING;
1378 video_set_drvdata(vdev, ceudev);
1379
1380 ret = video_register_device(vdev, VFL_TYPE_GRABBER, -1);
1381 if (ret < 0) {
1382 v4l2_err(vdev->v4l2_dev,
1383 "video_register_device failed: %d\n", ret);
1384 return ret;
1385 }
1386
1387 return 0;
1388}
1389
1390static const struct v4l2_async_notifier_operations ceu_notify_ops = {
1391 .bound = ceu_notify_bound,
1392 .complete = ceu_notify_complete,
1393};
1394
1395/*
1396 * ceu_init_async_subdevs() - Initialize CEU subdevices and async_subdevs in
1397 * ceu device. Both DT and platform data parsing use
1398 * this routine.
1399 *
1400 * Returns 0 for success, -ENOMEM for failure.
1401 */
1402static int ceu_init_async_subdevs(struct ceu_device *ceudev, unsigned int n_sd)
1403{
1404 /* Reserve memory for 'n_sd' ceu_subdev descriptors. */
1405 ceudev->subdevs = devm_kcalloc(ceudev->dev, n_sd,
1406 sizeof(*ceudev->subdevs), GFP_KERNEL);
1407 if (!ceudev->subdevs)
1408 return -ENOMEM;
1409
1410 /*
1411 * Reserve memory for 'n_sd' pointers to async_subdevices.
1412 * ceudev->asds members will point to &ceu_subdev.asd
1413 */
1414 ceudev->asds = devm_kcalloc(ceudev->dev, n_sd,
1415 sizeof(*ceudev->asds), GFP_KERNEL);
1416 if (!ceudev->asds)
1417 return -ENOMEM;
1418
1419 ceudev->sd = NULL;
1420 ceudev->sd_index = 0;
1421 ceudev->num_sd = 0;
1422
1423 return 0;
1424}
1425
1426/*
1427 * ceu_parse_platform_data() - Initialize async_subdevices using platform
1428 * device provided data.
1429 */
1430static int ceu_parse_platform_data(struct ceu_device *ceudev,
1431 const struct ceu_platform_data *pdata)
1432{
1433 const struct ceu_async_subdev *async_sd;
1434 struct ceu_subdev *ceu_sd;
1435 unsigned int i;
1436 int ret;
1437
1438 if (pdata->num_subdevs == 0)
1439 return -ENODEV;
1440
1441 ret = ceu_init_async_subdevs(ceudev, pdata->num_subdevs);
1442 if (ret)
1443 return ret;
1444
1445 for (i = 0; i < pdata->num_subdevs; i++) {
1446 /* Setup the ceu subdevice and the async subdevice. */
1447 async_sd = &pdata->subdevs[i];
1448 ceu_sd = &ceudev->subdevs[i];
1449
1450 INIT_LIST_HEAD(&ceu_sd->asd.list);
1451
1452 ceu_sd->mbus_flags = async_sd->flags;
1453 ceu_sd->asd.match_type = V4L2_ASYNC_MATCH_I2C;
1454 ceu_sd->asd.match.i2c.adapter_id = async_sd->i2c_adapter_id;
1455 ceu_sd->asd.match.i2c.address = async_sd->i2c_address;
1456
1457 ceudev->asds[i] = &ceu_sd->asd;
1458 }
1459
1460 return pdata->num_subdevs;
1461}
1462
1463/*
1464 * ceu_parse_dt() - Initialize async_subdevs parsing device tree graph.
1465 */
1466static int ceu_parse_dt(struct ceu_device *ceudev)
1467{
1468 struct device_node *of = ceudev->dev->of_node;
1469 struct v4l2_fwnode_endpoint fw_ep;
1470 struct ceu_subdev *ceu_sd;
1471 struct device_node *ep;
1472 unsigned int i;
1473 int num_ep;
1474 int ret;
1475
1476 num_ep = of_graph_get_endpoint_count(of);
1477 if (!num_ep)
1478 return -ENODEV;
1479
1480 ret = ceu_init_async_subdevs(ceudev, num_ep);
1481 if (ret)
1482 return ret;
1483
1484 for (i = 0; i < num_ep; i++) {
1485 ep = of_graph_get_endpoint_by_regs(of, 0, i);
1486 if (!ep) {
1487 dev_err(ceudev->dev,
1488 "No subdevice connected on endpoint %u.\n", i);
1489 ret = -ENODEV;
1490 goto error_put_node;
1491 }
1492
1493 ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep), &fw_ep);
1494 if (ret) {
1495 dev_err(ceudev->dev,
1496 "Unable to parse endpoint #%u.\n", i);
1497 goto error_put_node;
1498 }
1499
1500 if (fw_ep.bus_type != V4L2_MBUS_PARALLEL) {
1501 dev_err(ceudev->dev,
1502 "Only parallel input supported.\n");
1503 ret = -EINVAL;
1504 goto error_put_node;
1505 }
1506
1507 /* Setup the ceu subdevice and the async subdevice. */
1508 ceu_sd = &ceudev->subdevs[i];
1509 INIT_LIST_HEAD(&ceu_sd->asd.list);
1510
1511 ceu_sd->mbus_flags = fw_ep.bus.parallel.flags;
1512 ceu_sd->asd.match_type = V4L2_ASYNC_MATCH_FWNODE;
1513 ceu_sd->asd.match.fwnode =
1514 fwnode_graph_get_remote_port_parent(
1515 of_fwnode_handle(ep));
1516
1517 ceudev->asds[i] = &ceu_sd->asd;
1518 of_node_put(ep);
1519 }
1520
1521 return num_ep;
1522
1523error_put_node:
1524 of_node_put(ep);
1525 return ret;
1526}
1527
1528/*
1529 * struct ceu_data - Platform specific CEU data
1530 * @irq_mask: CETCR mask with all interrupt sources enabled. The mask differs
1531 * between SH4 and RZ platforms.
1532 */
1533struct ceu_data {
1534 u32 irq_mask;
1535};
1536
1537static const struct ceu_data ceu_data_rz = {
1538 .irq_mask = CEU_CETCR_ALL_IRQS_RZ,
1539};
1540
1541static const struct ceu_data ceu_data_sh4 = {
1542 .irq_mask = CEU_CETCR_ALL_IRQS_SH4,
1543};
1544
1545#if IS_ENABLED(CONFIG_OF)
1546static const struct of_device_id ceu_of_match[] = {
1547 { .compatible = "renesas,r7s72100-ceu", .data = &ceu_data_rz },
1548 { }
1549};
1550MODULE_DEVICE_TABLE(of, ceu_of_match);
1551#endif
1552
1553static int ceu_probe(struct platform_device *pdev)
1554{
1555 struct device *dev = &pdev->dev;
1556 const struct ceu_data *ceu_data;
1557 struct ceu_device *ceudev;
1558 struct resource *res;
1559 unsigned int irq;
1560 int num_subdevs;
1561 int ret;
1562
1563 ceudev = kzalloc(sizeof(*ceudev), GFP_KERNEL);
1564 if (!ceudev)
1565 return -ENOMEM;
1566
1567 platform_set_drvdata(pdev, ceudev);
1568 ceudev->dev = dev;
1569
1570 INIT_LIST_HEAD(&ceudev->capture);
1571 spin_lock_init(&ceudev->lock);
1572 mutex_init(&ceudev->mlock);
1573
1574 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1575 ceudev->base = devm_ioremap_resource(dev, res);
1576 if (IS_ERR(ceudev->base)) {
1577 ret = PTR_ERR(ceudev->base);
1578 goto error_free_ceudev;
1579 }
1580
1581 ret = platform_get_irq(pdev, 0);
1582 if (ret < 0) {
1583 dev_err(dev, "Failed to get irq: %d\n", ret);
1584 goto error_free_ceudev;
1585 }
1586 irq = ret;
1587
1588 ret = devm_request_irq(dev, irq, ceu_irq,
1589 0, dev_name(dev), ceudev);
1590 if (ret) {
1591 dev_err(&pdev->dev, "Unable to request CEU interrupt.\n");
1592 goto error_free_ceudev;
1593 }
1594
1595 pm_runtime_enable(dev);
1596
1597 ret = v4l2_device_register(dev, &ceudev->v4l2_dev);
1598 if (ret)
1599 goto error_pm_disable;
1600
1601 if (IS_ENABLED(CONFIG_OF) && dev->of_node) {
1602 ceu_data = of_match_device(ceu_of_match, dev)->data;
1603 num_subdevs = ceu_parse_dt(ceudev);
1604 } else if (dev->platform_data) {
1605 /* Assume SH4 if booting with platform data. */
1606 ceu_data = &ceu_data_sh4;
1607 num_subdevs = ceu_parse_platform_data(ceudev,
1608 dev->platform_data);
1609 } else {
1610 num_subdevs = -EINVAL;
1611 }
1612
1613 if (num_subdevs < 0) {
1614 ret = num_subdevs;
1615 goto error_v4l2_unregister;
1616 }
1617 ceudev->irq_mask = ceu_data->irq_mask;
1618
1619 ceudev->notifier.v4l2_dev = &ceudev->v4l2_dev;
1620 ceudev->notifier.subdevs = ceudev->asds;
1621 ceudev->notifier.num_subdevs = num_subdevs;
1622 ceudev->notifier.ops = &ceu_notify_ops;
1623 ret = v4l2_async_notifier_register(&ceudev->v4l2_dev,
1624 &ceudev->notifier);
1625 if (ret)
1626 goto error_v4l2_unregister;
1627
1628 dev_info(dev, "Renesas Capture Engine Unit %s\n", dev_name(dev));
1629
1630 return 0;
1631
1632error_v4l2_unregister:
1633 v4l2_device_unregister(&ceudev->v4l2_dev);
1634error_pm_disable:
1635 pm_runtime_disable(dev);
1636error_free_ceudev:
1637 kfree(ceudev);
1638
1639 return ret;
1640}
1641
1642static int ceu_remove(struct platform_device *pdev)
1643{
1644 struct ceu_device *ceudev = platform_get_drvdata(pdev);
1645
1646 pm_runtime_disable(ceudev->dev);
1647
1648 v4l2_async_notifier_unregister(&ceudev->notifier);
1649
1650 v4l2_device_unregister(&ceudev->v4l2_dev);
1651
1652 video_unregister_device(&ceudev->vdev);
1653
1654 return 0;
1655}
1656
1657static const struct dev_pm_ops ceu_pm_ops = {
1658 SET_RUNTIME_PM_OPS(ceu_runtime_suspend,
1659 ceu_runtime_resume,
1660 NULL)
1661};
1662
1663static struct platform_driver ceu_driver = {
1664 .driver = {
1665 .name = DRIVER_NAME,
1666 .pm = &ceu_pm_ops,
1667 .of_match_table = of_match_ptr(ceu_of_match),
1668 },
1669 .probe = ceu_probe,
1670 .remove = ceu_remove,
1671};
1672
1673module_platform_driver(ceu_driver);
1674
1675MODULE_DESCRIPTION("Renesas CEU camera driver");
1676MODULE_AUTHOR("Jacopo Mondi <jacopo+renesas@jmondi.org>");
1677MODULE_LICENSE("GPL v2");
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-27 09:02:34 -0400