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Diffstat (limited to 'drivers/media/platform/exynos4-is/fimc-is-regs.h')
-rw-r--r--drivers/media/platform/exynos4-is/fimc-is-regs.h164
1 files changed, 164 insertions, 0 deletions
diff --git a/drivers/media/platform/exynos4-is/fimc-is-regs.h b/drivers/media/platform/exynos4-is/fimc-is-regs.h
new file mode 100644
index 000000000000..5fa2fda46742
--- /dev/null
+++ b/drivers/media/platform/exynos4-is/fimc-is-regs.h
@@ -0,0 +1,164 @@
1/*
2 * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
3 *
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 *
6 * Authors: Sylwester Nawrocki <s.nawrocki@samsung.com>
7 * Younghwan Joo <yhwan.joo@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#ifndef FIMC_IS_REG_H_
14#define FIMC_IS_REG_H_
15
16/* WDT_ISP register */
17#define REG_WDT_ISP 0x00170000
18
19/* MCUCTL registers base offset */
20#define MCUCTL_BASE 0x00180000
21
22/* MCU Controller Register */
23#define MCUCTL_REG_MCUCTRL (MCUCTL_BASE + 0x00)
24#define MCUCTRL_MSWRST (1 << 0)
25
26/* Boot Base Offset Address Register */
27#define MCUCTL_REG_BBOAR (MCUCTL_BASE + 0x04)
28
29/* Interrupt Generation Register 0 from Host CPU to VIC */
30#define MCUCTL_REG_INTGR0 (MCUCTL_BASE + 0x08)
31/* __n = 0...9 */
32#define INTGR0_INTGC(__n) (1 << ((__n) + 16))
33/* __n = 0...5 */
34#define INTGR0_INTGD(__n) (1 << (__n))
35
36/* Interrupt Clear Register 0 from Host CPU to VIC */
37#define MCUCTL_REG_INTCR0 (MCUCTL_BASE + 0x0c)
38/* __n = 0...9 */
39#define INTCR0_INTGC(__n) (1 << ((__n) + 16))
40/* __n = 0...5 */
41#define INTCR0_INTCD(__n) (1 << ((__n) + 16))
42
43/* Interrupt Mask Register 0 from Host CPU to VIC */
44#define MCUCTL_REG_INTMR0 (MCUCTL_BASE + 0x10)
45/* __n = 0...9 */
46#define INTMR0_INTMC(__n) (1 << ((__n) + 16))
47/* __n = 0...5 */
48#define INTMR0_INTMD(__n) (1 << (__n))
49
50/* Interrupt Status Register 0 from Host CPU to VIC */
51#define MCUCTL_REG_INTSR0 (MCUCTL_BASE + 0x14)
52/* __n (bit number) = 0...4 */
53#define INTSR0_GET_INTSD(x, __n) (((x) >> (__n)) & 0x1)
54/* __n (bit number) = 0...9 */
55#define INTSR0_GET_INTSC(x, __n) (((x) >> ((__n) + 16)) & 0x1)
56
57/* Interrupt Mask Status Register 0 from Host CPU to VIC */
58#define MCUCTL_REG_INTMSR0 (MCUCTL_BASE + 0x18)
59/* __n (bit number) = 0...4 */
60#define INTMSR0_GET_INTMSD(x, __n) (((x) >> (__n)) & 0x1)
61/* __n (bit number) = 0...9 */
62#define INTMSR0_GET_INTMSC(x, __n) (((x) >> ((__n) + 16)) & 0x1)
63
64/* Interrupt Generation Register 1 from ISP CPU to Host IC */
65#define MCUCTL_REG_INTGR1 (MCUCTL_BASE + 0x1c)
66/* __n = 0...9 */
67#define INTGR1_INTGC(__n) (1 << (__n))
68
69/* Interrupt Clear Register 1 from ISP CPU to Host IC */
70#define MCUCTL_REG_INTCR1 (MCUCTL_BASE + 0x20)
71/* __n = 0...9 */
72#define INTCR1_INTCC(__n) (1 << (__n))
73
74/* Interrupt Mask Register 1 from ISP CPU to Host IC */
75#define MCUCTL_REG_INTMR1 (MCUCTL_BASE + 0x24)
76/* __n = 0...9 */
77#define INTMR1_INTMC(__n) (1 << (__n))
78
79/* Interrupt Status Register 1 from ISP CPU to Host IC */
80#define MCUCTL_REG_INTSR1 (MCUCTL_BASE + 0x28)
81/* Interrupt Mask Status Register 1 from ISP CPU to Host IC */
82#define MCUCTL_REG_INTMSR1 (MCUCTL_BASE + 0x2c)
83
84/* Interrupt Clear Register 2 from ISP BLK's interrupts to Host IC */
85#define MCUCTL_REG_INTCR2 (MCUCTL_BASE + 0x30)
86/* __n = 0...5 */
87#define INTCR2_INTCC(__n) (1 << ((__n) + 16))
88
89/* Interrupt Mask Register 2 from ISP BLK's interrupts to Host IC */
90#define MCUCTL_REG_INTMR2 (MCUCTL_BASE + 0x34)
91/* __n = 0...25 */
92#define INTMR2_INTMCIS(__n) (1 << (__n))
93
94/* Interrupt Status Register 2 from ISP BLK's interrupts to Host IC */
95#define MCUCTL_REG_INTSR2 (MCUCTL_BASE + 0x38)
96/* Interrupt Mask Status Register 2 from ISP BLK's interrupts to Host IC */
97#define MCUCTL_REG_INTMSR2 (MCUCTL_BASE + 0x3c)
98
99/* General Purpose Output Control Register (0~17) */
100#define MCUCTL_REG_GPOCTLR (MCUCTL_BASE + 0x40)
101/* __n = 0...17 */
102#define GPOCTLR_GPOG(__n) (1 << (__n))
103
104/* General Purpose Pad Output Enable Register (0~17) */
105#define MCUCTL_REG_GPOENCTLR (MCUCTL_BASE + 0x44)
106/* __n = 0...17 */
107#define GPOENCTLR_GPOEN(__n) (1 << (__n))
108
109/* General Purpose Input Control Register (0~17) */
110#define MCUCTL_REG_GPICTLR (MCUCTL_BASE + 0x48)
111
112/* Shared registers between ISP CPU and the host CPU - ISSRxx */
113
114/* ISSR(1): Command Host -> IS */
115/* ISSR(1): Sensor ID for Command, ISSR2...5 = Parameter 1...4 */
116
117/* ISSR(10): Reply IS -> Host */
118/* ISSR(11): Sensor ID for Reply, ISSR12...15 = Parameter 1...4 */
119
120/* ISSR(20): ISP_FRAME_DONE : SENSOR ID */
121/* ISSR(21): ISP_FRAME_DONE : PARAMETER 1 */
122
123/* ISSR(24): SCALERC_FRAME_DONE : SENSOR ID */
124/* ISSR(25): SCALERC_FRAME_DONE : PARAMETER 1 */
125
126/* ISSR(28): 3DNR_FRAME_DONE : SENSOR ID */
127/* ISSR(29): 3DNR_FRAME_DONE : PARAMETER 1 */
128
129/* ISSR(32): SCALERP_FRAME_DONE : SENSOR ID */
130/* ISSR(33): SCALERP_FRAME_DONE : PARAMETER 1 */
131
132/* __n = 0...63 */
133#define MCUCTL_REG_ISSR(__n) (MCUCTL_BASE + 0x80 + ((__n) * 4))
134
135/* PMU ISP register offsets */
136#define REG_CMU_RESET_ISP_SYS_PWR_REG 0x1174
137#define REG_CMU_SYSCLK_ISP_SYS_PWR_REG 0x13b8
138#define REG_PMU_ISP_ARM_SYS 0x1050
139#define REG_PMU_ISP_ARM_CONFIGURATION 0x2280
140#define REG_PMU_ISP_ARM_STATUS 0x2284
141#define REG_PMU_ISP_ARM_OPTION 0x2288
142
143void fimc_is_fw_clear_irq1(struct fimc_is *is, unsigned int bit);
144void fimc_is_fw_clear_irq2(struct fimc_is *is);
145int fimc_is_hw_get_params(struct fimc_is *is, unsigned int num);
146
147void fimc_is_hw_set_intgr0_gd0(struct fimc_is *is);
148int fimc_is_hw_wait_intsr0_intsd0(struct fimc_is *is);
149int fimc_is_hw_wait_intmsr0_intmsd0(struct fimc_is *is);
150void fimc_is_hw_set_sensor_num(struct fimc_is *is);
151void fimc_is_hw_stream_on(struct fimc_is *is);
152void fimc_is_hw_stream_off(struct fimc_is *is);
153int fimc_is_hw_set_param(struct fimc_is *is);
154int fimc_is_hw_change_mode(struct fimc_is *is);
155
156void fimc_is_hw_close_sensor(struct fimc_is *is, unsigned int index);
157void fimc_is_hw_get_setfile_addr(struct fimc_is *is);
158void fimc_is_hw_load_setfile(struct fimc_is *is);
159void fimc_is_hw_subip_power_off(struct fimc_is *is);
160
161int fimc_is_itf_s_param(struct fimc_is *is, bool update);
162int fimc_is_itf_mode_change(struct fimc_is *is);
163
164#endif /* FIMC_IS_REG_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-23 18:43:37 -0500