diff options
Diffstat (limited to 'drivers/media/pci/dt3155/dt3155.h')
| -rw-r--r-- | drivers/media/pci/dt3155/dt3155.h | 196 |
1 files changed, 196 insertions, 0 deletions
diff --git a/drivers/media/pci/dt3155/dt3155.h b/drivers/media/pci/dt3155/dt3155.h new file mode 100644 index 000000000000..4e1f4d598d57 --- /dev/null +++ b/drivers/media/pci/dt3155/dt3155.h | |||
| @@ -0,0 +1,196 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * Copyright (C) 2006-2010 by Marin Mitov * | ||
| 3 | * mitov@issp.bas.bg * | ||
| 4 | * * | ||
| 5 | * This program is free software; you can redistribute it and/or modify * | ||
| 6 | * it under the terms of the GNU General Public License as published by * | ||
| 7 | * the Free Software Foundation; either version 2 of the License, or * | ||
| 8 | * (at your option) any later version. * | ||
| 9 | * * | ||
| 10 | * This program is distributed in the hope that it will be useful, * | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of * | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * | ||
| 13 | * GNU General Public License for more details. * | ||
| 14 | * * | ||
| 15 | ***************************************************************************/ | ||
| 16 | |||
| 17 | /* DT3155 header file */ | ||
| 18 | #ifndef _DT3155_H_ | ||
| 19 | #define _DT3155_H_ | ||
| 20 | |||
| 21 | #include <linux/pci.h> | ||
| 22 | #include <linux/interrupt.h> | ||
| 23 | #include <media/v4l2-device.h> | ||
| 24 | #include <media/v4l2-dev.h> | ||
| 25 | |||
| 26 | #define DT3155_NAME "dt3155" | ||
| 27 | #define DT3155_VER_MAJ 2 | ||
| 28 | #define DT3155_VER_MIN 0 | ||
| 29 | #define DT3155_VER_EXT 0 | ||
| 30 | #define DT3155_VERSION __stringify(DT3155_VER_MAJ) "." \ | ||
| 31 | __stringify(DT3155_VER_MIN) "." \ | ||
| 32 | __stringify(DT3155_VER_EXT) | ||
| 33 | |||
| 34 | /* DT3155 Base Register offsets (memory mapped) */ | ||
| 35 | #define EVEN_DMA_START 0x00 | ||
| 36 | #define ODD_DMA_START 0x0C | ||
| 37 | #define EVEN_DMA_STRIDE 0x18 | ||
| 38 | #define ODD_DMA_STRIDE 0x24 | ||
| 39 | #define EVEN_PIXEL_FMT 0x30 | ||
| 40 | #define ODD_PIXEL_FMT 0x34 | ||
| 41 | #define FIFO_TRIGER 0x38 | ||
| 42 | #define XFER_MODE 0x3C | ||
| 43 | #define CSR1 0x40 | ||
| 44 | #define RETRY_WAIT_CNT 0x44 | ||
| 45 | #define INT_CSR 0x48 | ||
| 46 | #define EVEN_FLD_MASK 0x4C | ||
| 47 | #define ODD_FLD_MASK 0x50 | ||
| 48 | #define MASK_LENGTH 0x54 | ||
| 49 | #define FIFO_FLAG_CNT 0x58 | ||
| 50 | #define IIC_CLK_DUR 0x5C | ||
| 51 | #define IIC_CSR1 0x60 | ||
| 52 | #define IIC_CSR2 0x64 | ||
| 53 | |||
| 54 | /* DT3155 Internal Registers indexes (i2c/IIC mapped) */ | ||
| 55 | #define CSR2 0x10 | ||
| 56 | #define EVEN_CSR 0x11 | ||
| 57 | #define ODD_CSR 0x12 | ||
| 58 | #define CONFIG 0x13 | ||
| 59 | #define DT_ID 0x1F | ||
| 60 | #define X_CLIP_START 0x20 | ||
| 61 | #define Y_CLIP_START 0x22 | ||
| 62 | #define X_CLIP_END 0x24 | ||
| 63 | #define Y_CLIP_END 0x26 | ||
| 64 | #define AD_ADDR 0x30 | ||
| 65 | #define AD_LUT 0x31 | ||
| 66 | #define AD_CMD 0x32 | ||
| 67 | #define DIG_OUT 0x40 | ||
| 68 | #define PM_LUT_ADDR 0x50 | ||
| 69 | #define PM_LUT_DATA 0x51 | ||
| 70 | |||
| 71 | /* AD command register values */ | ||
| 72 | #define AD_CMD_REG 0x00 | ||
| 73 | #define AD_POS_REF 0x01 | ||
| 74 | #define AD_NEG_REF 0x02 | ||
| 75 | |||
| 76 | /* CSR1 bit masks */ | ||
| 77 | #define RANGE_EN 0x00008000 | ||
| 78 | #define CRPT_DIS 0x00004000 | ||
| 79 | #define ADDR_ERR_ODD 0x00000800 | ||
| 80 | #define ADDR_ERR_EVEN 0x00000400 | ||
| 81 | #define FLD_CRPT_ODD 0x00000200 | ||
| 82 | #define FLD_CRPT_EVEN 0x00000100 | ||
| 83 | #define FIFO_EN 0x00000080 | ||
| 84 | #define SRST 0x00000040 | ||
| 85 | #define FLD_DN_ODD 0x00000020 | ||
| 86 | #define FLD_DN_EVEN 0x00000010 | ||
| 87 | /* These should not be used. | ||
| 88 | * Use CAP_CONT_ODD/EVEN instead | ||
| 89 | #define CAP_SNGL_ODD 0x00000008 | ||
| 90 | #define CAP_SNGL_EVEN 0x00000004 | ||
| 91 | */ | ||
| 92 | #define CAP_CONT_ODD 0x00000002 | ||
| 93 | #define CAP_CONT_EVEN 0x00000001 | ||
| 94 | |||
| 95 | /* INT_CSR bit masks */ | ||
| 96 | #define FLD_START_EN 0x00000400 | ||
| 97 | #define FLD_END_ODD_EN 0x00000200 | ||
| 98 | #define FLD_END_EVEN_EN 0x00000100 | ||
| 99 | #define FLD_START 0x00000004 | ||
| 100 | #define FLD_END_ODD 0x00000002 | ||
| 101 | #define FLD_END_EVEN 0x00000001 | ||
| 102 | |||
| 103 | /* IIC_CSR1 bit masks */ | ||
| 104 | #define DIRECT_ABORT 0x00000200 | ||
| 105 | |||
| 106 | /* IIC_CSR2 bit masks */ | ||
| 107 | #define NEW_CYCLE 0x01000000 | ||
| 108 | #define DIR_RD 0x00010000 | ||
| 109 | #define IIC_READ 0x01010000 | ||
| 110 | #define IIC_WRITE 0x01000000 | ||
| 111 | |||
| 112 | /* CSR2 bit masks */ | ||
| 113 | #define DISP_PASS 0x40 | ||
| 114 | #define BUSY_ODD 0x20 | ||
| 115 | #define BUSY_EVEN 0x10 | ||
| 116 | #define SYNC_PRESENT 0x08 | ||
| 117 | #define VT_50HZ 0x04 | ||
| 118 | #define SYNC_SNTL 0x02 | ||
| 119 | #define CHROM_FILT 0x01 | ||
| 120 | #define VT_60HZ 0x00 | ||
| 121 | |||
| 122 | /* CSR_EVEN/ODD bit masks */ | ||
| 123 | #define CSR_ERROR 0x04 | ||
| 124 | #define CSR_SNGL 0x02 | ||
| 125 | #define CSR_DONE 0x01 | ||
| 126 | |||
| 127 | /* CONFIG bit masks */ | ||
| 128 | #define PM_LUT_PGM 0x80 | ||
| 129 | #define PM_LUT_SEL 0x40 | ||
| 130 | #define CLIP_EN 0x20 | ||
| 131 | #define HSCALE_EN 0x10 | ||
| 132 | #define EXT_TRIG_UP 0x0C | ||
| 133 | #define EXT_TRIG_DOWN 0x04 | ||
| 134 | #define ACQ_MODE_NEXT 0x02 | ||
| 135 | #define ACQ_MODE_ODD 0x01 | ||
| 136 | #define ACQ_MODE_EVEN 0x00 | ||
| 137 | |||
| 138 | /* AD_CMD bit masks */ | ||
| 139 | #define VIDEO_CNL_1 0x00 | ||
| 140 | #define VIDEO_CNL_2 0x40 | ||
| 141 | #define VIDEO_CNL_3 0x80 | ||
| 142 | #define VIDEO_CNL_4 0xC0 | ||
| 143 | #define SYNC_CNL_1 0x00 | ||
| 144 | #define SYNC_CNL_2 0x10 | ||
| 145 | #define SYNC_CNL_3 0x20 | ||
| 146 | #define SYNC_CNL_4 0x30 | ||
| 147 | #define SYNC_LVL_1 0x00 | ||
| 148 | #define SYNC_LVL_2 0x04 | ||
| 149 | #define SYNC_LVL_3 0x08 | ||
| 150 | #define SYNC_LVL_4 0x0C | ||
| 151 | |||
| 152 | /* DT3155 identificator */ | ||
| 153 | #define DT3155_ID 0x20 | ||
| 154 | |||
| 155 | /* per board private data structure */ | ||
| 156 | /** | ||
| 157 | * struct dt3155_priv - private data structure | ||
| 158 | * | ||
| 159 | * @v4l2_dev: v4l2_device structure | ||
| 160 | * @vdev: video_device structure | ||
| 161 | * @pdev: pointer to pci_dev structure | ||
| 162 | * @vidq: vb2_queue structure | ||
| 163 | * @alloc_ctx: dma_contig allocation context | ||
| 164 | * @curr_buf: pointer to curren buffer | ||
| 165 | * @mux: mutex to protect the instance | ||
| 166 | * @dmaq: queue for dma buffers | ||
| 167 | * @lock: spinlock for dma queue | ||
| 168 | * @std: input standard | ||
| 169 | * @width: frame width | ||
| 170 | * @height: frame height | ||
| 171 | * @input: current input | ||
| 172 | * @sequence: frame counter | ||
| 173 | * @stats: statistics structure | ||
| 174 | * @regs: local copy of mmio base register | ||
| 175 | * @csr2: local copy of csr2 register | ||
| 176 | * @config: local copy of config register | ||
| 177 | */ | ||
| 178 | struct dt3155_priv { | ||
| 179 | struct v4l2_device v4l2_dev; | ||
| 180 | struct video_device vdev; | ||
| 181 | struct pci_dev *pdev; | ||
| 182 | struct vb2_queue vidq; | ||
| 183 | struct vb2_alloc_ctx *alloc_ctx; | ||
| 184 | struct vb2_buffer *curr_buf; | ||
| 185 | struct mutex mux; | ||
| 186 | struct list_head dmaq; | ||
| 187 | spinlock_t lock; | ||
| 188 | v4l2_std_id std; | ||
| 189 | unsigned width, height; | ||
| 190 | unsigned input; | ||
| 191 | unsigned int sequence; | ||
| 192 | void __iomem *regs; | ||
| 193 | u8 csr2, config; | ||
| 194 | }; | ||
| 195 | |||
| 196 | #endif /* _DT3155_H_ */ | ||
