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-rw-r--r--drivers/i3c/Kconfig24
-rw-r--r--drivers/i3c/Makefile4
-rw-r--r--drivers/i3c/device.c233
-rw-r--r--drivers/i3c/internals.h26
-rw-r--r--drivers/i3c/master.c2659
-rw-r--r--drivers/i3c/master/Kconfig22
-rw-r--r--drivers/i3c/master/Makefile2
-rw-r--r--drivers/i3c/master/dw-i3c-master.c1216
-rw-r--r--drivers/i3c/master/i3c-master-cdns.c1666
9 files changed, 5852 insertions, 0 deletions
diff --git a/drivers/i3c/Kconfig b/drivers/i3c/Kconfig
new file mode 100644
index 000000000000..30a441506f61
--- /dev/null
+++ b/drivers/i3c/Kconfig
@@ -0,0 +1,24 @@
1# SPDX-License-Identifier: GPL-2.0
2
3menuconfig I3C
4 tristate "I3C support"
5 select I2C
6 help
7 I3C is a serial protocol standardized by the MIPI alliance.
8
9 It's supposed to be backward compatible with I2C while providing
10 support for high speed transfers and native interrupt support
11 without the need for extra pins.
12
13 The I3C protocol also standardizes the slave device types and is
14 mainly designed to communicate with sensors.
15
16 If you want I3C support, you should say Y here and also to the
17 specific driver for your bus adapter(s) below.
18
19 This I3C support can also be built as a module. If so, the module
20 will be called i3c.
21
22if I3C
23source "drivers/i3c/master/Kconfig"
24endif # I3C
diff --git a/drivers/i3c/Makefile b/drivers/i3c/Makefile
new file mode 100644
index 000000000000..11982efbc6d9
--- /dev/null
+++ b/drivers/i3c/Makefile
@@ -0,0 +1,4 @@
1# SPDX-License-Identifier: GPL-2.0
2i3c-y := device.o master.o
3obj-$(CONFIG_I3C) += i3c.o
4obj-$(CONFIG_I3C) += master/
diff --git a/drivers/i3c/device.c b/drivers/i3c/device.c
new file mode 100644
index 000000000000..69cc040c3a1c
--- /dev/null
+++ b/drivers/i3c/device.c
@@ -0,0 +1,233 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2018 Cadence Design Systems Inc.
4 *
5 * Author: Boris Brezillon <boris.brezillon@bootlin.com>
6 */
7
8#include <linux/atomic.h>
9#include <linux/bug.h>
10#include <linux/completion.h>
11#include <linux/device.h>
12#include <linux/mutex.h>
13#include <linux/slab.h>
14
15#include "internals.h"
16
17/**
18 * i3c_device_do_priv_xfers() - do I3C SDR private transfers directed to a
19 * specific device
20 *
21 * @dev: device with which the transfers should be done
22 * @xfers: array of transfers
23 * @nxfers: number of transfers
24 *
25 * Initiate one or several private SDR transfers with @dev.
26 *
27 * This function can sleep and thus cannot be called in atomic context.
28 *
29 * Return: 0 in case of success, a negative error core otherwise.
30 */
31int i3c_device_do_priv_xfers(struct i3c_device *dev,
32 struct i3c_priv_xfer *xfers,
33 int nxfers)
34{
35 int ret, i;
36
37 if (nxfers < 1)
38 return 0;
39
40 for (i = 0; i < nxfers; i++) {
41 if (!xfers[i].len || !xfers[i].data.in)
42 return -EINVAL;
43 }
44
45 i3c_bus_normaluse_lock(dev->bus);
46 ret = i3c_dev_do_priv_xfers_locked(dev->desc, xfers, nxfers);
47 i3c_bus_normaluse_unlock(dev->bus);
48
49 return ret;
50}
51EXPORT_SYMBOL_GPL(i3c_device_do_priv_xfers);
52
53/**
54 * i3c_device_get_info() - get I3C device information
55 *
56 * @dev: device we want information on
57 * @info: the information object to fill in
58 *
59 * Retrieve I3C dev info.
60 */
61void i3c_device_get_info(struct i3c_device *dev,
62 struct i3c_device_info *info)
63{
64 if (!info)
65 return;
66
67 i3c_bus_normaluse_lock(dev->bus);
68 if (dev->desc)
69 *info = dev->desc->info;
70 i3c_bus_normaluse_unlock(dev->bus);
71}
72EXPORT_SYMBOL_GPL(i3c_device_get_info);
73
74/**
75 * i3c_device_disable_ibi() - Disable IBIs coming from a specific device
76 * @dev: device on which IBIs should be disabled
77 *
78 * This function disable IBIs coming from a specific device and wait for
79 * all pending IBIs to be processed.
80 *
81 * Return: 0 in case of success, a negative error core otherwise.
82 */
83int i3c_device_disable_ibi(struct i3c_device *dev)
84{
85 int ret = -ENOENT;
86
87 i3c_bus_normaluse_lock(dev->bus);
88 if (dev->desc) {
89 mutex_lock(&dev->desc->ibi_lock);
90 ret = i3c_dev_disable_ibi_locked(dev->desc);
91 mutex_unlock(&dev->desc->ibi_lock);
92 }
93 i3c_bus_normaluse_unlock(dev->bus);
94
95 return ret;
96}
97EXPORT_SYMBOL_GPL(i3c_device_disable_ibi);
98
99/**
100 * i3c_device_enable_ibi() - Enable IBIs coming from a specific device
101 * @dev: device on which IBIs should be enabled
102 *
103 * This function enable IBIs coming from a specific device and wait for
104 * all pending IBIs to be processed. This should be called on a device
105 * where i3c_device_request_ibi() has succeeded.
106 *
107 * Note that IBIs from this device might be received before this function
108 * returns to its caller.
109 *
110 * Return: 0 in case of success, a negative error core otherwise.
111 */
112int i3c_device_enable_ibi(struct i3c_device *dev)
113{
114 int ret = -ENOENT;
115
116 i3c_bus_normaluse_lock(dev->bus);
117 if (dev->desc) {
118 mutex_lock(&dev->desc->ibi_lock);
119 ret = i3c_dev_enable_ibi_locked(dev->desc);
120 mutex_unlock(&dev->desc->ibi_lock);
121 }
122 i3c_bus_normaluse_unlock(dev->bus);
123
124 return ret;
125}
126EXPORT_SYMBOL_GPL(i3c_device_enable_ibi);
127
128/**
129 * i3c_device_request_ibi() - Request an IBI
130 * @dev: device for which we should enable IBIs
131 * @req: setup requested for this IBI
132 *
133 * This function is responsible for pre-allocating all resources needed to
134 * process IBIs coming from @dev. When this function returns, the IBI is not
135 * enabled until i3c_device_enable_ibi() is called.
136 *
137 * Return: 0 in case of success, a negative error core otherwise.
138 */
139int i3c_device_request_ibi(struct i3c_device *dev,
140 const struct i3c_ibi_setup *req)
141{
142 int ret = -ENOENT;
143
144 if (!req->handler || !req->num_slots)
145 return -EINVAL;
146
147 i3c_bus_normaluse_lock(dev->bus);
148 if (dev->desc) {
149 mutex_lock(&dev->desc->ibi_lock);
150 ret = i3c_dev_request_ibi_locked(dev->desc, req);
151 mutex_unlock(&dev->desc->ibi_lock);
152 }
153 i3c_bus_normaluse_unlock(dev->bus);
154
155 return ret;
156}
157EXPORT_SYMBOL_GPL(i3c_device_request_ibi);
158
159/**
160 * i3c_device_free_ibi() - Free all resources needed for IBI handling
161 * @dev: device on which you want to release IBI resources
162 *
163 * This function is responsible for de-allocating resources previously
164 * allocated by i3c_device_request_ibi(). It should be called after disabling
165 * IBIs with i3c_device_disable_ibi().
166 */
167void i3c_device_free_ibi(struct i3c_device *dev)
168{
169 i3c_bus_normaluse_lock(dev->bus);
170 if (dev->desc) {
171 mutex_lock(&dev->desc->ibi_lock);
172 i3c_dev_free_ibi_locked(dev->desc);
173 mutex_unlock(&dev->desc->ibi_lock);
174 }
175 i3c_bus_normaluse_unlock(dev->bus);
176}
177EXPORT_SYMBOL_GPL(i3c_device_free_ibi);
178
179/**
180 * i3cdev_to_dev() - Returns the device embedded in @i3cdev
181 * @i3cdev: I3C device
182 *
183 * Return: a pointer to a device object.
184 */
185struct device *i3cdev_to_dev(struct i3c_device *i3cdev)
186{
187 return &i3cdev->dev;
188}
189EXPORT_SYMBOL_GPL(i3cdev_to_dev);
190
191/**
192 * dev_to_i3cdev() - Returns the I3C device containing @dev
193 * @dev: device object
194 *
195 * Return: a pointer to an I3C device object.
196 */
197struct i3c_device *dev_to_i3cdev(struct device *dev)
198{
199 return container_of(dev, struct i3c_device, dev);
200}
201EXPORT_SYMBOL_GPL(dev_to_i3cdev);
202
203/**
204 * i3c_driver_register_with_owner() - register an I3C device driver
205 *
206 * @drv: driver to register
207 * @owner: module that owns this driver
208 *
209 * Register @drv to the core.
210 *
211 * Return: 0 in case of success, a negative error core otherwise.
212 */
213int i3c_driver_register_with_owner(struct i3c_driver *drv, struct module *owner)
214{
215 drv->driver.owner = owner;
216 drv->driver.bus = &i3c_bus_type;
217
218 return driver_register(&drv->driver);
219}
220EXPORT_SYMBOL_GPL(i3c_driver_register_with_owner);
221
222/**
223 * i3c_driver_unregister() - unregister an I3C device driver
224 *
225 * @drv: driver to unregister
226 *
227 * Unregister @drv.
228 */
229void i3c_driver_unregister(struct i3c_driver *drv)
230{
231 driver_unregister(&drv->driver);
232}
233EXPORT_SYMBOL_GPL(i3c_driver_unregister);
diff --git a/drivers/i3c/internals.h b/drivers/i3c/internals.h
new file mode 100644
index 000000000000..86b7b44cfca2
--- /dev/null
+++ b/drivers/i3c/internals.h
@@ -0,0 +1,26 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2018 Cadence Design Systems Inc.
4 *
5 * Author: Boris Brezillon <boris.brezillon@bootlin.com>
6 */
7
8#ifndef I3C_INTERNALS_H
9#define I3C_INTERNALS_H
10
11#include <linux/i3c/master.h>
12
13extern struct bus_type i3c_bus_type;
14
15void i3c_bus_normaluse_lock(struct i3c_bus *bus);
16void i3c_bus_normaluse_unlock(struct i3c_bus *bus);
17
18int i3c_dev_do_priv_xfers_locked(struct i3c_dev_desc *dev,
19 struct i3c_priv_xfer *xfers,
20 int nxfers);
21int i3c_dev_disable_ibi_locked(struct i3c_dev_desc *dev);
22int i3c_dev_enable_ibi_locked(struct i3c_dev_desc *dev);
23int i3c_dev_request_ibi_locked(struct i3c_dev_desc *dev,
24 const struct i3c_ibi_setup *req);
25void i3c_dev_free_ibi_locked(struct i3c_dev_desc *dev);
26#endif /* I3C_INTERNAL_H */
diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c
new file mode 100644
index 000000000000..c39f89d2deba
--- /dev/null
+++ b/drivers/i3c/master.c
@@ -0,0 +1,2659 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2018 Cadence Design Systems Inc.
4 *
5 * Author: Boris Brezillon <boris.brezillon@bootlin.com>
6 */
7
8#include <linux/atomic.h>
9#include <linux/bug.h>
10#include <linux/device.h>
11#include <linux/err.h>
12#include <linux/export.h>
13#include <linux/kernel.h>
14#include <linux/list.h>
15#include <linux/of.h>
16#include <linux/slab.h>
17#include <linux/spinlock.h>
18#include <linux/workqueue.h>
19
20#include "internals.h"
21
22static DEFINE_IDR(i3c_bus_idr);
23static DEFINE_MUTEX(i3c_core_lock);
24
25/**
26 * i3c_bus_maintenance_lock - Lock the bus for a maintenance operation
27 * @bus: I3C bus to take the lock on
28 *
29 * This function takes the bus lock so that no other operations can occur on
30 * the bus. This is needed for all kind of bus maintenance operation, like
31 * - enabling/disabling slave events
32 * - re-triggering DAA
33 * - changing the dynamic address of a device
34 * - relinquishing mastership
35 * - ...
36 *
37 * The reason for this kind of locking is that we don't want drivers and core
38 * logic to rely on I3C device information that could be changed behind their
39 * back.
40 */
41static void i3c_bus_maintenance_lock(struct i3c_bus *bus)
42{
43 down_write(&bus->lock);
44}
45
46/**
47 * i3c_bus_maintenance_unlock - Release the bus lock after a maintenance
48 * operation
49 * @bus: I3C bus to release the lock on
50 *
51 * Should be called when the bus maintenance operation is done. See
52 * i3c_bus_maintenance_lock() for more details on what these maintenance
53 * operations are.
54 */
55static void i3c_bus_maintenance_unlock(struct i3c_bus *bus)
56{
57 up_write(&bus->lock);
58}
59
60/**
61 * i3c_bus_normaluse_lock - Lock the bus for a normal operation
62 * @bus: I3C bus to take the lock on
63 *
64 * This function takes the bus lock for any operation that is not a maintenance
65 * operation (see i3c_bus_maintenance_lock() for a non-exhaustive list of
66 * maintenance operations). Basically all communications with I3C devices are
67 * normal operations (HDR, SDR transfers or CCC commands that do not change bus
68 * state or I3C dynamic address).
69 *
70 * Note that this lock is not guaranteeing serialization of normal operations.
71 * In other words, transfer requests passed to the I3C master can be submitted
72 * in parallel and I3C master drivers have to use their own locking to make
73 * sure two different communications are not inter-mixed, or access to the
74 * output/input queue is not done while the engine is busy.
75 */
76void i3c_bus_normaluse_lock(struct i3c_bus *bus)
77{
78 down_read(&bus->lock);
79}
80
81/**
82 * i3c_bus_normaluse_unlock - Release the bus lock after a normal operation
83 * @bus: I3C bus to release the lock on
84 *
85 * Should be called when a normal operation is done. See
86 * i3c_bus_normaluse_lock() for more details on what these normal operations
87 * are.
88 */
89void i3c_bus_normaluse_unlock(struct i3c_bus *bus)
90{
91 up_read(&bus->lock);
92}
93
94static struct i3c_master_controller *dev_to_i3cmaster(struct device *dev)
95{
96 return container_of(dev, struct i3c_master_controller, dev);
97}
98
99static const struct device_type i3c_device_type;
100
101static struct i3c_bus *dev_to_i3cbus(struct device *dev)
102{
103 struct i3c_master_controller *master;
104
105 if (dev->type == &i3c_device_type)
106 return dev_to_i3cdev(dev)->bus;
107
108 master = dev_to_i3cmaster(dev);
109
110 return &master->bus;
111}
112
113static struct i3c_dev_desc *dev_to_i3cdesc(struct device *dev)
114{
115 struct i3c_master_controller *master;
116
117 if (dev->type == &i3c_device_type)
118 return dev_to_i3cdev(dev)->desc;
119
120 master = container_of(dev, struct i3c_master_controller, dev);
121
122 return master->this;
123}
124
125static ssize_t bcr_show(struct device *dev,
126 struct device_attribute *da,
127 char *buf)
128{
129 struct i3c_bus *bus = dev_to_i3cbus(dev);
130 struct i3c_dev_desc *desc;
131 ssize_t ret;
132
133 i3c_bus_normaluse_lock(bus);
134 desc = dev_to_i3cdesc(dev);
135 ret = sprintf(buf, "%x\n", desc->info.bcr);
136 i3c_bus_normaluse_unlock(bus);
137
138 return ret;
139}
140static DEVICE_ATTR_RO(bcr);
141
142static ssize_t dcr_show(struct device *dev,
143 struct device_attribute *da,
144 char *buf)
145{
146 struct i3c_bus *bus = dev_to_i3cbus(dev);
147 struct i3c_dev_desc *desc;
148 ssize_t ret;
149
150 i3c_bus_normaluse_lock(bus);
151 desc = dev_to_i3cdesc(dev);
152 ret = sprintf(buf, "%x\n", desc->info.dcr);
153 i3c_bus_normaluse_unlock(bus);
154
155 return ret;
156}
157static DEVICE_ATTR_RO(dcr);
158
159static ssize_t pid_show(struct device *dev,
160 struct device_attribute *da,
161 char *buf)
162{
163 struct i3c_bus *bus = dev_to_i3cbus(dev);
164 struct i3c_dev_desc *desc;
165 ssize_t ret;
166
167 i3c_bus_normaluse_lock(bus);
168 desc = dev_to_i3cdesc(dev);
169 ret = sprintf(buf, "%llx\n", desc->info.pid);
170 i3c_bus_normaluse_unlock(bus);
171
172 return ret;
173}
174static DEVICE_ATTR_RO(pid);
175
176static ssize_t dynamic_address_show(struct device *dev,
177 struct device_attribute *da,
178 char *buf)
179{
180 struct i3c_bus *bus = dev_to_i3cbus(dev);
181 struct i3c_dev_desc *desc;
182 ssize_t ret;
183
184 i3c_bus_normaluse_lock(bus);
185 desc = dev_to_i3cdesc(dev);
186 ret = sprintf(buf, "%02x\n", desc->info.dyn_addr);
187 i3c_bus_normaluse_unlock(bus);
188
189 return ret;
190}
191static DEVICE_ATTR_RO(dynamic_address);
192
193static const char * const hdrcap_strings[] = {
194 "hdr-ddr", "hdr-tsp", "hdr-tsl",
195};
196
197static ssize_t hdrcap_show(struct device *dev,
198 struct device_attribute *da,
199 char *buf)
200{
201 struct i3c_bus *bus = dev_to_i3cbus(dev);
202 struct i3c_dev_desc *desc;
203 ssize_t offset = 0, ret;
204 unsigned long caps;
205 int mode;
206
207 i3c_bus_normaluse_lock(bus);
208 desc = dev_to_i3cdesc(dev);
209 caps = desc->info.hdr_cap;
210 for_each_set_bit(mode, &caps, 8) {
211 if (mode >= ARRAY_SIZE(hdrcap_strings))
212 break;
213
214 if (!hdrcap_strings[mode])
215 continue;
216
217 ret = sprintf(buf + offset, offset ? " %s" : "%s",
218 hdrcap_strings[mode]);
219 if (ret < 0)
220 goto out;
221
222 offset += ret;
223 }
224
225 ret = sprintf(buf + offset, "\n");
226 if (ret < 0)
227 goto out;
228
229 ret = offset + ret;
230
231out:
232 i3c_bus_normaluse_unlock(bus);
233
234 return ret;
235}
236static DEVICE_ATTR_RO(hdrcap);
237
238static struct attribute *i3c_device_attrs[] = {
239 &dev_attr_bcr.attr,
240 &dev_attr_dcr.attr,
241 &dev_attr_pid.attr,
242 &dev_attr_dynamic_address.attr,
243 &dev_attr_hdrcap.attr,
244 NULL,
245};
246ATTRIBUTE_GROUPS(i3c_device);
247
248static int i3c_device_uevent(struct device *dev, struct kobj_uevent_env *env)
249{
250 struct i3c_device *i3cdev = dev_to_i3cdev(dev);
251 struct i3c_device_info devinfo;
252 u16 manuf, part, ext;
253
254 i3c_device_get_info(i3cdev, &devinfo);
255 manuf = I3C_PID_MANUF_ID(devinfo.pid);
256 part = I3C_PID_PART_ID(devinfo.pid);
257 ext = I3C_PID_EXTRA_INFO(devinfo.pid);
258
259 if (I3C_PID_RND_LOWER_32BITS(devinfo.pid))
260 return add_uevent_var(env, "MODALIAS=i3c:dcr%02Xmanuf%04X",
261 devinfo.dcr, manuf);
262
263 return add_uevent_var(env,
264 "MODALIAS=i3c:dcr%02Xmanuf%04Xpart%04xext%04x",
265 devinfo.dcr, manuf, part, ext);
266}
267
268static const struct device_type i3c_device_type = {
269 .groups = i3c_device_groups,
270 .uevent = i3c_device_uevent,
271};
272
273static const struct i3c_device_id *
274i3c_device_match_id(struct i3c_device *i3cdev,
275 const struct i3c_device_id *id_table)
276{
277 struct i3c_device_info devinfo;
278 const struct i3c_device_id *id;
279
280 i3c_device_get_info(i3cdev, &devinfo);
281
282 /*
283 * The lower 32bits of the provisional ID is just filled with a random
284 * value, try to match using DCR info.
285 */
286 if (!I3C_PID_RND_LOWER_32BITS(devinfo.pid)) {
287 u16 manuf = I3C_PID_MANUF_ID(devinfo.pid);
288 u16 part = I3C_PID_PART_ID(devinfo.pid);
289 u16 ext_info = I3C_PID_EXTRA_INFO(devinfo.pid);
290
291 /* First try to match by manufacturer/part ID. */
292 for (id = id_table; id->match_flags != 0; id++) {
293 if ((id->match_flags & I3C_MATCH_MANUF_AND_PART) !=
294 I3C_MATCH_MANUF_AND_PART)
295 continue;
296
297 if (manuf != id->manuf_id || part != id->part_id)
298 continue;
299
300 if ((id->match_flags & I3C_MATCH_EXTRA_INFO) &&
301 ext_info != id->extra_info)
302 continue;
303
304 return id;
305 }
306 }
307
308 /* Fallback to DCR match. */
309 for (id = id_table; id->match_flags != 0; id++) {
310 if ((id->match_flags & I3C_MATCH_DCR) &&
311 id->dcr == devinfo.dcr)
312 return id;
313 }
314
315 return NULL;
316}
317
318static int i3c_device_match(struct device *dev, struct device_driver *drv)
319{
320 struct i3c_device *i3cdev;
321 struct i3c_driver *i3cdrv;
322
323 if (dev->type != &i3c_device_type)
324 return 0;
325
326 i3cdev = dev_to_i3cdev(dev);
327 i3cdrv = drv_to_i3cdrv(drv);
328 if (i3c_device_match_id(i3cdev, i3cdrv->id_table))
329 return 1;
330
331 return 0;
332}
333
334static int i3c_device_probe(struct device *dev)
335{
336 struct i3c_device *i3cdev = dev_to_i3cdev(dev);
337 struct i3c_driver *driver = drv_to_i3cdrv(dev->driver);
338
339 return driver->probe(i3cdev);
340}
341
342static int i3c_device_remove(struct device *dev)
343{
344 struct i3c_device *i3cdev = dev_to_i3cdev(dev);
345 struct i3c_driver *driver = drv_to_i3cdrv(dev->driver);
346 int ret;
347
348 ret = driver->remove(i3cdev);
349 if (ret)
350 return ret;
351
352 i3c_device_free_ibi(i3cdev);
353
354 return ret;
355}
356
357struct bus_type i3c_bus_type = {
358 .name = "i3c",
359 .match = i3c_device_match,
360 .probe = i3c_device_probe,
361 .remove = i3c_device_remove,
362};
363
364static enum i3c_addr_slot_status
365i3c_bus_get_addr_slot_status(struct i3c_bus *bus, u16 addr)
366{
367 int status, bitpos = addr * 2;
368
369 if (addr > I2C_MAX_ADDR)
370 return I3C_ADDR_SLOT_RSVD;
371
372 status = bus->addrslots[bitpos / BITS_PER_LONG];
373 status >>= bitpos % BITS_PER_LONG;
374
375 return status & I3C_ADDR_SLOT_STATUS_MASK;
376}
377
378static void i3c_bus_set_addr_slot_status(struct i3c_bus *bus, u16 addr,
379 enum i3c_addr_slot_status status)
380{
381 int bitpos = addr * 2;
382 unsigned long *ptr;
383
384 if (addr > I2C_MAX_ADDR)
385 return;
386
387 ptr = bus->addrslots + (bitpos / BITS_PER_LONG);
388 *ptr &= ~(I3C_ADDR_SLOT_STATUS_MASK << (bitpos % BITS_PER_LONG));
389 *ptr |= status << (bitpos % BITS_PER_LONG);
390}
391
392static bool i3c_bus_dev_addr_is_avail(struct i3c_bus *bus, u8 addr)
393{
394 enum i3c_addr_slot_status status;
395
396 status = i3c_bus_get_addr_slot_status(bus, addr);
397
398 return status == I3C_ADDR_SLOT_FREE;
399}
400
401static int i3c_bus_get_free_addr(struct i3c_bus *bus, u8 start_addr)
402{
403 enum i3c_addr_slot_status status;
404 u8 addr;
405
406 for (addr = start_addr; addr < I3C_MAX_ADDR; addr++) {
407 status = i3c_bus_get_addr_slot_status(bus, addr);
408 if (status == I3C_ADDR_SLOT_FREE)
409 return addr;
410 }
411
412 return -ENOMEM;
413}
414
415static void i3c_bus_init_addrslots(struct i3c_bus *bus)
416{
417 int i;
418
419 /* Addresses 0 to 7 are reserved. */
420 for (i = 0; i < 8; i++)
421 i3c_bus_set_addr_slot_status(bus, i, I3C_ADDR_SLOT_RSVD);
422
423 /*
424 * Reserve broadcast address and all addresses that might collide
425 * with the broadcast address when facing a single bit error.
426 */
427 i3c_bus_set_addr_slot_status(bus, I3C_BROADCAST_ADDR,
428 I3C_ADDR_SLOT_RSVD);
429 for (i = 0; i < 7; i++)
430 i3c_bus_set_addr_slot_status(bus, I3C_BROADCAST_ADDR ^ BIT(i),
431 I3C_ADDR_SLOT_RSVD);
432}
433
434static void i3c_bus_cleanup(struct i3c_bus *i3cbus)
435{
436 mutex_lock(&i3c_core_lock);
437 idr_remove(&i3c_bus_idr, i3cbus->id);
438 mutex_unlock(&i3c_core_lock);
439}
440
441static int i3c_bus_init(struct i3c_bus *i3cbus)
442{
443 int ret;
444
445 init_rwsem(&i3cbus->lock);
446 INIT_LIST_HEAD(&i3cbus->devs.i2c);
447 INIT_LIST_HEAD(&i3cbus->devs.i3c);
448 i3c_bus_init_addrslots(i3cbus);
449 i3cbus->mode = I3C_BUS_MODE_PURE;
450
451 mutex_lock(&i3c_core_lock);
452 ret = idr_alloc(&i3c_bus_idr, i3cbus, 0, 0, GFP_KERNEL);
453 mutex_unlock(&i3c_core_lock);
454
455 if (ret < 0)
456 return ret;
457
458 i3cbus->id = ret;
459
460 return 0;
461}
462
463static const char * const i3c_bus_mode_strings[] = {
464 [I3C_BUS_MODE_PURE] = "pure",
465 [I3C_BUS_MODE_MIXED_FAST] = "mixed-fast",
466 [I3C_BUS_MODE_MIXED_SLOW] = "mixed-slow",
467};
468
469static ssize_t mode_show(struct device *dev,
470 struct device_attribute *da,
471 char *buf)
472{
473 struct i3c_bus *i3cbus = dev_to_i3cbus(dev);
474 ssize_t ret;
475
476 i3c_bus_normaluse_lock(i3cbus);
477 if (i3cbus->mode < 0 ||
478 i3cbus->mode >= ARRAY_SIZE(i3c_bus_mode_strings) ||
479 !i3c_bus_mode_strings[i3cbus->mode])
480 ret = sprintf(buf, "unknown\n");
481 else
482 ret = sprintf(buf, "%s\n", i3c_bus_mode_strings[i3cbus->mode]);
483 i3c_bus_normaluse_unlock(i3cbus);
484
485 return ret;
486}
487static DEVICE_ATTR_RO(mode);
488
489static ssize_t current_master_show(struct device *dev,
490 struct device_attribute *da,
491 char *buf)
492{
493 struct i3c_bus *i3cbus = dev_to_i3cbus(dev);
494 ssize_t ret;
495
496 i3c_bus_normaluse_lock(i3cbus);
497 ret = sprintf(buf, "%d-%llx\n", i3cbus->id,
498 i3cbus->cur_master->info.pid);
499 i3c_bus_normaluse_unlock(i3cbus);
500
501 return ret;
502}
503static DEVICE_ATTR_RO(current_master);
504
505static ssize_t i3c_scl_frequency_show(struct device *dev,
506 struct device_attribute *da,
507 char *buf)
508{
509 struct i3c_bus *i3cbus = dev_to_i3cbus(dev);
510 ssize_t ret;
511
512 i3c_bus_normaluse_lock(i3cbus);
513 ret = sprintf(buf, "%ld\n", i3cbus->scl_rate.i3c);
514 i3c_bus_normaluse_unlock(i3cbus);
515
516 return ret;
517}
518static DEVICE_ATTR_RO(i3c_scl_frequency);
519
520static ssize_t i2c_scl_frequency_show(struct device *dev,
521 struct device_attribute *da,
522 char *buf)
523{
524 struct i3c_bus *i3cbus = dev_to_i3cbus(dev);
525 ssize_t ret;
526
527 i3c_bus_normaluse_lock(i3cbus);
528 ret = sprintf(buf, "%ld\n", i3cbus->scl_rate.i2c);
529 i3c_bus_normaluse_unlock(i3cbus);
530
531 return ret;
532}
533static DEVICE_ATTR_RO(i2c_scl_frequency);
534
535static struct attribute *i3c_masterdev_attrs[] = {
536 &dev_attr_mode.attr,
537 &dev_attr_current_master.attr,
538 &dev_attr_i3c_scl_frequency.attr,
539 &dev_attr_i2c_scl_frequency.attr,
540 &dev_attr_bcr.attr,
541 &dev_attr_dcr.attr,
542 &dev_attr_pid.attr,
543 &dev_attr_dynamic_address.attr,
544 &dev_attr_hdrcap.attr,
545 NULL,
546};
547ATTRIBUTE_GROUPS(i3c_masterdev);
548
549static void i3c_masterdev_release(struct device *dev)
550{
551 struct i3c_master_controller *master = dev_to_i3cmaster(dev);
552 struct i3c_bus *bus = dev_to_i3cbus(dev);
553
554 if (master->wq)
555 destroy_workqueue(master->wq);
556
557 WARN_ON(!list_empty(&bus->devs.i2c) || !list_empty(&bus->devs.i3c));
558 i3c_bus_cleanup(bus);
559
560 of_node_put(dev->of_node);
561}
562
563static const struct device_type i3c_masterdev_type = {
564 .groups = i3c_masterdev_groups,
565};
566
567int i3c_bus_set_mode(struct i3c_bus *i3cbus, enum i3c_bus_mode mode)
568{
569 i3cbus->mode = mode;
570
571 if (!i3cbus->scl_rate.i3c)
572 i3cbus->scl_rate.i3c = I3C_BUS_TYP_I3C_SCL_RATE;
573
574 if (!i3cbus->scl_rate.i2c) {
575 if (i3cbus->mode == I3C_BUS_MODE_MIXED_SLOW)
576 i3cbus->scl_rate.i2c = I3C_BUS_I2C_FM_SCL_RATE;
577 else
578 i3cbus->scl_rate.i2c = I3C_BUS_I2C_FM_PLUS_SCL_RATE;
579 }
580
581 /*
582 * I3C/I2C frequency may have been overridden, check that user-provided
583 * values are not exceeding max possible frequency.
584 */
585 if (i3cbus->scl_rate.i3c > I3C_BUS_MAX_I3C_SCL_RATE ||
586 i3cbus->scl_rate.i2c > I3C_BUS_I2C_FM_PLUS_SCL_RATE)
587 return -EINVAL;
588
589 return 0;
590}
591
592static struct i3c_master_controller *
593i2c_adapter_to_i3c_master(struct i2c_adapter *adap)
594{
595 return container_of(adap, struct i3c_master_controller, i2c);
596}
597
598static struct i2c_adapter *
599i3c_master_to_i2c_adapter(struct i3c_master_controller *master)
600{
601 return &master->i2c;
602}
603
604static void i3c_master_free_i2c_dev(struct i2c_dev_desc *dev)
605{
606 kfree(dev);
607}
608
609static struct i2c_dev_desc *
610i3c_master_alloc_i2c_dev(struct i3c_master_controller *master,
611 const struct i2c_dev_boardinfo *boardinfo)
612{
613 struct i2c_dev_desc *dev;
614
615 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
616 if (!dev)
617 return ERR_PTR(-ENOMEM);
618
619 dev->common.master = master;
620 dev->boardinfo = boardinfo;
621
622 return dev;
623}
624
625static void *i3c_ccc_cmd_dest_init(struct i3c_ccc_cmd_dest *dest, u8 addr,
626 u16 payloadlen)
627{
628 dest->addr = addr;
629 dest->payload.len = payloadlen;
630 if (payloadlen)
631 dest->payload.data = kzalloc(payloadlen, GFP_KERNEL);
632 else
633 dest->payload.data = NULL;
634
635 return dest->payload.data;
636}
637
638static void i3c_ccc_cmd_dest_cleanup(struct i3c_ccc_cmd_dest *dest)
639{
640 kfree(dest->payload.data);
641}
642
643static void i3c_ccc_cmd_init(struct i3c_ccc_cmd *cmd, bool rnw, u8 id,
644 struct i3c_ccc_cmd_dest *dests,
645 unsigned int ndests)
646{
647 cmd->rnw = rnw ? 1 : 0;
648 cmd->id = id;
649 cmd->dests = dests;
650 cmd->ndests = ndests;
651 cmd->err = I3C_ERROR_UNKNOWN;
652}
653
654static int i3c_master_send_ccc_cmd_locked(struct i3c_master_controller *master,
655 struct i3c_ccc_cmd *cmd)
656{
657 int ret;
658
659 if (!cmd || !master)
660 return -EINVAL;
661
662 if (WARN_ON(master->init_done &&
663 !rwsem_is_locked(&master->bus.lock)))
664 return -EINVAL;
665
666 if (!master->ops->send_ccc_cmd)
667 return -ENOTSUPP;
668
669 if ((cmd->id & I3C_CCC_DIRECT) && (!cmd->dests || !cmd->ndests))
670 return -EINVAL;
671
672 if (master->ops->supports_ccc_cmd &&
673 !master->ops->supports_ccc_cmd(master, cmd))
674 return -ENOTSUPP;
675
676 ret = master->ops->send_ccc_cmd(master, cmd);
677 if (ret) {
678 if (cmd->err != I3C_ERROR_UNKNOWN)
679 return cmd->err;
680
681 return ret;
682 }
683
684 return 0;
685}
686
687static struct i2c_dev_desc *
688i3c_master_find_i2c_dev_by_addr(const struct i3c_master_controller *master,
689 u16 addr)
690{
691 struct i2c_dev_desc *dev;
692
693 i3c_bus_for_each_i2cdev(&master->bus, dev) {
694 if (dev->boardinfo->base.addr == addr)
695 return dev;
696 }
697
698 return NULL;
699}
700
701/**
702 * i3c_master_get_free_addr() - get a free address on the bus
703 * @master: I3C master object
704 * @start_addr: where to start searching
705 *
706 * This function must be called with the bus lock held in write mode.
707 *
708 * Return: the first free address starting at @start_addr (included) or -ENOMEM
709 * if there's no more address available.
710 */
711int i3c_master_get_free_addr(struct i3c_master_controller *master,
712 u8 start_addr)
713{
714 return i3c_bus_get_free_addr(&master->bus, start_addr);
715}
716EXPORT_SYMBOL_GPL(i3c_master_get_free_addr);
717
718static void i3c_device_release(struct device *dev)
719{
720 struct i3c_device *i3cdev = dev_to_i3cdev(dev);
721
722 WARN_ON(i3cdev->desc);
723
724 of_node_put(i3cdev->dev.of_node);
725 kfree(i3cdev);
726}
727
728static void i3c_master_free_i3c_dev(struct i3c_dev_desc *dev)
729{
730 kfree(dev);
731}
732
733static struct i3c_dev_desc *
734i3c_master_alloc_i3c_dev(struct i3c_master_controller *master,
735 const struct i3c_device_info *info)
736{
737 struct i3c_dev_desc *dev;
738
739 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
740 if (!dev)
741 return ERR_PTR(-ENOMEM);
742
743 dev->common.master = master;
744 dev->info = *info;
745 mutex_init(&dev->ibi_lock);
746
747 return dev;
748}
749
750static int i3c_master_rstdaa_locked(struct i3c_master_controller *master,
751 u8 addr)
752{
753 enum i3c_addr_slot_status addrstat;
754 struct i3c_ccc_cmd_dest dest;
755 struct i3c_ccc_cmd cmd;
756 int ret;
757
758 if (!master)
759 return -EINVAL;
760
761 addrstat = i3c_bus_get_addr_slot_status(&master->bus, addr);
762 if (addr != I3C_BROADCAST_ADDR && addrstat != I3C_ADDR_SLOT_I3C_DEV)
763 return -EINVAL;
764
765 i3c_ccc_cmd_dest_init(&dest, addr, 0);
766 i3c_ccc_cmd_init(&cmd, false,
767 I3C_CCC_RSTDAA(addr == I3C_BROADCAST_ADDR),
768 &dest, 1);
769 ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
770 i3c_ccc_cmd_dest_cleanup(&dest);
771
772 return ret;
773}
774
775/**
776 * i3c_master_entdaa_locked() - start a DAA (Dynamic Address Assignment)
777 * procedure
778 * @master: master used to send frames on the bus
779 *
780 * Send a ENTDAA CCC command to start a DAA procedure.
781 *
782 * Note that this function only sends the ENTDAA CCC command, all the logic
783 * behind dynamic address assignment has to be handled in the I3C master
784 * driver.
785 *
786 * This function must be called with the bus lock held in write mode.
787 *
788 * Return: 0 in case of success, a positive I3C error code if the error is
789 * one of the official Mx error codes, and a negative error code otherwise.
790 */
791int i3c_master_entdaa_locked(struct i3c_master_controller *master)
792{
793 struct i3c_ccc_cmd_dest dest;
794 struct i3c_ccc_cmd cmd;
795 int ret;
796
797 i3c_ccc_cmd_dest_init(&dest, I3C_BROADCAST_ADDR, 0);
798 i3c_ccc_cmd_init(&cmd, false, I3C_CCC_ENTDAA, &dest, 1);
799 ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
800 i3c_ccc_cmd_dest_cleanup(&dest);
801
802 return ret;
803}
804EXPORT_SYMBOL_GPL(i3c_master_entdaa_locked);
805
806static int i3c_master_enec_disec_locked(struct i3c_master_controller *master,
807 u8 addr, bool enable, u8 evts)
808{
809 struct i3c_ccc_events *events;
810 struct i3c_ccc_cmd_dest dest;
811 struct i3c_ccc_cmd cmd;
812 int ret;
813
814 events = i3c_ccc_cmd_dest_init(&dest, addr, sizeof(*events));
815 if (!events)
816 return -ENOMEM;
817
818 events->events = evts;
819 i3c_ccc_cmd_init(&cmd, false,
820 enable ?
821 I3C_CCC_ENEC(addr == I3C_BROADCAST_ADDR) :
822 I3C_CCC_DISEC(addr == I3C_BROADCAST_ADDR),
823 &dest, 1);
824 ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
825 i3c_ccc_cmd_dest_cleanup(&dest);
826
827 return ret;
828}
829
830/**
831 * i3c_master_disec_locked() - send a DISEC CCC command
832 * @master: master used to send frames on the bus
833 * @addr: a valid I3C slave address or %I3C_BROADCAST_ADDR
834 * @evts: events to disable
835 *
836 * Send a DISEC CCC command to disable some or all events coming from a
837 * specific slave, or all devices if @addr is %I3C_BROADCAST_ADDR.
838 *
839 * This function must be called with the bus lock held in write mode.
840 *
841 * Return: 0 in case of success, a positive I3C error code if the error is
842 * one of the official Mx error codes, and a negative error code otherwise.
843 */
844int i3c_master_disec_locked(struct i3c_master_controller *master, u8 addr,
845 u8 evts)
846{
847 return i3c_master_enec_disec_locked(master, addr, false, evts);
848}
849EXPORT_SYMBOL_GPL(i3c_master_disec_locked);
850
851/**
852 * i3c_master_enec_locked() - send an ENEC CCC command
853 * @master: master used to send frames on the bus
854 * @addr: a valid I3C slave address or %I3C_BROADCAST_ADDR
855 * @evts: events to disable
856 *
857 * Sends an ENEC CCC command to enable some or all events coming from a
858 * specific slave, or all devices if @addr is %I3C_BROADCAST_ADDR.
859 *
860 * This function must be called with the bus lock held in write mode.
861 *
862 * Return: 0 in case of success, a positive I3C error code if the error is
863 * one of the official Mx error codes, and a negative error code otherwise.
864 */
865int i3c_master_enec_locked(struct i3c_master_controller *master, u8 addr,
866 u8 evts)
867{
868 return i3c_master_enec_disec_locked(master, addr, true, evts);
869}
870EXPORT_SYMBOL_GPL(i3c_master_enec_locked);
871
872/**
873 * i3c_master_defslvs_locked() - send a DEFSLVS CCC command
874 * @master: master used to send frames on the bus
875 *
876 * Send a DEFSLVS CCC command containing all the devices known to the @master.
877 * This is useful when you have secondary masters on the bus to propagate
878 * device information.
879 *
880 * This should be called after all I3C devices have been discovered (in other
881 * words, after the DAA procedure has finished) and instantiated in
882 * &i3c_master_controller_ops->bus_init().
883 * It should also be called if a master ACKed an Hot-Join request and assigned
884 * a dynamic address to the device joining the bus.
885 *
886 * This function must be called with the bus lock held in write mode.
887 *
888 * Return: 0 in case of success, a positive I3C error code if the error is
889 * one of the official Mx error codes, and a negative error code otherwise.
890 */
891int i3c_master_defslvs_locked(struct i3c_master_controller *master)
892{
893 struct i3c_ccc_defslvs *defslvs;
894 struct i3c_ccc_dev_desc *desc;
895 struct i3c_ccc_cmd_dest dest;
896 struct i3c_dev_desc *i3cdev;
897 struct i2c_dev_desc *i2cdev;
898 struct i3c_ccc_cmd cmd;
899 struct i3c_bus *bus;
900 bool send = false;
901 int ndevs = 0, ret;
902
903 if (!master)
904 return -EINVAL;
905
906 bus = i3c_master_get_bus(master);
907 i3c_bus_for_each_i3cdev(bus, i3cdev) {
908 ndevs++;
909
910 if (i3cdev == master->this)
911 continue;
912
913 if (I3C_BCR_DEVICE_ROLE(i3cdev->info.bcr) ==
914 I3C_BCR_I3C_MASTER)
915 send = true;
916 }
917
918 /* No other master on the bus, skip DEFSLVS. */
919 if (!send)
920 return 0;
921
922 i3c_bus_for_each_i2cdev(bus, i2cdev)
923 ndevs++;
924
925 defslvs = i3c_ccc_cmd_dest_init(&dest, I3C_BROADCAST_ADDR,
926 sizeof(*defslvs) +
927 ((ndevs - 1) *
928 sizeof(struct i3c_ccc_dev_desc)));
929 if (!defslvs)
930 return -ENOMEM;
931
932 defslvs->count = ndevs;
933 defslvs->master.bcr = master->this->info.bcr;
934 defslvs->master.dcr = master->this->info.dcr;
935 defslvs->master.dyn_addr = master->this->info.dyn_addr << 1;
936 defslvs->master.static_addr = I3C_BROADCAST_ADDR << 1;
937
938 desc = defslvs->slaves;
939 i3c_bus_for_each_i2cdev(bus, i2cdev) {
940 desc->lvr = i2cdev->boardinfo->lvr;
941 desc->static_addr = i2cdev->boardinfo->base.addr << 1;
942 desc++;
943 }
944
945 i3c_bus_for_each_i3cdev(bus, i3cdev) {
946 /* Skip the I3C dev representing this master. */
947 if (i3cdev == master->this)
948 continue;
949
950 desc->bcr = i3cdev->info.bcr;
951 desc->dcr = i3cdev->info.dcr;
952 desc->dyn_addr = i3cdev->info.dyn_addr << 1;
953 desc->static_addr = i3cdev->info.static_addr << 1;
954 desc++;
955 }
956
957 i3c_ccc_cmd_init(&cmd, false, I3C_CCC_DEFSLVS, &dest, 1);
958 ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
959 i3c_ccc_cmd_dest_cleanup(&dest);
960
961 return ret;
962}
963EXPORT_SYMBOL_GPL(i3c_master_defslvs_locked);
964
965static int i3c_master_setda_locked(struct i3c_master_controller *master,
966 u8 oldaddr, u8 newaddr, bool setdasa)
967{
968 struct i3c_ccc_cmd_dest dest;
969 struct i3c_ccc_setda *setda;
970 struct i3c_ccc_cmd cmd;
971 int ret;
972
973 if (!oldaddr || !newaddr)
974 return -EINVAL;
975
976 setda = i3c_ccc_cmd_dest_init(&dest, oldaddr, sizeof(*setda));
977 if (!setda)
978 return -ENOMEM;
979
980 setda->addr = newaddr << 1;
981 i3c_ccc_cmd_init(&cmd, false,
982 setdasa ? I3C_CCC_SETDASA : I3C_CCC_SETNEWDA,
983 &dest, 1);
984 ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
985 i3c_ccc_cmd_dest_cleanup(&dest);
986
987 return ret;
988}
989
990static int i3c_master_setdasa_locked(struct i3c_master_controller *master,
991 u8 static_addr, u8 dyn_addr)
992{
993 return i3c_master_setda_locked(master, static_addr, dyn_addr, true);
994}
995
996static int i3c_master_setnewda_locked(struct i3c_master_controller *master,
997 u8 oldaddr, u8 newaddr)
998{
999 return i3c_master_setda_locked(master, oldaddr, newaddr, false);
1000}
1001
1002static int i3c_master_getmrl_locked(struct i3c_master_controller *master,
1003 struct i3c_device_info *info)
1004{
1005 struct i3c_ccc_cmd_dest dest;
1006 unsigned int expected_len;
1007 struct i3c_ccc_mrl *mrl;
1008 struct i3c_ccc_cmd cmd;
1009 int ret;
1010
1011 mrl = i3c_ccc_cmd_dest_init(&dest, info->dyn_addr, sizeof(*mrl));
1012 if (!mrl)
1013 return -ENOMEM;
1014
1015 /*
1016 * When the device does not have IBI payload GETMRL only returns 2
1017 * bytes of data.
1018 */
1019 if (!(info->bcr & I3C_BCR_IBI_PAYLOAD))
1020 dest.payload.len -= 1;
1021
1022 expected_len = dest.payload.len;
1023 i3c_ccc_cmd_init(&cmd, true, I3C_CCC_GETMRL, &dest, 1);
1024 ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
1025 if (ret)
1026 goto out;
1027
1028 if (dest.payload.len != expected_len) {
1029 ret = -EIO;
1030 goto out;
1031 }
1032
1033 info->max_read_len = be16_to_cpu(mrl->read_len);
1034
1035 if (info->bcr & I3C_BCR_IBI_PAYLOAD)
1036 info->max_ibi_len = mrl->ibi_len;
1037
1038out:
1039 i3c_ccc_cmd_dest_cleanup(&dest);
1040
1041 return ret;
1042}
1043
1044static int i3c_master_getmwl_locked(struct i3c_master_controller *master,
1045 struct i3c_device_info *info)
1046{
1047 struct i3c_ccc_cmd_dest dest;
1048 struct i3c_ccc_mwl *mwl;
1049 struct i3c_ccc_cmd cmd;
1050 int ret;
1051
1052 mwl = i3c_ccc_cmd_dest_init(&dest, info->dyn_addr, sizeof(*mwl));
1053 if (!mwl)
1054 return -ENOMEM;
1055
1056 i3c_ccc_cmd_init(&cmd, true, I3C_CCC_GETMWL, &dest, 1);
1057 ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
1058 if (ret)
1059 goto out;
1060
1061 if (dest.payload.len != sizeof(*mwl))
1062 return -EIO;
1063
1064 info->max_write_len = be16_to_cpu(mwl->len);
1065
1066out:
1067 i3c_ccc_cmd_dest_cleanup(&dest);
1068
1069 return ret;
1070}
1071
1072static int i3c_master_getmxds_locked(struct i3c_master_controller *master,
1073 struct i3c_device_info *info)
1074{
1075 struct i3c_ccc_getmxds *getmaxds;
1076 struct i3c_ccc_cmd_dest dest;
1077 struct i3c_ccc_cmd cmd;
1078 int ret;
1079
1080 getmaxds = i3c_ccc_cmd_dest_init(&dest, info->dyn_addr,
1081 sizeof(*getmaxds));
1082 if (!getmaxds)
1083 return -ENOMEM;
1084
1085 i3c_ccc_cmd_init(&cmd, true, I3C_CCC_GETMXDS, &dest, 1);
1086 ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
1087 if (ret)
1088 goto out;
1089
1090 if (dest.payload.len != 2 && dest.payload.len != 5) {
1091 ret = -EIO;
1092 goto out;
1093 }
1094
1095 info->max_read_ds = getmaxds->maxrd;
1096 info->max_write_ds = getmaxds->maxwr;
1097 if (dest.payload.len == 5)
1098 info->max_read_turnaround = getmaxds->maxrdturn[0] |
1099 ((u32)getmaxds->maxrdturn[1] << 8) |
1100 ((u32)getmaxds->maxrdturn[2] << 16);
1101
1102out:
1103 i3c_ccc_cmd_dest_cleanup(&dest);
1104
1105 return ret;
1106}
1107
1108static int i3c_master_gethdrcap_locked(struct i3c_master_controller *master,
1109 struct i3c_device_info *info)
1110{
1111 struct i3c_ccc_gethdrcap *gethdrcap;
1112 struct i3c_ccc_cmd_dest dest;
1113 struct i3c_ccc_cmd cmd;
1114 int ret;
1115
1116 gethdrcap = i3c_ccc_cmd_dest_init(&dest, info->dyn_addr,
1117 sizeof(*gethdrcap));
1118 if (!gethdrcap)
1119 return -ENOMEM;
1120
1121 i3c_ccc_cmd_init(&cmd, true, I3C_CCC_GETHDRCAP, &dest, 1);
1122 ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
1123 if (ret)
1124 goto out;
1125
1126 if (dest.payload.len != 1) {
1127 ret = -EIO;
1128 goto out;
1129 }
1130
1131 info->hdr_cap = gethdrcap->modes;
1132
1133out:
1134 i3c_ccc_cmd_dest_cleanup(&dest);
1135
1136 return ret;
1137}
1138
1139static int i3c_master_getpid_locked(struct i3c_master_controller *master,
1140 struct i3c_device_info *info)
1141{
1142 struct i3c_ccc_getpid *getpid;
1143 struct i3c_ccc_cmd_dest dest;
1144 struct i3c_ccc_cmd cmd;
1145 int ret, i;
1146
1147 getpid = i3c_ccc_cmd_dest_init(&dest, info->dyn_addr, sizeof(*getpid));
1148 if (!getpid)
1149 return -ENOMEM;
1150
1151 i3c_ccc_cmd_init(&cmd, true, I3C_CCC_GETPID, &dest, 1);
1152 ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
1153 if (ret)
1154 goto out;
1155
1156 info->pid = 0;
1157 for (i = 0; i < sizeof(getpid->pid); i++) {
1158 int sft = (sizeof(getpid->pid) - i - 1) * 8;
1159
1160 info->pid |= (u64)getpid->pid[i] << sft;
1161 }
1162
1163out:
1164 i3c_ccc_cmd_dest_cleanup(&dest);
1165
1166 return ret;
1167}
1168
1169static int i3c_master_getbcr_locked(struct i3c_master_controller *master,
1170 struct i3c_device_info *info)
1171{
1172 struct i3c_ccc_getbcr *getbcr;
1173 struct i3c_ccc_cmd_dest dest;
1174 struct i3c_ccc_cmd cmd;
1175 int ret;
1176
1177 getbcr = i3c_ccc_cmd_dest_init(&dest, info->dyn_addr, sizeof(*getbcr));
1178 if (!getbcr)
1179 return -ENOMEM;
1180
1181 i3c_ccc_cmd_init(&cmd, true, I3C_CCC_GETBCR, &dest, 1);
1182 ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
1183 if (ret)
1184 goto out;
1185
1186 info->bcr = getbcr->bcr;
1187
1188out:
1189 i3c_ccc_cmd_dest_cleanup(&dest);
1190
1191 return ret;
1192}
1193
1194static int i3c_master_getdcr_locked(struct i3c_master_controller *master,
1195 struct i3c_device_info *info)
1196{
1197 struct i3c_ccc_getdcr *getdcr;
1198 struct i3c_ccc_cmd_dest dest;
1199 struct i3c_ccc_cmd cmd;
1200 int ret;
1201
1202 getdcr = i3c_ccc_cmd_dest_init(&dest, info->dyn_addr, sizeof(*getdcr));
1203 if (!getdcr)
1204 return -ENOMEM;
1205
1206 i3c_ccc_cmd_init(&cmd, true, I3C_CCC_GETDCR, &dest, 1);
1207 ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
1208 if (ret)
1209 goto out;
1210
1211 info->dcr = getdcr->dcr;
1212
1213out:
1214 i3c_ccc_cmd_dest_cleanup(&dest);
1215
1216 return ret;
1217}
1218
1219static int i3c_master_retrieve_dev_info(struct i3c_dev_desc *dev)
1220{
1221 struct i3c_master_controller *master = i3c_dev_get_master(dev);
1222 enum i3c_addr_slot_status slot_status;
1223 int ret;
1224
1225 if (!dev->info.dyn_addr)
1226 return -EINVAL;
1227
1228 slot_status = i3c_bus_get_addr_slot_status(&master->bus,
1229 dev->info.dyn_addr);
1230 if (slot_status == I3C_ADDR_SLOT_RSVD ||
1231 slot_status == I3C_ADDR_SLOT_I2C_DEV)
1232 return -EINVAL;
1233
1234 ret = i3c_master_getpid_locked(master, &dev->info);
1235 if (ret)
1236 return ret;
1237
1238 ret = i3c_master_getbcr_locked(master, &dev->info);
1239 if (ret)
1240 return ret;
1241
1242 ret = i3c_master_getdcr_locked(master, &dev->info);
1243 if (ret)
1244 return ret;
1245
1246 if (dev->info.bcr & I3C_BCR_MAX_DATA_SPEED_LIM) {
1247 ret = i3c_master_getmxds_locked(master, &dev->info);
1248 if (ret)
1249 return ret;
1250 }
1251
1252 if (dev->info.bcr & I3C_BCR_IBI_PAYLOAD)
1253 dev->info.max_ibi_len = 1;
1254
1255 i3c_master_getmrl_locked(master, &dev->info);
1256 i3c_master_getmwl_locked(master, &dev->info);
1257
1258 if (dev->info.bcr & I3C_BCR_HDR_CAP) {
1259 ret = i3c_master_gethdrcap_locked(master, &dev->info);
1260 if (ret)
1261 return ret;
1262 }
1263
1264 return 0;
1265}
1266
1267static void i3c_master_put_i3c_addrs(struct i3c_dev_desc *dev)
1268{
1269 struct i3c_master_controller *master = i3c_dev_get_master(dev);
1270
1271 if (dev->info.static_addr)
1272 i3c_bus_set_addr_slot_status(&master->bus,
1273 dev->info.static_addr,
1274 I3C_ADDR_SLOT_FREE);
1275
1276 if (dev->info.dyn_addr)
1277 i3c_bus_set_addr_slot_status(&master->bus, dev->info.dyn_addr,
1278 I3C_ADDR_SLOT_FREE);
1279
1280 if (dev->boardinfo && dev->boardinfo->init_dyn_addr)
1281 i3c_bus_set_addr_slot_status(&master->bus, dev->info.dyn_addr,
1282 I3C_ADDR_SLOT_FREE);
1283}
1284
1285static int i3c_master_get_i3c_addrs(struct i3c_dev_desc *dev)
1286{
1287 struct i3c_master_controller *master = i3c_dev_get_master(dev);
1288 enum i3c_addr_slot_status status;
1289
1290 if (!dev->info.static_addr && !dev->info.dyn_addr)
1291 return 0;
1292
1293 if (dev->info.static_addr) {
1294 status = i3c_bus_get_addr_slot_status(&master->bus,
1295 dev->info.static_addr);
1296 if (status != I3C_ADDR_SLOT_FREE)
1297 return -EBUSY;
1298
1299 i3c_bus_set_addr_slot_status(&master->bus,
1300 dev->info.static_addr,
1301 I3C_ADDR_SLOT_I3C_DEV);
1302 }
1303
1304 /*
1305 * ->init_dyn_addr should have been reserved before that, so, if we're
1306 * trying to apply a pre-reserved dynamic address, we should not try
1307 * to reserve the address slot a second time.
1308 */
1309 if (dev->info.dyn_addr &&
1310 (!dev->boardinfo ||
1311 dev->boardinfo->init_dyn_addr != dev->info.dyn_addr)) {
1312 status = i3c_bus_get_addr_slot_status(&master->bus,
1313 dev->info.dyn_addr);
1314 if (status != I3C_ADDR_SLOT_FREE)
1315 goto err_release_static_addr;
1316
1317 i3c_bus_set_addr_slot_status(&master->bus, dev->info.dyn_addr,
1318 I3C_ADDR_SLOT_I3C_DEV);
1319 }
1320
1321 return 0;
1322
1323err_release_static_addr:
1324 if (dev->info.static_addr)
1325 i3c_bus_set_addr_slot_status(&master->bus,
1326 dev->info.static_addr,
1327 I3C_ADDR_SLOT_FREE);
1328
1329 return -EBUSY;
1330}
1331
1332static int i3c_master_attach_i3c_dev(struct i3c_master_controller *master,
1333 struct i3c_dev_desc *dev)
1334{
1335 int ret;
1336
1337 /*
1338 * We don't attach devices to the controller until they are
1339 * addressable on the bus.
1340 */
1341 if (!dev->info.static_addr && !dev->info.dyn_addr)
1342 return 0;
1343
1344 ret = i3c_master_get_i3c_addrs(dev);
1345 if (ret)
1346 return ret;
1347
1348 /* Do not attach the master device itself. */
1349 if (master->this != dev && master->ops->attach_i3c_dev) {
1350 ret = master->ops->attach_i3c_dev(dev);
1351 if (ret) {
1352 i3c_master_put_i3c_addrs(dev);
1353 return ret;
1354 }
1355 }
1356
1357 list_add_tail(&dev->common.node, &master->bus.devs.i3c);
1358
1359 return 0;
1360}
1361
1362static int i3c_master_reattach_i3c_dev(struct i3c_dev_desc *dev,
1363 u8 old_dyn_addr)
1364{
1365 struct i3c_master_controller *master = i3c_dev_get_master(dev);
1366 enum i3c_addr_slot_status status;
1367 int ret;
1368
1369 if (dev->info.dyn_addr != old_dyn_addr) {
1370 status = i3c_bus_get_addr_slot_status(&master->bus,
1371 dev->info.dyn_addr);
1372 if (status != I3C_ADDR_SLOT_FREE)
1373 return -EBUSY;
1374 i3c_bus_set_addr_slot_status(&master->bus,
1375 dev->info.dyn_addr,
1376 I3C_ADDR_SLOT_I3C_DEV);
1377 }
1378
1379 if (master->ops->reattach_i3c_dev) {
1380 ret = master->ops->reattach_i3c_dev(dev, old_dyn_addr);
1381 if (ret) {
1382 i3c_master_put_i3c_addrs(dev);
1383 return ret;
1384 }
1385 }
1386
1387 return 0;
1388}
1389
1390static void i3c_master_detach_i3c_dev(struct i3c_dev_desc *dev)
1391{
1392 struct i3c_master_controller *master = i3c_dev_get_master(dev);
1393
1394 /* Do not detach the master device itself. */
1395 if (master->this != dev && master->ops->detach_i3c_dev)
1396 master->ops->detach_i3c_dev(dev);
1397
1398 i3c_master_put_i3c_addrs(dev);
1399 list_del(&dev->common.node);
1400}
1401
1402static int i3c_master_attach_i2c_dev(struct i3c_master_controller *master,
1403 struct i2c_dev_desc *dev)
1404{
1405 int ret;
1406
1407 if (master->ops->attach_i2c_dev) {
1408 ret = master->ops->attach_i2c_dev(dev);
1409 if (ret)
1410 return ret;
1411 }
1412
1413 list_add_tail(&dev->common.node, &master->bus.devs.i2c);
1414
1415 return 0;
1416}
1417
1418static void i3c_master_detach_i2c_dev(struct i2c_dev_desc *dev)
1419{
1420 struct i3c_master_controller *master = i2c_dev_get_master(dev);
1421
1422 list_del(&dev->common.node);
1423
1424 if (master->ops->detach_i2c_dev)
1425 master->ops->detach_i2c_dev(dev);
1426}
1427
1428static void i3c_master_pre_assign_dyn_addr(struct i3c_dev_desc *dev)
1429{
1430 struct i3c_master_controller *master = i3c_dev_get_master(dev);
1431 int ret;
1432
1433 if (!dev->boardinfo || !dev->boardinfo->init_dyn_addr ||
1434 !dev->boardinfo->static_addr)
1435 return;
1436
1437 ret = i3c_master_setdasa_locked(master, dev->info.static_addr,
1438 dev->boardinfo->init_dyn_addr);
1439 if (ret)
1440 return;
1441
1442 dev->info.dyn_addr = dev->boardinfo->init_dyn_addr;
1443 ret = i3c_master_reattach_i3c_dev(dev, 0);
1444 if (ret)
1445 goto err_rstdaa;
1446
1447 ret = i3c_master_retrieve_dev_info(dev);
1448 if (ret)
1449 goto err_rstdaa;
1450
1451 return;
1452
1453err_rstdaa:
1454 i3c_master_rstdaa_locked(master, dev->boardinfo->init_dyn_addr);
1455}
1456
1457static void
1458i3c_master_register_new_i3c_devs(struct i3c_master_controller *master)
1459{
1460 struct i3c_dev_desc *desc;
1461 int ret;
1462
1463 if (!master->init_done)
1464 return;
1465
1466 i3c_bus_for_each_i3cdev(&master->bus, desc) {
1467 if (desc->dev || !desc->info.dyn_addr || desc == master->this)
1468 continue;
1469
1470 desc->dev = kzalloc(sizeof(*desc->dev), GFP_KERNEL);
1471 if (!desc->dev)
1472 continue;
1473
1474 desc->dev->bus = &master->bus;
1475 desc->dev->desc = desc;
1476 desc->dev->dev.parent = &master->dev;
1477 desc->dev->dev.type = &i3c_device_type;
1478 desc->dev->dev.bus = &i3c_bus_type;
1479 desc->dev->dev.release = i3c_device_release;
1480 dev_set_name(&desc->dev->dev, "%d-%llx", master->bus.id,
1481 desc->info.pid);
1482
1483 if (desc->boardinfo)
1484 desc->dev->dev.of_node = desc->boardinfo->of_node;
1485
1486 ret = device_register(&desc->dev->dev);
1487 if (ret)
1488 dev_err(&master->dev,
1489 "Failed to add I3C device (err = %d)\n", ret);
1490 }
1491}
1492
1493/**
1494 * i3c_master_do_daa() - do a DAA (Dynamic Address Assignment)
1495 * @master: master doing the DAA
1496 *
1497 * This function is instantiating an I3C device object and adding it to the
1498 * I3C device list. All device information are automatically retrieved using
1499 * standard CCC commands.
1500 *
1501 * The I3C device object is returned in case the master wants to attach
1502 * private data to it using i3c_dev_set_master_data().
1503 *
1504 * This function must be called with the bus lock held in write mode.
1505 *
1506 * Return: a 0 in case of success, an negative error code otherwise.
1507 */
1508int i3c_master_do_daa(struct i3c_master_controller *master)
1509{
1510 int ret;
1511
1512 i3c_bus_maintenance_lock(&master->bus);
1513 ret = master->ops->do_daa(master);
1514 i3c_bus_maintenance_unlock(&master->bus);
1515
1516 if (ret)
1517 return ret;
1518
1519 i3c_bus_normaluse_lock(&master->bus);
1520 i3c_master_register_new_i3c_devs(master);
1521 i3c_bus_normaluse_unlock(&master->bus);
1522
1523 return 0;
1524}
1525EXPORT_SYMBOL_GPL(i3c_master_do_daa);
1526
1527/**
1528 * i3c_master_set_info() - set master device information
1529 * @master: master used to send frames on the bus
1530 * @info: I3C device information
1531 *
1532 * Set master device info. This should be called from
1533 * &i3c_master_controller_ops->bus_init().
1534 *
1535 * Not all &i3c_device_info fields are meaningful for a master device.
1536 * Here is a list of fields that should be properly filled:
1537 *
1538 * - &i3c_device_info->dyn_addr
1539 * - &i3c_device_info->bcr
1540 * - &i3c_device_info->dcr
1541 * - &i3c_device_info->pid
1542 * - &i3c_device_info->hdr_cap if %I3C_BCR_HDR_CAP bit is set in
1543 * &i3c_device_info->bcr
1544 *
1545 * This function must be called with the bus lock held in maintenance mode.
1546 *
1547 * Return: 0 if @info contains valid information (not every piece of
1548 * information can be checked, but we can at least make sure @info->dyn_addr
1549 * and @info->bcr are correct), -EINVAL otherwise.
1550 */
1551int i3c_master_set_info(struct i3c_master_controller *master,
1552 const struct i3c_device_info *info)
1553{
1554 struct i3c_dev_desc *i3cdev;
1555 int ret;
1556
1557 if (!i3c_bus_dev_addr_is_avail(&master->bus, info->dyn_addr))
1558 return -EINVAL;
1559
1560 if (I3C_BCR_DEVICE_ROLE(info->bcr) == I3C_BCR_I3C_MASTER &&
1561 master->secondary)
1562 return -EINVAL;
1563
1564 if (master->this)
1565 return -EINVAL;
1566
1567 i3cdev = i3c_master_alloc_i3c_dev(master, info);
1568 if (IS_ERR(i3cdev))
1569 return PTR_ERR(i3cdev);
1570
1571 master->this = i3cdev;
1572 master->bus.cur_master = master->this;
1573
1574 ret = i3c_master_attach_i3c_dev(master, i3cdev);
1575 if (ret)
1576 goto err_free_dev;
1577
1578 return 0;
1579
1580err_free_dev:
1581 i3c_master_free_i3c_dev(i3cdev);
1582
1583 return ret;
1584}
1585EXPORT_SYMBOL_GPL(i3c_master_set_info);
1586
1587static void i3c_master_detach_free_devs(struct i3c_master_controller *master)
1588{
1589 struct i3c_dev_desc *i3cdev, *i3ctmp;
1590 struct i2c_dev_desc *i2cdev, *i2ctmp;
1591
1592 list_for_each_entry_safe(i3cdev, i3ctmp, &master->bus.devs.i3c,
1593 common.node) {
1594 i3c_master_detach_i3c_dev(i3cdev);
1595
1596 if (i3cdev->boardinfo && i3cdev->boardinfo->init_dyn_addr)
1597 i3c_bus_set_addr_slot_status(&master->bus,
1598 i3cdev->boardinfo->init_dyn_addr,
1599 I3C_ADDR_SLOT_FREE);
1600
1601 i3c_master_free_i3c_dev(i3cdev);
1602 }
1603
1604 list_for_each_entry_safe(i2cdev, i2ctmp, &master->bus.devs.i2c,
1605 common.node) {
1606 i3c_master_detach_i2c_dev(i2cdev);
1607 i3c_bus_set_addr_slot_status(&master->bus,
1608 i2cdev->boardinfo->base.addr,
1609 I3C_ADDR_SLOT_FREE);
1610 i3c_master_free_i2c_dev(i2cdev);
1611 }
1612}
1613
1614/**
1615 * i3c_master_bus_init() - initialize an I3C bus
1616 * @master: main master initializing the bus
1617 *
1618 * This function is following all initialisation steps described in the I3C
1619 * specification:
1620 *
1621 * 1. Attach I2C and statically defined I3C devs to the master so that the
1622 * master can fill its internal device table appropriately
1623 *
1624 * 2. Call &i3c_master_controller_ops->bus_init() method to initialize
1625 * the master controller. That's usually where the bus mode is selected
1626 * (pure bus or mixed fast/slow bus)
1627 *
1628 * 3. Instruct all devices on the bus to drop their dynamic address. This is
1629 * particularly important when the bus was previously configured by someone
1630 * else (for example the bootloader)
1631 *
1632 * 4. Disable all slave events.
1633 *
1634 * 5. Pre-assign dynamic addresses requested by the FW with SETDASA for I3C
1635 * devices that have a static address
1636 *
1637 * 6. Do a DAA (Dynamic Address Assignment) to assign dynamic addresses to all
1638 * remaining I3C devices
1639 *
1640 * Once this is done, all I3C and I2C devices should be usable.
1641 *
1642 * Return: a 0 in case of success, an negative error code otherwise.
1643 */
1644static int i3c_master_bus_init(struct i3c_master_controller *master)
1645{
1646 enum i3c_addr_slot_status status;
1647 struct i2c_dev_boardinfo *i2cboardinfo;
1648 struct i3c_dev_boardinfo *i3cboardinfo;
1649 struct i3c_dev_desc *i3cdev;
1650 struct i2c_dev_desc *i2cdev;
1651 int ret;
1652
1653 /*
1654 * First attach all devices with static definitions provided by the
1655 * FW.
1656 */
1657 list_for_each_entry(i2cboardinfo, &master->boardinfo.i2c, node) {
1658 status = i3c_bus_get_addr_slot_status(&master->bus,
1659 i2cboardinfo->base.addr);
1660 if (status != I3C_ADDR_SLOT_FREE) {
1661 ret = -EBUSY;
1662 goto err_detach_devs;
1663 }
1664
1665 i3c_bus_set_addr_slot_status(&master->bus,
1666 i2cboardinfo->base.addr,
1667 I3C_ADDR_SLOT_I2C_DEV);
1668
1669 i2cdev = i3c_master_alloc_i2c_dev(master, i2cboardinfo);
1670 if (IS_ERR(i2cdev)) {
1671 ret = PTR_ERR(i2cdev);
1672 goto err_detach_devs;
1673 }
1674
1675 ret = i3c_master_attach_i2c_dev(master, i2cdev);
1676 if (ret) {
1677 i3c_master_free_i2c_dev(i2cdev);
1678 goto err_detach_devs;
1679 }
1680 }
1681 list_for_each_entry(i3cboardinfo, &master->boardinfo.i3c, node) {
1682 struct i3c_device_info info = {
1683 .static_addr = i3cboardinfo->static_addr,
1684 };
1685
1686 if (i3cboardinfo->init_dyn_addr) {
1687 status = i3c_bus_get_addr_slot_status(&master->bus,
1688 i3cboardinfo->init_dyn_addr);
1689 if (status != I3C_ADDR_SLOT_FREE) {
1690 ret = -EBUSY;
1691 goto err_detach_devs;
1692 }
1693 }
1694
1695 i3cdev = i3c_master_alloc_i3c_dev(master, &info);
1696 if (IS_ERR(i3cdev)) {
1697 ret = PTR_ERR(i3cdev);
1698 goto err_detach_devs;
1699 }
1700
1701 i3cdev->boardinfo = i3cboardinfo;
1702
1703 ret = i3c_master_attach_i3c_dev(master, i3cdev);
1704 if (ret) {
1705 i3c_master_free_i3c_dev(i3cdev);
1706 goto err_detach_devs;
1707 }
1708 }
1709
1710 /*
1711 * Now execute the controller specific ->bus_init() routine, which
1712 * might configure its internal logic to match the bus limitations.
1713 */
1714 ret = master->ops->bus_init(master);
1715 if (ret)
1716 goto err_detach_devs;
1717
1718 /*
1719 * The master device should have been instantiated in ->bus_init(),
1720 * complain if this was not the case.
1721 */
1722 if (!master->this) {
1723 dev_err(&master->dev,
1724 "master_set_info() was not called in ->bus_init()\n");
1725 ret = -EINVAL;
1726 goto err_bus_cleanup;
1727 }
1728
1729 /*
1730 * Reset all dynamic address that may have been assigned before
1731 * (assigned by the bootloader for example).
1732 */
1733 ret = i3c_master_rstdaa_locked(master, I3C_BROADCAST_ADDR);
1734 if (ret && ret != I3C_ERROR_M2)
1735 goto err_bus_cleanup;
1736
1737 /* Disable all slave events before starting DAA. */
1738 ret = i3c_master_disec_locked(master, I3C_BROADCAST_ADDR,
1739 I3C_CCC_EVENT_SIR | I3C_CCC_EVENT_MR |
1740 I3C_CCC_EVENT_HJ);
1741 if (ret && ret != I3C_ERROR_M2)
1742 goto err_bus_cleanup;
1743
1744 /*
1745 * Pre-assign dynamic address and retrieve device information if
1746 * needed.
1747 */
1748 i3c_bus_for_each_i3cdev(&master->bus, i3cdev)
1749 i3c_master_pre_assign_dyn_addr(i3cdev);
1750
1751 ret = i3c_master_do_daa(master);
1752 if (ret)
1753 goto err_rstdaa;
1754
1755 return 0;
1756
1757err_rstdaa:
1758 i3c_master_rstdaa_locked(master, I3C_BROADCAST_ADDR);
1759
1760err_bus_cleanup:
1761 if (master->ops->bus_cleanup)
1762 master->ops->bus_cleanup(master);
1763
1764err_detach_devs:
1765 i3c_master_detach_free_devs(master);
1766
1767 return ret;
1768}
1769
1770static void i3c_master_bus_cleanup(struct i3c_master_controller *master)
1771{
1772 if (master->ops->bus_cleanup)
1773 master->ops->bus_cleanup(master);
1774
1775 i3c_master_detach_free_devs(master);
1776}
1777
1778static struct i3c_dev_desc *
1779i3c_master_search_i3c_dev_duplicate(struct i3c_dev_desc *refdev)
1780{
1781 struct i3c_master_controller *master = refdev->common.master;
1782 struct i3c_dev_desc *i3cdev;
1783
1784 i3c_bus_for_each_i3cdev(&master->bus, i3cdev) {
1785 if (i3cdev != refdev && i3cdev->info.pid == refdev->info.pid)
1786 return i3cdev;
1787 }
1788
1789 return NULL;
1790}
1791
1792/**
1793 * i3c_master_add_i3c_dev_locked() - add an I3C slave to the bus
1794 * @master: master used to send frames on the bus
1795 * @addr: I3C slave dynamic address assigned to the device
1796 *
1797 * This function is instantiating an I3C device object and adding it to the
1798 * I3C device list. All device information are automatically retrieved using
1799 * standard CCC commands.
1800 *
1801 * The I3C device object is returned in case the master wants to attach
1802 * private data to it using i3c_dev_set_master_data().
1803 *
1804 * This function must be called with the bus lock held in write mode.
1805 *
1806 * Return: a 0 in case of success, an negative error code otherwise.
1807 */
1808int i3c_master_add_i3c_dev_locked(struct i3c_master_controller *master,
1809 u8 addr)
1810{
1811 struct i3c_device_info info = { .dyn_addr = addr };
1812 struct i3c_dev_desc *newdev, *olddev;
1813 u8 old_dyn_addr = addr, expected_dyn_addr;
1814 struct i3c_ibi_setup ibireq = { };
1815 bool enable_ibi = false;
1816 int ret;
1817
1818 if (!master)
1819 return -EINVAL;
1820
1821 newdev = i3c_master_alloc_i3c_dev(master, &info);
1822 if (IS_ERR(newdev))
1823 return PTR_ERR(newdev);
1824
1825 ret = i3c_master_attach_i3c_dev(master, newdev);
1826 if (ret)
1827 goto err_free_dev;
1828
1829 ret = i3c_master_retrieve_dev_info(newdev);
1830 if (ret)
1831 goto err_free_dev;
1832
1833 olddev = i3c_master_search_i3c_dev_duplicate(newdev);
1834 if (olddev) {
1835 newdev->boardinfo = olddev->boardinfo;
1836 newdev->info.static_addr = olddev->info.static_addr;
1837 newdev->dev = olddev->dev;
1838 if (newdev->dev)
1839 newdev->dev->desc = newdev;
1840
1841 /*
1842 * We need to restore the IBI state too, so let's save the
1843 * IBI information and try to restore them after olddev has
1844 * been detached+released and its IBI has been stopped and
1845 * the associated resources have been freed.
1846 */
1847 mutex_lock(&olddev->ibi_lock);
1848 if (olddev->ibi) {
1849 ibireq.handler = olddev->ibi->handler;
1850 ibireq.max_payload_len = olddev->ibi->max_payload_len;
1851 ibireq.num_slots = olddev->ibi->num_slots;
1852
1853 if (olddev->ibi->enabled) {
1854 enable_ibi = true;
1855 i3c_dev_disable_ibi_locked(olddev);
1856 }
1857
1858 i3c_dev_free_ibi_locked(olddev);
1859 }
1860 mutex_unlock(&olddev->ibi_lock);
1861
1862 old_dyn_addr = olddev->info.dyn_addr;
1863
1864 i3c_master_detach_i3c_dev(olddev);
1865 i3c_master_free_i3c_dev(olddev);
1866 }
1867
1868 ret = i3c_master_reattach_i3c_dev(newdev, old_dyn_addr);
1869 if (ret)
1870 goto err_detach_dev;
1871
1872 /*
1873 * Depending on our previous state, the expected dynamic address might
1874 * differ:
1875 * - if the device already had a dynamic address assigned, let's try to
1876 * re-apply this one
1877 * - if the device did not have a dynamic address and the firmware
1878 * requested a specific address, pick this one
1879 * - in any other case, keep the address automatically assigned by the
1880 * master
1881 */
1882 if (old_dyn_addr && old_dyn_addr != newdev->info.dyn_addr)
1883 expected_dyn_addr = old_dyn_addr;
1884 else if (newdev->boardinfo && newdev->boardinfo->init_dyn_addr)
1885 expected_dyn_addr = newdev->boardinfo->init_dyn_addr;
1886 else
1887 expected_dyn_addr = newdev->info.dyn_addr;
1888
1889 if (newdev->info.dyn_addr != expected_dyn_addr) {
1890 /*
1891 * Try to apply the expected dynamic address. If it fails, keep
1892 * the address assigned by the master.
1893 */
1894 ret = i3c_master_setnewda_locked(master,
1895 newdev->info.dyn_addr,
1896 expected_dyn_addr);
1897 if (!ret) {
1898 old_dyn_addr = newdev->info.dyn_addr;
1899 newdev->info.dyn_addr = expected_dyn_addr;
1900 i3c_master_reattach_i3c_dev(newdev, old_dyn_addr);
1901 } else {
1902 dev_err(&master->dev,
1903 "Failed to assign reserved/old address to device %d%llx",
1904 master->bus.id, newdev->info.pid);
1905 }
1906 }
1907
1908 /*
1909 * Now is time to try to restore the IBI setup. If we're lucky,
1910 * everything works as before, otherwise, all we can do is complain.
1911 * FIXME: maybe we should add callback to inform the driver that it
1912 * should request the IBI again instead of trying to hide that from
1913 * him.
1914 */
1915 if (ibireq.handler) {
1916 mutex_lock(&newdev->ibi_lock);
1917 ret = i3c_dev_request_ibi_locked(newdev, &ibireq);
1918 if (ret) {
1919 dev_err(&master->dev,
1920 "Failed to request IBI on device %d-%llx",
1921 master->bus.id, newdev->info.pid);
1922 } else if (enable_ibi) {
1923 ret = i3c_dev_enable_ibi_locked(newdev);
1924 if (ret)
1925 dev_err(&master->dev,
1926 "Failed to re-enable IBI on device %d-%llx",
1927 master->bus.id, newdev->info.pid);
1928 }
1929 mutex_unlock(&newdev->ibi_lock);
1930 }
1931
1932 return 0;
1933
1934err_detach_dev:
1935 if (newdev->dev && newdev->dev->desc)
1936 newdev->dev->desc = NULL;
1937
1938 i3c_master_detach_i3c_dev(newdev);
1939
1940err_free_dev:
1941 i3c_master_free_i3c_dev(newdev);
1942
1943 return ret;
1944}
1945EXPORT_SYMBOL_GPL(i3c_master_add_i3c_dev_locked);
1946
1947#define OF_I3C_REG1_IS_I2C_DEV BIT(31)
1948
1949static int
1950of_i3c_master_add_i2c_boardinfo(struct i3c_master_controller *master,
1951 struct device_node *node, u32 *reg)
1952{
1953 struct i2c_dev_boardinfo *boardinfo;
1954 struct device *dev = &master->dev;
1955 int ret;
1956
1957 boardinfo = devm_kzalloc(dev, sizeof(*boardinfo), GFP_KERNEL);
1958 if (!boardinfo)
1959 return -ENOMEM;
1960
1961 ret = of_i2c_get_board_info(dev, node, &boardinfo->base);
1962 if (ret)
1963 return ret;
1964
1965 /* LVR is encoded in reg[2]. */
1966 boardinfo->lvr = reg[2];
1967
1968 if (boardinfo->lvr & I3C_LVR_I2C_FM_MODE)
1969 master->bus.scl_rate.i2c = I3C_BUS_I2C_FM_SCL_RATE;
1970
1971 list_add_tail(&boardinfo->node, &master->boardinfo.i2c);
1972 of_node_get(node);
1973
1974 return 0;
1975}
1976
1977static int
1978of_i3c_master_add_i3c_boardinfo(struct i3c_master_controller *master,
1979 struct device_node *node, u32 *reg)
1980{
1981 struct i3c_dev_boardinfo *boardinfo;
1982 struct device *dev = &master->dev;
1983 struct i3c_device_info info = { };
1984 enum i3c_addr_slot_status addrstatus;
1985 u32 init_dyn_addr = 0;
1986
1987 boardinfo = devm_kzalloc(dev, sizeof(*boardinfo), GFP_KERNEL);
1988 if (!boardinfo)
1989 return -ENOMEM;
1990
1991 if (reg[0]) {
1992 if (reg[0] > I3C_MAX_ADDR)
1993 return -EINVAL;
1994
1995 addrstatus = i3c_bus_get_addr_slot_status(&master->bus,
1996 reg[0]);
1997 if (addrstatus != I3C_ADDR_SLOT_FREE)
1998 return -EINVAL;
1999 }
2000
2001 boardinfo->static_addr = reg[0];
2002
2003 if (!of_property_read_u32(node, "assigned-address", &init_dyn_addr)) {
2004 if (init_dyn_addr > I3C_MAX_ADDR)
2005 return -EINVAL;
2006
2007 addrstatus = i3c_bus_get_addr_slot_status(&master->bus,
2008 init_dyn_addr);
2009 if (addrstatus != I3C_ADDR_SLOT_FREE)
2010 return -EINVAL;
2011 }
2012
2013 boardinfo->pid = ((u64)reg[1] << 32) | reg[2];
2014
2015 if ((info.pid & GENMASK_ULL(63, 48)) ||
2016 I3C_PID_RND_LOWER_32BITS(info.pid))
2017 return -EINVAL;
2018
2019 boardinfo->init_dyn_addr = init_dyn_addr;
2020 boardinfo->of_node = of_node_get(node);
2021 list_add_tail(&boardinfo->node, &master->boardinfo.i3c);
2022
2023 return 0;
2024}
2025
2026static int of_i3c_master_add_dev(struct i3c_master_controller *master,
2027 struct device_node *node)
2028{
2029 u32 reg[3];
2030 int ret;
2031
2032 if (!master || !node)
2033 return -EINVAL;
2034
2035 ret = of_property_read_u32_array(node, "reg", reg, ARRAY_SIZE(reg));
2036 if (ret)
2037 return ret;
2038
2039 /*
2040 * The manufacturer ID can't be 0. If reg[1] == 0 that means we're
2041 * dealing with an I2C device.
2042 */
2043 if (!reg[1])
2044 ret = of_i3c_master_add_i2c_boardinfo(master, node, reg);
2045 else
2046 ret = of_i3c_master_add_i3c_boardinfo(master, node, reg);
2047
2048 return ret;
2049}
2050
2051static int of_populate_i3c_bus(struct i3c_master_controller *master)
2052{
2053 struct device *dev = &master->dev;
2054 struct device_node *i3cbus_np = dev->of_node;
2055 struct device_node *node;
2056 int ret;
2057 u32 val;
2058
2059 if (!i3cbus_np)
2060 return 0;
2061
2062 for_each_available_child_of_node(i3cbus_np, node) {
2063 ret = of_i3c_master_add_dev(master, node);
2064 if (ret)
2065 return ret;
2066 }
2067
2068 /*
2069 * The user might want to limit I2C and I3C speed in case some devices
2070 * on the bus are not supporting typical rates, or if the bus topology
2071 * prevents it from using max possible rate.
2072 */
2073 if (!of_property_read_u32(i3cbus_np, "i2c-scl-hz", &val))
2074 master->bus.scl_rate.i2c = val;
2075
2076 if (!of_property_read_u32(i3cbus_np, "i3c-scl-hz", &val))
2077 master->bus.scl_rate.i3c = val;
2078
2079 return 0;
2080}
2081
2082static int i3c_master_i2c_adapter_xfer(struct i2c_adapter *adap,
2083 struct i2c_msg *xfers, int nxfers)
2084{
2085 struct i3c_master_controller *master = i2c_adapter_to_i3c_master(adap);
2086 struct i2c_dev_desc *dev;
2087 int i, ret;
2088 u16 addr;
2089
2090 if (!xfers || !master || nxfers <= 0)
2091 return -EINVAL;
2092
2093 if (!master->ops->i2c_xfers)
2094 return -ENOTSUPP;
2095
2096 /* Doing transfers to different devices is not supported. */
2097 addr = xfers[0].addr;
2098 for (i = 1; i < nxfers; i++) {
2099 if (addr != xfers[i].addr)
2100 return -ENOTSUPP;
2101 }
2102
2103 i3c_bus_normaluse_lock(&master->bus);
2104 dev = i3c_master_find_i2c_dev_by_addr(master, addr);
2105 if (!dev)
2106 ret = -ENOENT;
2107 else
2108 ret = master->ops->i2c_xfers(dev, xfers, nxfers);
2109 i3c_bus_normaluse_unlock(&master->bus);
2110
2111 return ret ? ret : nxfers;
2112}
2113
2114static u32 i3c_master_i2c_functionalities(struct i2c_adapter *adap)
2115{
2116 struct i3c_master_controller *master = i2c_adapter_to_i3c_master(adap);
2117
2118 return master->ops->i2c_funcs(master);
2119}
2120
2121static const struct i2c_algorithm i3c_master_i2c_algo = {
2122 .master_xfer = i3c_master_i2c_adapter_xfer,
2123 .functionality = i3c_master_i2c_functionalities,
2124};
2125
2126static int i3c_master_i2c_adapter_init(struct i3c_master_controller *master)
2127{
2128 struct i2c_adapter *adap = i3c_master_to_i2c_adapter(master);
2129 struct i2c_dev_desc *i2cdev;
2130 int ret;
2131
2132 adap->dev.parent = master->dev.parent;
2133 adap->owner = master->dev.parent->driver->owner;
2134 adap->algo = &i3c_master_i2c_algo;
2135 strncpy(adap->name, dev_name(master->dev.parent), sizeof(adap->name));
2136
2137 /* FIXME: Should we allow i3c masters to override these values? */
2138 adap->timeout = 1000;
2139 adap->retries = 3;
2140
2141 ret = i2c_add_adapter(adap);
2142 if (ret)
2143 return ret;
2144
2145 /*
2146 * We silently ignore failures here. The bus should keep working
2147 * correctly even if one or more i2c devices are not registered.
2148 */
2149 i3c_bus_for_each_i2cdev(&master->bus, i2cdev)
2150 i2cdev->dev = i2c_new_device(adap, &i2cdev->boardinfo->base);
2151
2152 return 0;
2153}
2154
2155static void i3c_master_i2c_adapter_cleanup(struct i3c_master_controller *master)
2156{
2157 struct i2c_dev_desc *i2cdev;
2158
2159 i2c_del_adapter(&master->i2c);
2160
2161 i3c_bus_for_each_i2cdev(&master->bus, i2cdev)
2162 i2cdev->dev = NULL;
2163}
2164
2165static void i3c_master_unregister_i3c_devs(struct i3c_master_controller *master)
2166{
2167 struct i3c_dev_desc *i3cdev;
2168
2169 i3c_bus_for_each_i3cdev(&master->bus, i3cdev) {
2170 if (!i3cdev->dev)
2171 continue;
2172
2173 i3cdev->dev->desc = NULL;
2174 if (device_is_registered(&i3cdev->dev->dev))
2175 device_unregister(&i3cdev->dev->dev);
2176 else
2177 put_device(&i3cdev->dev->dev);
2178 i3cdev->dev = NULL;
2179 }
2180}
2181
2182/**
2183 * i3c_master_queue_ibi() - Queue an IBI
2184 * @dev: the device this IBI is coming from
2185 * @slot: the IBI slot used to store the payload
2186 *
2187 * Queue an IBI to the controller workqueue. The IBI handler attached to
2188 * the dev will be called from a workqueue context.
2189 */
2190void i3c_master_queue_ibi(struct i3c_dev_desc *dev, struct i3c_ibi_slot *slot)
2191{
2192 atomic_inc(&dev->ibi->pending_ibis);
2193 queue_work(dev->common.master->wq, &slot->work);
2194}
2195EXPORT_SYMBOL_GPL(i3c_master_queue_ibi);
2196
2197static void i3c_master_handle_ibi(struct work_struct *work)
2198{
2199 struct i3c_ibi_slot *slot = container_of(work, struct i3c_ibi_slot,
2200 work);
2201 struct i3c_dev_desc *dev = slot->dev;
2202 struct i3c_master_controller *master = i3c_dev_get_master(dev);
2203 struct i3c_ibi_payload payload;
2204
2205 payload.data = slot->data;
2206 payload.len = slot->len;
2207
2208 if (dev->dev)
2209 dev->ibi->handler(dev->dev, &payload);
2210
2211 master->ops->recycle_ibi_slot(dev, slot);
2212 if (atomic_dec_and_test(&dev->ibi->pending_ibis))
2213 complete(&dev->ibi->all_ibis_handled);
2214}
2215
2216static void i3c_master_init_ibi_slot(struct i3c_dev_desc *dev,
2217 struct i3c_ibi_slot *slot)
2218{
2219 slot->dev = dev;
2220 INIT_WORK(&slot->work, i3c_master_handle_ibi);
2221}
2222
2223struct i3c_generic_ibi_slot {
2224 struct list_head node;
2225 struct i3c_ibi_slot base;
2226};
2227
2228struct i3c_generic_ibi_pool {
2229 spinlock_t lock;
2230 unsigned int num_slots;
2231 struct i3c_generic_ibi_slot *slots;
2232 void *payload_buf;
2233 struct list_head free_slots;
2234 struct list_head pending;
2235};
2236
2237/**
2238 * i3c_generic_ibi_free_pool() - Free a generic IBI pool
2239 * @pool: the IBI pool to free
2240 *
2241 * Free all IBI slots allated by a generic IBI pool.
2242 */
2243void i3c_generic_ibi_free_pool(struct i3c_generic_ibi_pool *pool)
2244{
2245 struct i3c_generic_ibi_slot *slot;
2246 unsigned int nslots = 0;
2247
2248 while (!list_empty(&pool->free_slots)) {
2249 slot = list_first_entry(&pool->free_slots,
2250 struct i3c_generic_ibi_slot, node);
2251 list_del(&slot->node);
2252 nslots++;
2253 }
2254
2255 /*
2256 * If the number of freed slots is not equal to the number of allocated
2257 * slots we have a leak somewhere.
2258 */
2259 WARN_ON(nslots != pool->num_slots);
2260
2261 kfree(pool->payload_buf);
2262 kfree(pool->slots);
2263 kfree(pool);
2264}
2265EXPORT_SYMBOL_GPL(i3c_generic_ibi_free_pool);
2266
2267/**
2268 * i3c_generic_ibi_alloc_pool() - Create a generic IBI pool
2269 * @dev: the device this pool will be used for
2270 * @req: IBI setup request describing what the device driver expects
2271 *
2272 * Create a generic IBI pool based on the information provided in @req.
2273 *
2274 * Return: a valid IBI pool in case of success, an ERR_PTR() otherwise.
2275 */
2276struct i3c_generic_ibi_pool *
2277i3c_generic_ibi_alloc_pool(struct i3c_dev_desc *dev,
2278 const struct i3c_ibi_setup *req)
2279{
2280 struct i3c_generic_ibi_pool *pool;
2281 struct i3c_generic_ibi_slot *slot;
2282 unsigned int i;
2283 int ret;
2284
2285 pool = kzalloc(sizeof(*pool), GFP_KERNEL);
2286 if (!pool)
2287 return ERR_PTR(-ENOMEM);
2288
2289 spin_lock_init(&pool->lock);
2290 INIT_LIST_HEAD(&pool->free_slots);
2291 INIT_LIST_HEAD(&pool->pending);
2292
2293 pool->slots = kcalloc(req->num_slots, sizeof(*slot), GFP_KERNEL);
2294 if (!pool->slots) {
2295 ret = -ENOMEM;
2296 goto err_free_pool;
2297 }
2298
2299 if (req->max_payload_len) {
2300 pool->payload_buf = kcalloc(req->num_slots,
2301 req->max_payload_len, GFP_KERNEL);
2302 if (!pool->payload_buf) {
2303 ret = -ENOMEM;
2304 goto err_free_pool;
2305 }
2306 }
2307
2308 for (i = 0; i < req->num_slots; i++) {
2309 slot = &pool->slots[i];
2310 i3c_master_init_ibi_slot(dev, &slot->base);
2311
2312 if (req->max_payload_len)
2313 slot->base.data = pool->payload_buf +
2314 (i * req->max_payload_len);
2315
2316 list_add_tail(&slot->node, &pool->free_slots);
2317 pool->num_slots++;
2318 }
2319
2320 return pool;
2321
2322err_free_pool:
2323 i3c_generic_ibi_free_pool(pool);
2324 return ERR_PTR(ret);
2325}
2326EXPORT_SYMBOL_GPL(i3c_generic_ibi_alloc_pool);
2327
2328/**
2329 * i3c_generic_ibi_get_free_slot() - Get a free slot from a generic IBI pool
2330 * @pool: the pool to query an IBI slot on
2331 *
2332 * Search for a free slot in a generic IBI pool.
2333 * The slot should be returned to the pool using i3c_generic_ibi_recycle_slot()
2334 * when it's no longer needed.
2335 *
2336 * Return: a pointer to a free slot, or NULL if there's no free slot available.
2337 */
2338struct i3c_ibi_slot *
2339i3c_generic_ibi_get_free_slot(struct i3c_generic_ibi_pool *pool)
2340{
2341 struct i3c_generic_ibi_slot *slot;
2342 unsigned long flags;
2343
2344 spin_lock_irqsave(&pool->lock, flags);
2345 slot = list_first_entry_or_null(&pool->free_slots,
2346 struct i3c_generic_ibi_slot, node);
2347 if (slot)
2348 list_del(&slot->node);
2349 spin_unlock_irqrestore(&pool->lock, flags);
2350
2351 return slot ? &slot->base : NULL;
2352}
2353EXPORT_SYMBOL_GPL(i3c_generic_ibi_get_free_slot);
2354
2355/**
2356 * i3c_generic_ibi_recycle_slot() - Return a slot to a generic IBI pool
2357 * @pool: the pool to return the IBI slot to
2358 * @s: IBI slot to recycle
2359 *
2360 * Add an IBI slot back to its generic IBI pool. Should be called from the
2361 * master driver struct_master_controller_ops->recycle_ibi() method.
2362 */
2363void i3c_generic_ibi_recycle_slot(struct i3c_generic_ibi_pool *pool,
2364 struct i3c_ibi_slot *s)
2365{
2366 struct i3c_generic_ibi_slot *slot;
2367 unsigned long flags;
2368
2369 if (!s)
2370 return;
2371
2372 slot = container_of(s, struct i3c_generic_ibi_slot, base);
2373 spin_lock_irqsave(&pool->lock, flags);
2374 list_add_tail(&slot->node, &pool->free_slots);
2375 spin_unlock_irqrestore(&pool->lock, flags);
2376}
2377EXPORT_SYMBOL_GPL(i3c_generic_ibi_recycle_slot);
2378
2379static int i3c_master_check_ops(const struct i3c_master_controller_ops *ops)
2380{
2381 if (!ops || !ops->bus_init || !ops->priv_xfers ||
2382 !ops->send_ccc_cmd || !ops->do_daa || !ops->i2c_xfers ||
2383 !ops->i2c_funcs)
2384 return -EINVAL;
2385
2386 if (ops->request_ibi &&
2387 (!ops->enable_ibi || !ops->disable_ibi || !ops->free_ibi ||
2388 !ops->recycle_ibi_slot))
2389 return -EINVAL;
2390
2391 return 0;
2392}
2393
2394/**
2395 * i3c_master_register() - register an I3C master
2396 * @master: master used to send frames on the bus
2397 * @parent: the parent device (the one that provides this I3C master
2398 * controller)
2399 * @ops: the master controller operations
2400 * @secondary: true if you are registering a secondary master. Will return
2401 * -ENOTSUPP if set to true since secondary masters are not yet
2402 * supported
2403 *
2404 * This function takes care of everything for you:
2405 *
2406 * - creates and initializes the I3C bus
2407 * - populates the bus with static I2C devs if @parent->of_node is not
2408 * NULL
2409 * - registers all I3C devices added by the controller during bus
2410 * initialization
2411 * - registers the I2C adapter and all I2C devices
2412 *
2413 * Return: 0 in case of success, a negative error code otherwise.
2414 */
2415int i3c_master_register(struct i3c_master_controller *master,
2416 struct device *parent,
2417 const struct i3c_master_controller_ops *ops,
2418 bool secondary)
2419{
2420 struct i3c_bus *i3cbus = i3c_master_get_bus(master);
2421 enum i3c_bus_mode mode = I3C_BUS_MODE_PURE;
2422 struct i2c_dev_boardinfo *i2cbi;
2423 int ret;
2424
2425 /* We do not support secondary masters yet. */
2426 if (secondary)
2427 return -ENOTSUPP;
2428
2429 ret = i3c_master_check_ops(ops);
2430 if (ret)
2431 return ret;
2432
2433 master->dev.parent = parent;
2434 master->dev.of_node = of_node_get(parent->of_node);
2435 master->dev.bus = &i3c_bus_type;
2436 master->dev.type = &i3c_masterdev_type;
2437 master->dev.release = i3c_masterdev_release;
2438 master->ops = ops;
2439 master->secondary = secondary;
2440 INIT_LIST_HEAD(&master->boardinfo.i2c);
2441 INIT_LIST_HEAD(&master->boardinfo.i3c);
2442
2443 ret = i3c_bus_init(i3cbus);
2444 if (ret)
2445 return ret;
2446
2447 device_initialize(&master->dev);
2448 dev_set_name(&master->dev, "i3c-%d", i3cbus->id);
2449
2450 ret = of_populate_i3c_bus(master);
2451 if (ret)
2452 goto err_put_dev;
2453
2454 list_for_each_entry(i2cbi, &master->boardinfo.i2c, node) {
2455 switch (i2cbi->lvr & I3C_LVR_I2C_INDEX_MASK) {
2456 case I3C_LVR_I2C_INDEX(0):
2457 if (mode < I3C_BUS_MODE_MIXED_FAST)
2458 mode = I3C_BUS_MODE_MIXED_FAST;
2459 break;
2460 case I3C_LVR_I2C_INDEX(1):
2461 case I3C_LVR_I2C_INDEX(2):
2462 if (mode < I3C_BUS_MODE_MIXED_SLOW)
2463 mode = I3C_BUS_MODE_MIXED_SLOW;
2464 break;
2465 default:
2466 ret = -EINVAL;
2467 goto err_put_dev;
2468 }
2469 }
2470
2471 ret = i3c_bus_set_mode(i3cbus, mode);
2472 if (ret)
2473 goto err_put_dev;
2474
2475 master->wq = alloc_workqueue("%s", 0, 0, dev_name(parent));
2476 if (!master->wq) {
2477 ret = -ENOMEM;
2478 goto err_put_dev;
2479 }
2480
2481 ret = i3c_master_bus_init(master);
2482 if (ret)
2483 goto err_put_dev;
2484
2485 ret = device_add(&master->dev);
2486 if (ret)
2487 goto err_cleanup_bus;
2488
2489 /*
2490 * Expose our I3C bus as an I2C adapter so that I2C devices are exposed
2491 * through the I2C subsystem.
2492 */
2493 ret = i3c_master_i2c_adapter_init(master);
2494 if (ret)
2495 goto err_del_dev;
2496
2497 /*
2498 * We're done initializing the bus and the controller, we can now
2499 * register I3C devices dicovered during the initial DAA.
2500 */
2501 master->init_done = true;
2502 i3c_bus_normaluse_lock(&master->bus);
2503 i3c_master_register_new_i3c_devs(master);
2504 i3c_bus_normaluse_unlock(&master->bus);
2505
2506 return 0;
2507
2508err_del_dev:
2509 device_del(&master->dev);
2510
2511err_cleanup_bus:
2512 i3c_master_bus_cleanup(master);
2513
2514err_put_dev:
2515 put_device(&master->dev);
2516
2517 return ret;
2518}
2519EXPORT_SYMBOL_GPL(i3c_master_register);
2520
2521/**
2522 * i3c_master_unregister() - unregister an I3C master
2523 * @master: master used to send frames on the bus
2524 *
2525 * Basically undo everything done in i3c_master_register().
2526 *
2527 * Return: 0 in case of success, a negative error code otherwise.
2528 */
2529int i3c_master_unregister(struct i3c_master_controller *master)
2530{
2531 i3c_master_i2c_adapter_cleanup(master);
2532 i3c_master_unregister_i3c_devs(master);
2533 i3c_master_bus_cleanup(master);
2534 device_unregister(&master->dev);
2535
2536 return 0;
2537}
2538EXPORT_SYMBOL_GPL(i3c_master_unregister);
2539
2540int i3c_dev_do_priv_xfers_locked(struct i3c_dev_desc *dev,
2541 struct i3c_priv_xfer *xfers,
2542 int nxfers)
2543{
2544 struct i3c_master_controller *master;
2545
2546 if (!dev)
2547 return -ENOENT;
2548
2549 master = i3c_dev_get_master(dev);
2550 if (!master || !xfers)
2551 return -EINVAL;
2552
2553 if (!master->ops->priv_xfers)
2554 return -ENOTSUPP;
2555
2556 return master->ops->priv_xfers(dev, xfers, nxfers);
2557}
2558
2559int i3c_dev_disable_ibi_locked(struct i3c_dev_desc *dev)
2560{
2561 struct i3c_master_controller *master;
2562 int ret;
2563
2564 if (!dev->ibi)
2565 return -EINVAL;
2566
2567 master = i3c_dev_get_master(dev);
2568 ret = master->ops->disable_ibi(dev);
2569 if (ret)
2570 return ret;
2571
2572 reinit_completion(&dev->ibi->all_ibis_handled);
2573 if (atomic_read(&dev->ibi->pending_ibis))
2574 wait_for_completion(&dev->ibi->all_ibis_handled);
2575
2576 dev->ibi->enabled = false;
2577
2578 return 0;
2579}
2580
2581int i3c_dev_enable_ibi_locked(struct i3c_dev_desc *dev)
2582{
2583 struct i3c_master_controller *master = i3c_dev_get_master(dev);
2584 int ret;
2585
2586 if (!dev->ibi)
2587 return -EINVAL;
2588
2589 ret = master->ops->enable_ibi(dev);
2590 if (!ret)
2591 dev->ibi->enabled = true;
2592
2593 return ret;
2594}
2595
2596int i3c_dev_request_ibi_locked(struct i3c_dev_desc *dev,
2597 const struct i3c_ibi_setup *req)
2598{
2599 struct i3c_master_controller *master = i3c_dev_get_master(dev);
2600 struct i3c_device_ibi_info *ibi;
2601 int ret;
2602
2603 if (!master->ops->request_ibi)
2604 return -ENOTSUPP;
2605
2606 if (dev->ibi)
2607 return -EBUSY;
2608
2609 ibi = kzalloc(sizeof(*ibi), GFP_KERNEL);
2610 if (!ibi)
2611 return -ENOMEM;
2612
2613 atomic_set(&ibi->pending_ibis, 0);
2614 init_completion(&ibi->all_ibis_handled);
2615 ibi->handler = req->handler;
2616 ibi->max_payload_len = req->max_payload_len;
2617 ibi->num_slots = req->num_slots;
2618
2619 dev->ibi = ibi;
2620 ret = master->ops->request_ibi(dev, req);
2621 if (ret) {
2622 kfree(ibi);
2623 dev->ibi = NULL;
2624 }
2625
2626 return ret;
2627}
2628
2629void i3c_dev_free_ibi_locked(struct i3c_dev_desc *dev)
2630{
2631 struct i3c_master_controller *master = i3c_dev_get_master(dev);
2632
2633 if (!dev->ibi)
2634 return;
2635
2636 if (WARN_ON(dev->ibi->enabled))
2637 WARN_ON(i3c_dev_disable_ibi_locked(dev));
2638
2639 master->ops->free_ibi(dev);
2640 kfree(dev->ibi);
2641 dev->ibi = NULL;
2642}
2643
2644static int __init i3c_init(void)
2645{
2646 return bus_register(&i3c_bus_type);
2647}
2648subsys_initcall(i3c_init);
2649
2650static void __exit i3c_exit(void)
2651{
2652 idr_destroy(&i3c_bus_idr);
2653 bus_unregister(&i3c_bus_type);
2654}
2655module_exit(i3c_exit);
2656
2657MODULE_AUTHOR("Boris Brezillon <boris.brezillon@bootlin.com>");
2658MODULE_DESCRIPTION("I3C core");
2659MODULE_LICENSE("GPL v2");
diff --git a/drivers/i3c/master/Kconfig b/drivers/i3c/master/Kconfig
new file mode 100644
index 000000000000..26c6b585894e
--- /dev/null
+++ b/drivers/i3c/master/Kconfig
@@ -0,0 +1,22 @@
1config CDNS_I3C_MASTER
2 tristate "Cadence I3C master driver"
3 depends on I3C
4 depends on HAS_IOMEM
5 depends on !(ALPHA || PARISC)
6 help
7 Enable this driver if you want to support Cadence I3C master block.
8
9config DW_I3C_MASTER
10 tristate "Synospsys DesignWare I3C master driver"
11 depends on I3C
12 depends on HAS_IOMEM
13 depends on !(ALPHA || PARISC)
14 # ALPHA and PARISC needs {read,write}sl()
15 help
16 Support for Synopsys DesignWare MIPI I3C Controller.
17
18 For details please see
19 https://www.synopsys.com/dw/ipdir.php?ds=mipi_i3c
20
21 This driver can also be built as a module. If so, the module
22 will be called dw-i3c-master.
diff --git a/drivers/i3c/master/Makefile b/drivers/i3c/master/Makefile
new file mode 100644
index 000000000000..fc53939a0bb1
--- /dev/null
+++ b/drivers/i3c/master/Makefile
@@ -0,0 +1,2 @@
1obj-$(CONFIG_CDNS_I3C_MASTER) += i3c-master-cdns.o
2obj-$(CONFIG_DW_I3C_MASTER) += dw-i3c-master.o
diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c-master.c
new file mode 100644
index 000000000000..b532e2c9cf5c
--- /dev/null
+++ b/drivers/i3c/master/dw-i3c-master.c
@@ -0,0 +1,1216 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2018 Synopsys, Inc. and/or its affiliates.
4 *
5 * Author: Vitor Soares <vitor.soares@synopsys.com>
6 */
7
8#include <linux/bitops.h>
9#include <linux/clk.h>
10#include <linux/completion.h>
11#include <linux/err.h>
12#include <linux/errno.h>
13#include <linux/i3c/master.h>
14#include <linux/interrupt.h>
15#include <linux/ioport.h>
16#include <linux/iopoll.h>
17#include <linux/list.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/platform_device.h>
21#include <linux/reset.h>
22#include <linux/slab.h>
23
24#define DEVICE_CTRL 0x0
25#define DEV_CTRL_ENABLE BIT(31)
26#define DEV_CTRL_RESUME BIT(30)
27#define DEV_CTRL_HOT_JOIN_NACK BIT(8)
28#define DEV_CTRL_I2C_SLAVE_PRESENT BIT(7)
29
30#define DEVICE_ADDR 0x4
31#define DEV_ADDR_DYNAMIC_ADDR_VALID BIT(31)
32#define DEV_ADDR_DYNAMIC(x) (((x) << 16) & GENMASK(22, 16))
33
34#define HW_CAPABILITY 0x8
35#define COMMAND_QUEUE_PORT 0xc
36#define COMMAND_PORT_TOC BIT(30)
37#define COMMAND_PORT_READ_TRANSFER BIT(28)
38#define COMMAND_PORT_SDAP BIT(27)
39#define COMMAND_PORT_ROC BIT(26)
40#define COMMAND_PORT_SPEED(x) (((x) << 21) & GENMASK(23, 21))
41#define COMMAND_PORT_DEV_INDEX(x) (((x) << 16) & GENMASK(20, 16))
42#define COMMAND_PORT_CP BIT(15)
43#define COMMAND_PORT_CMD(x) (((x) << 7) & GENMASK(14, 7))
44#define COMMAND_PORT_TID(x) (((x) << 3) & GENMASK(6, 3))
45
46#define COMMAND_PORT_ARG_DATA_LEN(x) (((x) << 16) & GENMASK(31, 16))
47#define COMMAND_PORT_ARG_DATA_LEN_MAX 65536
48#define COMMAND_PORT_TRANSFER_ARG 0x01
49
50#define COMMAND_PORT_SDA_DATA_BYTE_3(x) (((x) << 24) & GENMASK(31, 24))
51#define COMMAND_PORT_SDA_DATA_BYTE_2(x) (((x) << 16) & GENMASK(23, 16))
52#define COMMAND_PORT_SDA_DATA_BYTE_1(x) (((x) << 8) & GENMASK(15, 8))
53#define COMMAND_PORT_SDA_BYTE_STRB_3 BIT(5)
54#define COMMAND_PORT_SDA_BYTE_STRB_2 BIT(4)
55#define COMMAND_PORT_SDA_BYTE_STRB_1 BIT(3)
56#define COMMAND_PORT_SHORT_DATA_ARG 0x02
57
58#define COMMAND_PORT_DEV_COUNT(x) (((x) << 21) & GENMASK(25, 21))
59#define COMMAND_PORT_ADDR_ASSGN_CMD 0x03
60
61#define RESPONSE_QUEUE_PORT 0x10
62#define RESPONSE_PORT_ERR_STATUS(x) (((x) & GENMASK(31, 28)) >> 28)
63#define RESPONSE_NO_ERROR 0
64#define RESPONSE_ERROR_CRC 1
65#define RESPONSE_ERROR_PARITY 2
66#define RESPONSE_ERROR_FRAME 3
67#define RESPONSE_ERROR_IBA_NACK 4
68#define RESPONSE_ERROR_ADDRESS_NACK 5
69#define RESPONSE_ERROR_OVER_UNDER_FLOW 6
70#define RESPONSE_ERROR_TRANSF_ABORT 8
71#define RESPONSE_ERROR_I2C_W_NACK_ERR 9
72#define RESPONSE_PORT_TID(x) (((x) & GENMASK(27, 24)) >> 24)
73#define RESPONSE_PORT_DATA_LEN(x) ((x) & GENMASK(15, 0))
74
75#define RX_TX_DATA_PORT 0x14
76#define IBI_QUEUE_STATUS 0x18
77#define QUEUE_THLD_CTRL 0x1c
78#define QUEUE_THLD_CTRL_RESP_BUF_MASK GENMASK(15, 8)
79#define QUEUE_THLD_CTRL_RESP_BUF(x) (((x) - 1) << 8)
80
81#define DATA_BUFFER_THLD_CTRL 0x20
82#define DATA_BUFFER_THLD_CTRL_RX_BUF GENMASK(11, 8)
83
84#define IBI_QUEUE_CTRL 0x24
85#define IBI_MR_REQ_REJECT 0x2C
86#define IBI_SIR_REQ_REJECT 0x30
87#define IBI_REQ_REJECT_ALL GENMASK(31, 0)
88
89#define RESET_CTRL 0x34
90#define RESET_CTRL_IBI_QUEUE BIT(5)
91#define RESET_CTRL_RX_FIFO BIT(4)
92#define RESET_CTRL_TX_FIFO BIT(3)
93#define RESET_CTRL_RESP_QUEUE BIT(2)
94#define RESET_CTRL_CMD_QUEUE BIT(1)
95#define RESET_CTRL_SOFT BIT(0)
96
97#define SLV_EVENT_CTRL 0x38
98#define INTR_STATUS 0x3c
99#define INTR_STATUS_EN 0x40
100#define INTR_SIGNAL_EN 0x44
101#define INTR_FORCE 0x48
102#define INTR_BUSOWNER_UPDATE_STAT BIT(13)
103#define INTR_IBI_UPDATED_STAT BIT(12)
104#define INTR_READ_REQ_RECV_STAT BIT(11)
105#define INTR_DEFSLV_STAT BIT(10)
106#define INTR_TRANSFER_ERR_STAT BIT(9)
107#define INTR_DYN_ADDR_ASSGN_STAT BIT(8)
108#define INTR_CCC_UPDATED_STAT BIT(6)
109#define INTR_TRANSFER_ABORT_STAT BIT(5)
110#define INTR_RESP_READY_STAT BIT(4)
111#define INTR_CMD_QUEUE_READY_STAT BIT(3)
112#define INTR_IBI_THLD_STAT BIT(2)
113#define INTR_RX_THLD_STAT BIT(1)
114#define INTR_TX_THLD_STAT BIT(0)
115#define INTR_ALL (INTR_BUSOWNER_UPDATE_STAT | \
116 INTR_IBI_UPDATED_STAT | \
117 INTR_READ_REQ_RECV_STAT | \
118 INTR_DEFSLV_STAT | \
119 INTR_TRANSFER_ERR_STAT | \
120 INTR_DYN_ADDR_ASSGN_STAT | \
121 INTR_CCC_UPDATED_STAT | \
122 INTR_TRANSFER_ABORT_STAT | \
123 INTR_RESP_READY_STAT | \
124 INTR_CMD_QUEUE_READY_STAT | \
125 INTR_IBI_THLD_STAT | \
126 INTR_TX_THLD_STAT | \
127 INTR_RX_THLD_STAT)
128
129#define INTR_MASTER_MASK (INTR_TRANSFER_ERR_STAT | \
130 INTR_RESP_READY_STAT)
131
132#define QUEUE_STATUS_LEVEL 0x4c
133#define QUEUE_STATUS_IBI_STATUS_CNT(x) (((x) & GENMASK(28, 24)) >> 24)
134#define QUEUE_STATUS_IBI_BUF_BLR(x) (((x) & GENMASK(23, 16)) >> 16)
135#define QUEUE_STATUS_LEVEL_RESP(x) (((x) & GENMASK(15, 8)) >> 8)
136#define QUEUE_STATUS_LEVEL_CMD(x) ((x) & GENMASK(7, 0))
137
138#define DATA_BUFFER_STATUS_LEVEL 0x50
139#define DATA_BUFFER_STATUS_LEVEL_TX(x) ((x) & GENMASK(7, 0))
140
141#define PRESENT_STATE 0x54
142#define CCC_DEVICE_STATUS 0x58
143#define DEVICE_ADDR_TABLE_POINTER 0x5c
144#define DEVICE_ADDR_TABLE_DEPTH(x) (((x) & GENMASK(31, 16)) >> 16)
145#define DEVICE_ADDR_TABLE_ADDR(x) ((x) & GENMASK(7, 0))
146
147#define DEV_CHAR_TABLE_POINTER 0x60
148#define VENDOR_SPECIFIC_REG_POINTER 0x6c
149#define SLV_PID_VALUE 0x74
150#define SLV_CHAR_CTRL 0x78
151#define SLV_MAX_LEN 0x7c
152#define MAX_READ_TURNAROUND 0x80
153#define MAX_DATA_SPEED 0x84
154#define SLV_DEBUG_STATUS 0x88
155#define SLV_INTR_REQ 0x8c
156#define DEVICE_CTRL_EXTENDED 0xb0
157#define SCL_I3C_OD_TIMING 0xb4
158#define SCL_I3C_PP_TIMING 0xb8
159#define SCL_I3C_TIMING_HCNT(x) (((x) << 16) & GENMASK(23, 16))
160#define SCL_I3C_TIMING_LCNT(x) ((x) & GENMASK(7, 0))
161#define SCL_I3C_TIMING_CNT_MIN 5
162
163#define SCL_I2C_FM_TIMING 0xbc
164#define SCL_I2C_FM_TIMING_HCNT(x) (((x) << 16) & GENMASK(31, 16))
165#define SCL_I2C_FM_TIMING_LCNT(x) ((x) & GENMASK(15, 0))
166
167#define SCL_I2C_FMP_TIMING 0xc0
168#define SCL_I2C_FMP_TIMING_HCNT(x) (((x) << 16) & GENMASK(23, 16))
169#define SCL_I2C_FMP_TIMING_LCNT(x) ((x) & GENMASK(15, 0))
170
171#define SCL_EXT_LCNT_TIMING 0xc8
172#define SCL_EXT_LCNT_4(x) (((x) << 24) & GENMASK(31, 24))
173#define SCL_EXT_LCNT_3(x) (((x) << 16) & GENMASK(23, 16))
174#define SCL_EXT_LCNT_2(x) (((x) << 8) & GENMASK(15, 8))
175#define SCL_EXT_LCNT_1(x) ((x) & GENMASK(7, 0))
176
177#define SCL_EXT_TERMN_LCNT_TIMING 0xcc
178#define BUS_FREE_TIMING 0xd4
179#define BUS_I3C_MST_FREE(x) ((x) & GENMASK(15, 0))
180
181#define BUS_IDLE_TIMING 0xd8
182#define I3C_VER_ID 0xe0
183#define I3C_VER_TYPE 0xe4
184#define EXTENDED_CAPABILITY 0xe8
185#define SLAVE_CONFIG 0xec
186
187#define DEV_ADDR_TABLE_LEGACY_I2C_DEV BIT(31)
188#define DEV_ADDR_TABLE_DYNAMIC_ADDR(x) (((x) << 16) & GENMASK(23, 16))
189#define DEV_ADDR_TABLE_STATIC_ADDR(x) ((x) & GENMASK(6, 0))
190#define DEV_ADDR_TABLE_LOC(start, idx) ((start) + ((idx) << 2))
191
192#define MAX_DEVS 32
193
194#define I3C_BUS_SDR1_SCL_RATE 8000000
195#define I3C_BUS_SDR2_SCL_RATE 6000000
196#define I3C_BUS_SDR3_SCL_RATE 4000000
197#define I3C_BUS_SDR4_SCL_RATE 2000000
198#define I3C_BUS_I2C_FM_TLOW_MIN_NS 1300
199#define I3C_BUS_I2C_FMP_TLOW_MIN_NS 500
200#define I3C_BUS_THIGH_MAX_NS 41
201
202#define XFER_TIMEOUT (msecs_to_jiffies(1000))
203
204struct dw_i3c_master_caps {
205 u8 cmdfifodepth;
206 u8 datafifodepth;
207};
208
209struct dw_i3c_cmd {
210 u32 cmd_lo;
211 u32 cmd_hi;
212 u16 tx_len;
213 const void *tx_buf;
214 u16 rx_len;
215 void *rx_buf;
216 u8 error;
217};
218
219struct dw_i3c_xfer {
220 struct list_head node;
221 struct completion comp;
222 int ret;
223 unsigned int ncmds;
224 struct dw_i3c_cmd cmds[0];
225};
226
227struct dw_i3c_master {
228 struct i3c_master_controller base;
229 u16 maxdevs;
230 u16 datstartaddr;
231 u32 free_pos;
232 struct {
233 struct list_head list;
234 struct dw_i3c_xfer *cur;
235 spinlock_t lock;
236 } xferqueue;
237 struct dw_i3c_master_caps caps;
238 void __iomem *regs;
239 struct reset_control *core_rst;
240 struct clk *core_clk;
241 char version[5];
242 char type[5];
243 u8 addrs[MAX_DEVS];
244};
245
246struct dw_i3c_i2c_dev_data {
247 u8 index;
248};
249
250static u8 even_parity(u8 p)
251{
252 p ^= p >> 4;
253 p &= 0xf;
254
255 return (0x9669 >> p) & 1;
256}
257
258static bool dw_i3c_master_supports_ccc_cmd(struct i3c_master_controller *m,
259 const struct i3c_ccc_cmd *cmd)
260{
261 if (cmd->ndests > 1)
262 return false;
263
264 switch (cmd->id) {
265 case I3C_CCC_ENEC(true):
266 case I3C_CCC_ENEC(false):
267 case I3C_CCC_DISEC(true):
268 case I3C_CCC_DISEC(false):
269 case I3C_CCC_ENTAS(0, true):
270 case I3C_CCC_ENTAS(0, false):
271 case I3C_CCC_RSTDAA(true):
272 case I3C_CCC_RSTDAA(false):
273 case I3C_CCC_ENTDAA:
274 case I3C_CCC_SETMWL(true):
275 case I3C_CCC_SETMWL(false):
276 case I3C_CCC_SETMRL(true):
277 case I3C_CCC_SETMRL(false):
278 case I3C_CCC_ENTHDR(0):
279 case I3C_CCC_SETDASA:
280 case I3C_CCC_SETNEWDA:
281 case I3C_CCC_GETMWL:
282 case I3C_CCC_GETMRL:
283 case I3C_CCC_GETPID:
284 case I3C_CCC_GETBCR:
285 case I3C_CCC_GETDCR:
286 case I3C_CCC_GETSTATUS:
287 case I3C_CCC_GETMXDS:
288 case I3C_CCC_GETHDRCAP:
289 return true;
290 default:
291 return false;
292 }
293}
294
295static inline struct dw_i3c_master *
296to_dw_i3c_master(struct i3c_master_controller *master)
297{
298 return container_of(master, struct dw_i3c_master, base);
299}
300
301static void dw_i3c_master_disable(struct dw_i3c_master *master)
302{
303 writel(readl(master->regs + DEVICE_CTRL) & DEV_CTRL_ENABLE,
304 master->regs + DEVICE_CTRL);
305}
306
307static void dw_i3c_master_enable(struct dw_i3c_master *master)
308{
309 writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_ENABLE,
310 master->regs + DEVICE_CTRL);
311}
312
313static int dw_i3c_master_get_addr_pos(struct dw_i3c_master *master, u8 addr)
314{
315 int pos;
316
317 for (pos = 0; pos < master->maxdevs; pos++) {
318 if (addr == master->addrs[pos])
319 return pos;
320 }
321
322 return -EINVAL;
323}
324
325static int dw_i3c_master_get_free_pos(struct dw_i3c_master *master)
326{
327 if (!(master->free_pos & GENMASK(master->maxdevs - 1, 0)))
328 return -ENOSPC;
329
330 return ffs(master->free_pos) - 1;
331}
332
333static void dw_i3c_master_wr_tx_fifo(struct dw_i3c_master *master,
334 const u8 *bytes, int nbytes)
335{
336 writesl(master->regs + RX_TX_DATA_PORT, bytes, nbytes / 4);
337 if (nbytes & 3) {
338 u32 tmp = 0;
339
340 memcpy(&tmp, bytes + (nbytes & ~3), nbytes & 3);
341 writesl(master->regs + RX_TX_DATA_PORT, &tmp, 1);
342 }
343}
344
345static void dw_i3c_master_read_rx_fifo(struct dw_i3c_master *master,
346 u8 *bytes, int nbytes)
347{
348 readsl(master->regs + RX_TX_DATA_PORT, bytes, nbytes / 4);
349 if (nbytes & 3) {
350 u32 tmp;
351
352 readsl(master->regs + RX_TX_DATA_PORT, &tmp, 1);
353 memcpy(bytes + (nbytes & ~3), &tmp, nbytes & 3);
354 }
355}
356
357static struct dw_i3c_xfer *
358dw_i3c_master_alloc_xfer(struct dw_i3c_master *master, unsigned int ncmds)
359{
360 struct dw_i3c_xfer *xfer;
361
362 xfer = kzalloc(struct_size(xfer, cmds, ncmds), GFP_KERNEL);
363 if (!xfer)
364 return NULL;
365
366 INIT_LIST_HEAD(&xfer->node);
367 xfer->ncmds = ncmds;
368 xfer->ret = -ETIMEDOUT;
369
370 return xfer;
371}
372
373static void dw_i3c_master_free_xfer(struct dw_i3c_xfer *xfer)
374{
375 kfree(xfer);
376}
377
378static void dw_i3c_master_start_xfer_locked(struct dw_i3c_master *master)
379{
380 struct dw_i3c_xfer *xfer = master->xferqueue.cur;
381 unsigned int i;
382 u32 thld_ctrl;
383
384 if (!xfer)
385 return;
386
387 for (i = 0; i < xfer->ncmds; i++) {
388 struct dw_i3c_cmd *cmd = &xfer->cmds[i];
389
390 dw_i3c_master_wr_tx_fifo(master, cmd->tx_buf, cmd->tx_len);
391 }
392
393 thld_ctrl = readl(master->regs + QUEUE_THLD_CTRL);
394 thld_ctrl &= ~QUEUE_THLD_CTRL_RESP_BUF_MASK;
395 thld_ctrl |= QUEUE_THLD_CTRL_RESP_BUF(xfer->ncmds);
396 writel(thld_ctrl, master->regs + QUEUE_THLD_CTRL);
397
398 for (i = 0; i < xfer->ncmds; i++) {
399 struct dw_i3c_cmd *cmd = &xfer->cmds[i];
400
401 writel(cmd->cmd_hi, master->regs + COMMAND_QUEUE_PORT);
402 writel(cmd->cmd_lo, master->regs + COMMAND_QUEUE_PORT);
403 }
404}
405
406static void dw_i3c_master_enqueue_xfer(struct dw_i3c_master *master,
407 struct dw_i3c_xfer *xfer)
408{
409 unsigned long flags;
410
411 init_completion(&xfer->comp);
412 spin_lock_irqsave(&master->xferqueue.lock, flags);
413 if (master->xferqueue.cur) {
414 list_add_tail(&xfer->node, &master->xferqueue.list);
415 } else {
416 master->xferqueue.cur = xfer;
417 dw_i3c_master_start_xfer_locked(master);
418 }
419 spin_unlock_irqrestore(&master->xferqueue.lock, flags);
420}
421
422static void dw_i3c_master_dequeue_xfer(struct dw_i3c_master *master,
423 struct dw_i3c_xfer *xfer)
424{
425 unsigned long flags;
426
427 spin_lock_irqsave(&master->xferqueue.lock, flags);
428 if (master->xferqueue.cur == xfer) {
429 u32 status;
430
431 master->xferqueue.cur = NULL;
432
433 writel(RESET_CTRL_RX_FIFO | RESET_CTRL_TX_FIFO |
434 RESET_CTRL_RESP_QUEUE | RESET_CTRL_CMD_QUEUE,
435 master->regs + RESET_CTRL);
436
437 readl_poll_timeout_atomic(master->regs + RESET_CTRL, status,
438 !status, 10, 1000000);
439 } else {
440 list_del_init(&xfer->node);
441 }
442 spin_unlock_irqrestore(&master->xferqueue.lock, flags);
443}
444
445static void dw_i3c_master_end_xfer_locked(struct dw_i3c_master *master, u32 isr)
446{
447 struct dw_i3c_xfer *xfer = master->xferqueue.cur;
448 int i, ret = 0;
449 u32 nresp;
450
451 if (!xfer)
452 return;
453
454 nresp = readl(master->regs + QUEUE_STATUS_LEVEL);
455 nresp = QUEUE_STATUS_LEVEL_RESP(nresp);
456
457 for (i = 0; i < nresp; i++) {
458 struct dw_i3c_cmd *cmd;
459 u32 resp;
460
461 resp = readl(master->regs + RESPONSE_QUEUE_PORT);
462
463 cmd = &xfer->cmds[RESPONSE_PORT_TID(resp)];
464 cmd->rx_len = RESPONSE_PORT_DATA_LEN(resp);
465 cmd->error = RESPONSE_PORT_ERR_STATUS(resp);
466 if (cmd->rx_len && !cmd->error)
467 dw_i3c_master_read_rx_fifo(master, cmd->rx_buf,
468 cmd->rx_len);
469 }
470
471 for (i = 0; i < nresp; i++) {
472 switch (xfer->cmds[i].error) {
473 case RESPONSE_NO_ERROR:
474 break;
475 case RESPONSE_ERROR_PARITY:
476 case RESPONSE_ERROR_IBA_NACK:
477 case RESPONSE_ERROR_TRANSF_ABORT:
478 case RESPONSE_ERROR_CRC:
479 case RESPONSE_ERROR_FRAME:
480 ret = -EIO;
481 break;
482 case RESPONSE_ERROR_OVER_UNDER_FLOW:
483 ret = -ENOSPC;
484 break;
485 case RESPONSE_ERROR_I2C_W_NACK_ERR:
486 case RESPONSE_ERROR_ADDRESS_NACK:
487 default:
488 ret = -EINVAL;
489 break;
490 }
491 }
492
493 xfer->ret = ret;
494 complete(&xfer->comp);
495
496 if (ret < 0) {
497 dw_i3c_master_dequeue_xfer(master, xfer);
498 writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_RESUME,
499 master->regs + DEVICE_CTRL);
500 }
501
502 xfer = list_first_entry_or_null(&master->xferqueue.list,
503 struct dw_i3c_xfer,
504 node);
505 if (xfer)
506 list_del_init(&xfer->node);
507
508 master->xferqueue.cur = xfer;
509 dw_i3c_master_start_xfer_locked(master);
510}
511
512static int dw_i3c_clk_cfg(struct dw_i3c_master *master)
513{
514 unsigned long core_rate, core_period;
515 u32 scl_timing;
516 u8 hcnt, lcnt;
517
518 core_rate = clk_get_rate(master->core_clk);
519 if (!core_rate)
520 return -EINVAL;
521
522 core_period = DIV_ROUND_UP(1000000000, core_rate);
523
524 hcnt = DIV_ROUND_UP(I3C_BUS_THIGH_MAX_NS, core_period) - 1;
525 if (hcnt < SCL_I3C_TIMING_CNT_MIN)
526 hcnt = SCL_I3C_TIMING_CNT_MIN;
527
528 lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_TYP_I3C_SCL_RATE) - hcnt;
529 if (lcnt < SCL_I3C_TIMING_CNT_MIN)
530 lcnt = SCL_I3C_TIMING_CNT_MIN;
531
532 scl_timing = SCL_I3C_TIMING_HCNT(hcnt) | SCL_I3C_TIMING_LCNT(lcnt);
533 writel(scl_timing, master->regs + SCL_I3C_PP_TIMING);
534
535 if (!(readl(master->regs + DEVICE_CTRL) & DEV_CTRL_I2C_SLAVE_PRESENT))
536 writel(BUS_I3C_MST_FREE(lcnt), master->regs + BUS_FREE_TIMING);
537
538 lcnt = DIV_ROUND_UP(I3C_BUS_TLOW_OD_MIN_NS, core_period);
539 scl_timing = SCL_I3C_TIMING_HCNT(hcnt) | SCL_I3C_TIMING_LCNT(lcnt);
540 writel(scl_timing, master->regs + SCL_I3C_OD_TIMING);
541
542 lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR1_SCL_RATE) - hcnt;
543 scl_timing = SCL_EXT_LCNT_1(lcnt);
544 lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR2_SCL_RATE) - hcnt;
545 scl_timing |= SCL_EXT_LCNT_2(lcnt);
546 lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR3_SCL_RATE) - hcnt;
547 scl_timing |= SCL_EXT_LCNT_3(lcnt);
548 lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR4_SCL_RATE) - hcnt;
549 scl_timing |= SCL_EXT_LCNT_4(lcnt);
550 writel(scl_timing, master->regs + SCL_EXT_LCNT_TIMING);
551
552 return 0;
553}
554
555static int dw_i2c_clk_cfg(struct dw_i3c_master *master)
556{
557 unsigned long core_rate, core_period;
558 u16 hcnt, lcnt;
559 u32 scl_timing;
560
561 core_rate = clk_get_rate(master->core_clk);
562 if (!core_rate)
563 return -EINVAL;
564
565 core_period = DIV_ROUND_UP(1000000000, core_rate);
566
567 lcnt = DIV_ROUND_UP(I3C_BUS_I2C_FMP_TLOW_MIN_NS, core_period);
568 hcnt = DIV_ROUND_UP(core_rate, I3C_BUS_I2C_FM_PLUS_SCL_RATE) - lcnt;
569 scl_timing = SCL_I2C_FMP_TIMING_HCNT(hcnt) |
570 SCL_I2C_FMP_TIMING_LCNT(lcnt);
571 writel(scl_timing, master->regs + SCL_I2C_FMP_TIMING);
572
573 lcnt = DIV_ROUND_UP(I3C_BUS_I2C_FM_TLOW_MIN_NS, core_period);
574 hcnt = DIV_ROUND_UP(core_rate, I3C_BUS_I2C_FM_SCL_RATE) - lcnt;
575 scl_timing = SCL_I2C_FM_TIMING_HCNT(hcnt) |
576 SCL_I2C_FM_TIMING_LCNT(lcnt);
577 writel(scl_timing, master->regs + SCL_I2C_FM_TIMING);
578
579 writel(BUS_I3C_MST_FREE(lcnt), master->regs + BUS_FREE_TIMING);
580 writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_I2C_SLAVE_PRESENT,
581 master->regs + DEVICE_CTRL);
582
583 return 0;
584}
585
586static int dw_i3c_master_bus_init(struct i3c_master_controller *m)
587{
588 struct dw_i3c_master *master = to_dw_i3c_master(m);
589 struct i3c_bus *bus = i3c_master_get_bus(m);
590 struct i3c_device_info info = { };
591 u32 thld_ctrl;
592 int ret;
593
594 switch (bus->mode) {
595 case I3C_BUS_MODE_MIXED_FAST:
596 ret = dw_i2c_clk_cfg(master);
597 if (ret)
598 return ret;
599 case I3C_BUS_MODE_PURE:
600 ret = dw_i3c_clk_cfg(master);
601 if (ret)
602 return ret;
603 break;
604 default:
605 return -EINVAL;
606 }
607
608 thld_ctrl = readl(master->regs + QUEUE_THLD_CTRL);
609 thld_ctrl &= ~QUEUE_THLD_CTRL_RESP_BUF_MASK;
610 writel(thld_ctrl, master->regs + QUEUE_THLD_CTRL);
611
612 thld_ctrl = readl(master->regs + DATA_BUFFER_THLD_CTRL);
613 thld_ctrl &= ~DATA_BUFFER_THLD_CTRL_RX_BUF;
614 writel(thld_ctrl, master->regs + DATA_BUFFER_THLD_CTRL);
615
616 writel(INTR_ALL, master->regs + INTR_STATUS);
617 writel(INTR_MASTER_MASK, master->regs + INTR_STATUS_EN);
618 writel(INTR_MASTER_MASK, master->regs + INTR_SIGNAL_EN);
619
620 ret = i3c_master_get_free_addr(m, 0);
621 if (ret < 0)
622 return ret;
623
624 writel(DEV_ADDR_DYNAMIC_ADDR_VALID | DEV_ADDR_DYNAMIC(ret),
625 master->regs + DEVICE_ADDR);
626
627 memset(&info, 0, sizeof(info));
628 info.dyn_addr = ret;
629
630 ret = i3c_master_set_info(&master->base, &info);
631 if (ret)
632 return ret;
633
634 writel(IBI_REQ_REJECT_ALL, master->regs + IBI_SIR_REQ_REJECT);
635 writel(IBI_REQ_REJECT_ALL, master->regs + IBI_MR_REQ_REJECT);
636
637 /* For now don't support Hot-Join */
638 writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_HOT_JOIN_NACK,
639 master->regs + DEVICE_CTRL);
640
641 dw_i3c_master_enable(master);
642
643 return 0;
644}
645
646static void dw_i3c_master_bus_cleanup(struct i3c_master_controller *m)
647{
648 struct dw_i3c_master *master = to_dw_i3c_master(m);
649
650 dw_i3c_master_disable(master);
651}
652
653static int dw_i3c_ccc_set(struct dw_i3c_master *master,
654 struct i3c_ccc_cmd *ccc)
655{
656 struct dw_i3c_xfer *xfer;
657 struct dw_i3c_cmd *cmd;
658 int ret, pos = 0;
659
660 if (ccc->id & I3C_CCC_DIRECT) {
661 pos = dw_i3c_master_get_addr_pos(master, ccc->dests[0].addr);
662 if (pos < 0)
663 return pos;
664 }
665
666 xfer = dw_i3c_master_alloc_xfer(master, 1);
667 if (!xfer)
668 return -ENOMEM;
669
670 cmd = xfer->cmds;
671 cmd->tx_buf = ccc->dests[0].payload.data;
672 cmd->tx_len = ccc->dests[0].payload.len;
673
674 cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(ccc->dests[0].payload.len) |
675 COMMAND_PORT_TRANSFER_ARG;
676
677 cmd->cmd_lo = COMMAND_PORT_CP |
678 COMMAND_PORT_DEV_INDEX(pos) |
679 COMMAND_PORT_CMD(ccc->id) |
680 COMMAND_PORT_TOC |
681 COMMAND_PORT_ROC;
682
683 dw_i3c_master_enqueue_xfer(master, xfer);
684 if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT))
685 dw_i3c_master_dequeue_xfer(master, xfer);
686
687 ret = xfer->ret;
688 if (xfer->cmds[0].error == RESPONSE_ERROR_IBA_NACK)
689 ccc->err = I3C_ERROR_M2;
690
691 dw_i3c_master_free_xfer(xfer);
692
693 return ret;
694}
695
696static int dw_i3c_ccc_get(struct dw_i3c_master *master, struct i3c_ccc_cmd *ccc)
697{
698 struct dw_i3c_xfer *xfer;
699 struct dw_i3c_cmd *cmd;
700 int ret, pos;
701
702 pos = dw_i3c_master_get_addr_pos(master, ccc->dests[0].addr);
703 if (pos < 0)
704 return pos;
705
706 xfer = dw_i3c_master_alloc_xfer(master, 1);
707 if (!xfer)
708 return -ENOMEM;
709
710 cmd = xfer->cmds;
711 cmd->rx_buf = ccc->dests[0].payload.data;
712 cmd->rx_len = ccc->dests[0].payload.len;
713
714 cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(ccc->dests[0].payload.len) |
715 COMMAND_PORT_TRANSFER_ARG;
716
717 cmd->cmd_lo = COMMAND_PORT_READ_TRANSFER |
718 COMMAND_PORT_CP |
719 COMMAND_PORT_DEV_INDEX(pos) |
720 COMMAND_PORT_CMD(ccc->id) |
721 COMMAND_PORT_TOC |
722 COMMAND_PORT_ROC;
723
724 dw_i3c_master_enqueue_xfer(master, xfer);
725 if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT))
726 dw_i3c_master_dequeue_xfer(master, xfer);
727
728 ret = xfer->ret;
729 if (xfer->cmds[0].error == RESPONSE_ERROR_IBA_NACK)
730 ccc->err = I3C_ERROR_M2;
731 dw_i3c_master_free_xfer(xfer);
732
733 return ret;
734}
735
736static int dw_i3c_master_send_ccc_cmd(struct i3c_master_controller *m,
737 struct i3c_ccc_cmd *ccc)
738{
739 struct dw_i3c_master *master = to_dw_i3c_master(m);
740 int ret = 0;
741
742 if (ccc->id == I3C_CCC_ENTDAA)
743 return -EINVAL;
744
745 if (ccc->rnw)
746 ret = dw_i3c_ccc_get(master, ccc);
747 else
748 ret = dw_i3c_ccc_set(master, ccc);
749
750 return ret;
751}
752
753static int dw_i3c_master_daa(struct i3c_master_controller *m)
754{
755 struct dw_i3c_master *master = to_dw_i3c_master(m);
756 struct dw_i3c_xfer *xfer;
757 struct dw_i3c_cmd *cmd;
758 u32 olddevs, newdevs;
759 u8 p, last_addr = 0;
760 int ret, pos;
761
762 olddevs = ~(master->free_pos);
763
764 /* Prepare DAT before launching DAA. */
765 for (pos = 0; pos < master->maxdevs; pos++) {
766 if (olddevs & BIT(pos))
767 continue;
768
769 ret = i3c_master_get_free_addr(m, last_addr + 1);
770 if (ret < 0)
771 return -ENOSPC;
772
773 master->addrs[pos] = ret;
774 p = even_parity(ret);
775 last_addr = ret;
776 ret |= (p << 7);
777
778 writel(DEV_ADDR_TABLE_DYNAMIC_ADDR(ret),
779 master->regs +
780 DEV_ADDR_TABLE_LOC(master->datstartaddr, pos));
781 }
782
783 xfer = dw_i3c_master_alloc_xfer(master, 1);
784 if (!xfer)
785 return -ENOMEM;
786
787 pos = dw_i3c_master_get_free_pos(master);
788 cmd = &xfer->cmds[0];
789 cmd->cmd_hi = 0x1;
790 cmd->cmd_lo = COMMAND_PORT_DEV_COUNT(master->maxdevs - pos) |
791 COMMAND_PORT_DEV_INDEX(pos) |
792 COMMAND_PORT_CMD(I3C_CCC_ENTDAA) |
793 COMMAND_PORT_ADDR_ASSGN_CMD |
794 COMMAND_PORT_TOC |
795 COMMAND_PORT_ROC;
796
797 dw_i3c_master_enqueue_xfer(master, xfer);
798 if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT))
799 dw_i3c_master_dequeue_xfer(master, xfer);
800
801 newdevs = GENMASK(master->maxdevs - cmd->rx_len - 1, 0);
802 newdevs &= ~olddevs;
803
804 for (pos = 0; pos < master->maxdevs; pos++) {
805 if (newdevs & BIT(pos))
806 i3c_master_add_i3c_dev_locked(m, master->addrs[pos]);
807 }
808
809 dw_i3c_master_free_xfer(xfer);
810
811 i3c_master_disec_locked(m, I3C_BROADCAST_ADDR,
812 I3C_CCC_EVENT_HJ |
813 I3C_CCC_EVENT_MR |
814 I3C_CCC_EVENT_SIR);
815
816 return 0;
817}
818
819static int dw_i3c_master_priv_xfers(struct i3c_dev_desc *dev,
820 struct i3c_priv_xfer *i3c_xfers,
821 int i3c_nxfers)
822{
823 struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
824 struct i3c_master_controller *m = i3c_dev_get_master(dev);
825 struct dw_i3c_master *master = to_dw_i3c_master(m);
826 unsigned int nrxwords = 0, ntxwords = 0;
827 struct dw_i3c_xfer *xfer;
828 int i, ret = 0;
829
830 if (!i3c_nxfers)
831 return 0;
832
833 if (i3c_nxfers > master->caps.cmdfifodepth)
834 return -ENOTSUPP;
835
836 for (i = 0; i < i3c_nxfers; i++) {
837 if (i3c_xfers[i].len > COMMAND_PORT_ARG_DATA_LEN_MAX)
838 return -ENOTSUPP;
839 }
840
841 for (i = 0; i < i3c_nxfers; i++) {
842 if (i3c_xfers[i].rnw)
843 nrxwords += DIV_ROUND_UP(i3c_xfers[i].len, 4);
844 else
845 ntxwords += DIV_ROUND_UP(i3c_xfers[i].len, 4);
846 }
847
848 if (ntxwords > master->caps.datafifodepth ||
849 nrxwords > master->caps.datafifodepth)
850 return -ENOTSUPP;
851
852 xfer = dw_i3c_master_alloc_xfer(master, i3c_nxfers);
853 if (!xfer)
854 return -ENOMEM;
855
856 for (i = 0; i < i3c_nxfers; i++) {
857 struct dw_i3c_cmd *cmd = &xfer->cmds[i];
858
859 cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(i3c_xfers[i].len) |
860 COMMAND_PORT_TRANSFER_ARG;
861
862 if (i3c_xfers[i].rnw) {
863 cmd->rx_buf = i3c_xfers[i].data.in;
864 cmd->rx_len = i3c_xfers[i].len;
865 cmd->cmd_lo = COMMAND_PORT_READ_TRANSFER |
866 COMMAND_PORT_SPEED(dev->info.max_read_ds);
867
868 } else {
869 cmd->tx_buf = i3c_xfers[i].data.out;
870 cmd->tx_len = i3c_xfers[i].len;
871 cmd->cmd_lo =
872 COMMAND_PORT_SPEED(dev->info.max_write_ds);
873 }
874
875 cmd->cmd_lo |= COMMAND_PORT_TID(i) |
876 COMMAND_PORT_DEV_INDEX(data->index) |
877 COMMAND_PORT_ROC;
878
879 if (i == (i3c_nxfers - 1))
880 cmd->cmd_lo |= COMMAND_PORT_TOC;
881 }
882
883 dw_i3c_master_enqueue_xfer(master, xfer);
884 if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT))
885 dw_i3c_master_dequeue_xfer(master, xfer);
886
887 ret = xfer->ret;
888 dw_i3c_master_free_xfer(xfer);
889
890 return ret;
891}
892
893static int dw_i3c_master_reattach_i3c_dev(struct i3c_dev_desc *dev,
894 u8 old_dyn_addr)
895{
896 struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
897 struct i3c_master_controller *m = i3c_dev_get_master(dev);
898 struct dw_i3c_master *master = to_dw_i3c_master(m);
899
900 writel(DEV_ADDR_TABLE_DYNAMIC_ADDR(dev->info.dyn_addr),
901 master->regs +
902 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
903
904 if (!old_dyn_addr)
905 return 0;
906
907 master->addrs[data->index] = dev->info.dyn_addr;
908
909 return 0;
910}
911
912static int dw_i3c_master_attach_i3c_dev(struct i3c_dev_desc *dev)
913{
914 struct i3c_master_controller *m = i3c_dev_get_master(dev);
915 struct dw_i3c_master *master = to_dw_i3c_master(m);
916 struct dw_i3c_i2c_dev_data *data;
917 int pos;
918
919 pos = dw_i3c_master_get_free_pos(master);
920 if (pos < 0)
921 return pos;
922
923 data = kzalloc(sizeof(*data), GFP_KERNEL);
924 if (!data)
925 return -ENOMEM;
926
927 data->index = pos;
928 master->addrs[pos] = dev->info.dyn_addr;
929 master->free_pos &= ~BIT(pos);
930 i3c_dev_set_master_data(dev, data);
931
932 writel(DEV_ADDR_TABLE_DYNAMIC_ADDR(dev->info.dyn_addr),
933 master->regs +
934 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
935
936 return 0;
937}
938
939static void dw_i3c_master_detach_i3c_dev(struct i3c_dev_desc *dev)
940{
941 struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
942 struct i3c_master_controller *m = i3c_dev_get_master(dev);
943 struct dw_i3c_master *master = to_dw_i3c_master(m);
944
945 writel(0,
946 master->regs +
947 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
948
949 i3c_dev_set_master_data(dev, NULL);
950 master->addrs[data->index] = 0;
951 master->free_pos |= BIT(data->index);
952 kfree(data);
953}
954
955static int dw_i3c_master_i2c_xfers(struct i2c_dev_desc *dev,
956 const struct i2c_msg *i2c_xfers,
957 int i2c_nxfers)
958{
959 struct dw_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev);
960 struct i3c_master_controller *m = i2c_dev_get_master(dev);
961 struct dw_i3c_master *master = to_dw_i3c_master(m);
962 unsigned int nrxwords = 0, ntxwords = 0;
963 struct dw_i3c_xfer *xfer;
964 int i, ret = 0;
965
966 if (!i2c_nxfers)
967 return 0;
968
969 if (i2c_nxfers > master->caps.cmdfifodepth)
970 return -ENOTSUPP;
971
972 for (i = 0; i < i2c_nxfers; i++) {
973 if (i2c_xfers[i].len > COMMAND_PORT_ARG_DATA_LEN_MAX)
974 return -ENOTSUPP;
975 }
976
977 for (i = 0; i < i2c_nxfers; i++) {
978 if (i2c_xfers[i].flags & I2C_M_RD)
979 nrxwords += DIV_ROUND_UP(i2c_xfers[i].len, 4);
980 else
981 ntxwords += DIV_ROUND_UP(i2c_xfers[i].len, 4);
982 }
983
984 if (ntxwords > master->caps.datafifodepth ||
985 nrxwords > master->caps.datafifodepth)
986 return -ENOTSUPP;
987
988 xfer = dw_i3c_master_alloc_xfer(master, i2c_nxfers);
989 if (!xfer)
990 return -ENOMEM;
991
992 for (i = 0; i < i2c_nxfers; i++) {
993 struct dw_i3c_cmd *cmd = &xfer->cmds[i];
994
995 cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(i2c_xfers[i].len) |
996 COMMAND_PORT_TRANSFER_ARG;
997
998 cmd->cmd_lo = COMMAND_PORT_TID(i) |
999 COMMAND_PORT_DEV_INDEX(data->index) |
1000 COMMAND_PORT_ROC;
1001
1002 if (i2c_xfers[i].flags & I2C_M_RD) {
1003 cmd->cmd_lo |= COMMAND_PORT_READ_TRANSFER;
1004 cmd->rx_buf = i2c_xfers[i].buf;
1005 cmd->rx_len = i2c_xfers[i].len;
1006 } else {
1007 cmd->tx_buf = i2c_xfers[i].buf;
1008 cmd->tx_len = i2c_xfers[i].len;
1009 }
1010
1011 if (i == (i2c_nxfers - 1))
1012 cmd->cmd_lo |= COMMAND_PORT_TOC;
1013 }
1014
1015 dw_i3c_master_enqueue_xfer(master, xfer);
1016 if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT))
1017 dw_i3c_master_dequeue_xfer(master, xfer);
1018
1019 ret = xfer->ret;
1020 dw_i3c_master_free_xfer(xfer);
1021
1022 return ret;
1023}
1024
1025static int dw_i3c_master_attach_i2c_dev(struct i2c_dev_desc *dev)
1026{
1027 struct i3c_master_controller *m = i2c_dev_get_master(dev);
1028 struct dw_i3c_master *master = to_dw_i3c_master(m);
1029 struct dw_i3c_i2c_dev_data *data;
1030 int pos;
1031
1032 pos = dw_i3c_master_get_free_pos(master);
1033 if (pos < 0)
1034 return pos;
1035
1036 data = kzalloc(sizeof(*data), GFP_KERNEL);
1037 if (!data)
1038 return -ENOMEM;
1039
1040 data->index = pos;
1041 master->addrs[pos] = dev->boardinfo->base.addr;
1042 master->free_pos &= ~BIT(pos);
1043 i2c_dev_set_master_data(dev, data);
1044
1045 writel(DEV_ADDR_TABLE_LEGACY_I2C_DEV |
1046 DEV_ADDR_TABLE_STATIC_ADDR(dev->boardinfo->base.addr),
1047 master->regs +
1048 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
1049
1050 return 0;
1051}
1052
1053static void dw_i3c_master_detach_i2c_dev(struct i2c_dev_desc *dev)
1054{
1055 struct dw_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev);
1056 struct i3c_master_controller *m = i2c_dev_get_master(dev);
1057 struct dw_i3c_master *master = to_dw_i3c_master(m);
1058
1059 writel(0,
1060 master->regs +
1061 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
1062
1063 i2c_dev_set_master_data(dev, NULL);
1064 master->addrs[data->index] = 0;
1065 master->free_pos |= BIT(data->index);
1066 kfree(data);
1067}
1068
1069static u32 dw_i3c_master_i2c_funcs(struct i3c_master_controller *m)
1070{
1071 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
1072}
1073
1074static irqreturn_t dw_i3c_master_irq_handler(int irq, void *dev_id)
1075{
1076 struct dw_i3c_master *master = dev_id;
1077 u32 status;
1078
1079 status = readl(master->regs + INTR_STATUS);
1080
1081 if (!(status & readl(master->regs + INTR_STATUS_EN))) {
1082 writel(INTR_ALL, master->regs + INTR_STATUS);
1083 return IRQ_NONE;
1084 }
1085
1086 spin_lock(&master->xferqueue.lock);
1087 dw_i3c_master_end_xfer_locked(master, status);
1088 if (status & INTR_TRANSFER_ERR_STAT)
1089 writel(INTR_TRANSFER_ERR_STAT, master->regs + INTR_STATUS);
1090 spin_unlock(&master->xferqueue.lock);
1091
1092 return IRQ_HANDLED;
1093}
1094
1095static const struct i3c_master_controller_ops dw_mipi_i3c_ops = {
1096 .bus_init = dw_i3c_master_bus_init,
1097 .bus_cleanup = dw_i3c_master_bus_cleanup,
1098 .attach_i3c_dev = dw_i3c_master_attach_i3c_dev,
1099 .reattach_i3c_dev = dw_i3c_master_reattach_i3c_dev,
1100 .detach_i3c_dev = dw_i3c_master_detach_i3c_dev,
1101 .do_daa = dw_i3c_master_daa,
1102 .supports_ccc_cmd = dw_i3c_master_supports_ccc_cmd,
1103 .send_ccc_cmd = dw_i3c_master_send_ccc_cmd,
1104 .priv_xfers = dw_i3c_master_priv_xfers,
1105 .attach_i2c_dev = dw_i3c_master_attach_i2c_dev,
1106 .detach_i2c_dev = dw_i3c_master_detach_i2c_dev,
1107 .i2c_xfers = dw_i3c_master_i2c_xfers,
1108 .i2c_funcs = dw_i3c_master_i2c_funcs,
1109};
1110
1111static int dw_i3c_probe(struct platform_device *pdev)
1112{
1113 struct dw_i3c_master *master;
1114 struct resource *res;
1115 int ret, irq;
1116
1117 master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL);
1118 if (!master)
1119 return -ENOMEM;
1120
1121 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1122 master->regs = devm_ioremap_resource(&pdev->dev, res);
1123 if (IS_ERR(master->regs))
1124 return PTR_ERR(master->regs);
1125
1126 master->core_clk = devm_clk_get(&pdev->dev, NULL);
1127 if (IS_ERR(master->core_clk))
1128 return PTR_ERR(master->core_clk);
1129
1130 master->core_rst = devm_reset_control_get_optional_exclusive(&pdev->dev,
1131 "core_rst");
1132 if (IS_ERR(master->core_rst))
1133 return PTR_ERR(master->core_rst);
1134
1135 ret = clk_prepare_enable(master->core_clk);
1136 if (ret)
1137 goto err_disable_core_clk;
1138
1139 reset_control_deassert(master->core_rst);
1140
1141 spin_lock_init(&master->xferqueue.lock);
1142 INIT_LIST_HEAD(&master->xferqueue.list);
1143
1144 writel(INTR_ALL, master->regs + INTR_STATUS);
1145 irq = platform_get_irq(pdev, 0);
1146 ret = devm_request_irq(&pdev->dev, irq,
1147 dw_i3c_master_irq_handler, 0,
1148 dev_name(&pdev->dev), master);
1149 if (ret)
1150 goto err_assert_rst;
1151
1152 platform_set_drvdata(pdev, master);
1153
1154 /* Information regarding the FIFOs/QUEUEs depth */
1155 ret = readl(master->regs + QUEUE_STATUS_LEVEL);
1156 master->caps.cmdfifodepth = QUEUE_STATUS_LEVEL_CMD(ret);
1157
1158 ret = readl(master->regs + DATA_BUFFER_STATUS_LEVEL);
1159 master->caps.datafifodepth = DATA_BUFFER_STATUS_LEVEL_TX(ret);
1160
1161 ret = readl(master->regs + DEVICE_ADDR_TABLE_POINTER);
1162 master->datstartaddr = ret;
1163 master->maxdevs = ret >> 16;
1164 master->free_pos = GENMASK(master->maxdevs - 1, 0);
1165
1166 ret = i3c_master_register(&master->base, &pdev->dev,
1167 &dw_mipi_i3c_ops, false);
1168 if (ret)
1169 goto err_assert_rst;
1170
1171 return 0;
1172
1173err_assert_rst:
1174 reset_control_assert(master->core_rst);
1175
1176err_disable_core_clk:
1177 clk_disable_unprepare(master->core_clk);
1178
1179 return ret;
1180}
1181
1182static int dw_i3c_remove(struct platform_device *pdev)
1183{
1184 struct dw_i3c_master *master = platform_get_drvdata(pdev);
1185 int ret;
1186
1187 ret = i3c_master_unregister(&master->base);
1188 if (ret)
1189 return ret;
1190
1191 reset_control_assert(master->core_rst);
1192
1193 clk_disable_unprepare(master->core_clk);
1194
1195 return 0;
1196}
1197
1198static const struct of_device_id dw_i3c_master_of_match[] = {
1199 { .compatible = "snps,dw-i3c-master-1.00a", },
1200 {},
1201};
1202MODULE_DEVICE_TABLE(of, dw_i3c_master_of_match);
1203
1204static struct platform_driver dw_i3c_driver = {
1205 .probe = dw_i3c_probe,
1206 .remove = dw_i3c_remove,
1207 .driver = {
1208 .name = "dw-i3c-master",
1209 .of_match_table = of_match_ptr(dw_i3c_master_of_match),
1210 },
1211};
1212module_platform_driver(dw_i3c_driver);
1213
1214MODULE_AUTHOR("Vitor Soares <vitor.soares@synopsys.com>");
1215MODULE_DESCRIPTION("DesignWare MIPI I3C driver");
1216MODULE_LICENSE("GPL v2");
diff --git a/drivers/i3c/master/i3c-master-cdns.c b/drivers/i3c/master/i3c-master-cdns.c
new file mode 100644
index 000000000000..bbd79b8b1a80
--- /dev/null
+++ b/drivers/i3c/master/i3c-master-cdns.c
@@ -0,0 +1,1666 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2018 Cadence Design Systems Inc.
4 *
5 * Author: Boris Brezillon <boris.brezillon@bootlin.com>
6 */
7
8#include <linux/bitops.h>
9#include <linux/clk.h>
10#include <linux/err.h>
11#include <linux/errno.h>
12#include <linux/i3c/master.h>
13#include <linux/interrupt.h>
14#include <linux/io.h>
15#include <linux/iopoll.h>
16#include <linux/ioport.h>
17#include <linux/kernel.h>
18#include <linux/list.h>
19#include <linux/module.h>
20#include <linux/of.h>
21#include <linux/platform_device.h>
22#include <linux/slab.h>
23#include <linux/spinlock.h>
24#include <linux/workqueue.h>
25
26#define DEV_ID 0x0
27#define DEV_ID_I3C_MASTER 0x5034
28
29#define CONF_STATUS0 0x4
30#define CONF_STATUS0_CMDR_DEPTH(x) (4 << (((x) & GENMASK(31, 29)) >> 29))
31#define CONF_STATUS0_ECC_CHK BIT(28)
32#define CONF_STATUS0_INTEG_CHK BIT(27)
33#define CONF_STATUS0_CSR_DAP_CHK BIT(26)
34#define CONF_STATUS0_TRANS_TOUT_CHK BIT(25)
35#define CONF_STATUS0_PROT_FAULTS_CHK BIT(24)
36#define CONF_STATUS0_GPO_NUM(x) (((x) & GENMASK(23, 16)) >> 16)
37#define CONF_STATUS0_GPI_NUM(x) (((x) & GENMASK(15, 8)) >> 8)
38#define CONF_STATUS0_IBIR_DEPTH(x) (4 << (((x) & GENMASK(7, 6)) >> 7))
39#define CONF_STATUS0_SUPPORTS_DDR BIT(5)
40#define CONF_STATUS0_SEC_MASTER BIT(4)
41#define CONF_STATUS0_DEVS_NUM(x) ((x) & GENMASK(3, 0))
42
43#define CONF_STATUS1 0x8
44#define CONF_STATUS1_IBI_HW_RES(x) ((((x) & GENMASK(31, 28)) >> 28) + 1)
45#define CONF_STATUS1_CMD_DEPTH(x) (4 << (((x) & GENMASK(27, 26)) >> 26))
46#define CONF_STATUS1_SLVDDR_RX_DEPTH(x) (8 << (((x) & GENMASK(25, 21)) >> 21))
47#define CONF_STATUS1_SLVDDR_TX_DEPTH(x) (8 << (((x) & GENMASK(20, 16)) >> 16))
48#define CONF_STATUS1_IBI_DEPTH(x) (2 << (((x) & GENMASK(12, 10)) >> 10))
49#define CONF_STATUS1_RX_DEPTH(x) (8 << (((x) & GENMASK(9, 5)) >> 5))
50#define CONF_STATUS1_TX_DEPTH(x) (8 << ((x) & GENMASK(4, 0)))
51
52#define REV_ID 0xc
53#define REV_ID_VID(id) (((id) & GENMASK(31, 20)) >> 20)
54#define REV_ID_PID(id) (((id) & GENMASK(19, 8)) >> 8)
55#define REV_ID_REV_MAJOR(id) (((id) & GENMASK(7, 4)) >> 4)
56#define REV_ID_REV_MINOR(id) ((id) & GENMASK(3, 0))
57
58#define CTRL 0x10
59#define CTRL_DEV_EN BIT(31)
60#define CTRL_HALT_EN BIT(30)
61#define CTRL_MCS BIT(29)
62#define CTRL_MCS_EN BIT(28)
63#define CTRL_HJ_DISEC BIT(8)
64#define CTRL_MST_ACK BIT(7)
65#define CTRL_HJ_ACK BIT(6)
66#define CTRL_HJ_INIT BIT(5)
67#define CTRL_MST_INIT BIT(4)
68#define CTRL_AHDR_OPT BIT(3)
69#define CTRL_PURE_BUS_MODE 0
70#define CTRL_MIXED_FAST_BUS_MODE 2
71#define CTRL_MIXED_SLOW_BUS_MODE 3
72#define CTRL_BUS_MODE_MASK GENMASK(1, 0)
73
74#define PRESCL_CTRL0 0x14
75#define PRESCL_CTRL0_I2C(x) ((x) << 16)
76#define PRESCL_CTRL0_I3C(x) (x)
77#define PRESCL_CTRL0_MAX GENMASK(9, 0)
78
79#define PRESCL_CTRL1 0x18
80#define PRESCL_CTRL1_PP_LOW_MASK GENMASK(15, 8)
81#define PRESCL_CTRL1_PP_LOW(x) ((x) << 8)
82#define PRESCL_CTRL1_OD_LOW_MASK GENMASK(7, 0)
83#define PRESCL_CTRL1_OD_LOW(x) (x)
84
85#define MST_IER 0x20
86#define MST_IDR 0x24
87#define MST_IMR 0x28
88#define MST_ICR 0x2c
89#define MST_ISR 0x30
90#define MST_INT_HALTED BIT(18)
91#define MST_INT_MR_DONE BIT(17)
92#define MST_INT_IMM_COMP BIT(16)
93#define MST_INT_TX_THR BIT(15)
94#define MST_INT_TX_OVF BIT(14)
95#define MST_INT_IBID_THR BIT(12)
96#define MST_INT_IBID_UNF BIT(11)
97#define MST_INT_IBIR_THR BIT(10)
98#define MST_INT_IBIR_UNF BIT(9)
99#define MST_INT_IBIR_OVF BIT(8)
100#define MST_INT_RX_THR BIT(7)
101#define MST_INT_RX_UNF BIT(6)
102#define MST_INT_CMDD_EMP BIT(5)
103#define MST_INT_CMDD_THR BIT(4)
104#define MST_INT_CMDD_OVF BIT(3)
105#define MST_INT_CMDR_THR BIT(2)
106#define MST_INT_CMDR_UNF BIT(1)
107#define MST_INT_CMDR_OVF BIT(0)
108
109#define MST_STATUS0 0x34
110#define MST_STATUS0_IDLE BIT(18)
111#define MST_STATUS0_HALTED BIT(17)
112#define MST_STATUS0_MASTER_MODE BIT(16)
113#define MST_STATUS0_TX_FULL BIT(13)
114#define MST_STATUS0_IBID_FULL BIT(12)
115#define MST_STATUS0_IBIR_FULL BIT(11)
116#define MST_STATUS0_RX_FULL BIT(10)
117#define MST_STATUS0_CMDD_FULL BIT(9)
118#define MST_STATUS0_CMDR_FULL BIT(8)
119#define MST_STATUS0_TX_EMP BIT(5)
120#define MST_STATUS0_IBID_EMP BIT(4)
121#define MST_STATUS0_IBIR_EMP BIT(3)
122#define MST_STATUS0_RX_EMP BIT(2)
123#define MST_STATUS0_CMDD_EMP BIT(1)
124#define MST_STATUS0_CMDR_EMP BIT(0)
125
126#define CMDR 0x38
127#define CMDR_NO_ERROR 0
128#define CMDR_DDR_PREAMBLE_ERROR 1
129#define CMDR_DDR_PARITY_ERROR 2
130#define CMDR_DDR_RX_FIFO_OVF 3
131#define CMDR_DDR_TX_FIFO_UNF 4
132#define CMDR_M0_ERROR 5
133#define CMDR_M1_ERROR 6
134#define CMDR_M2_ERROR 7
135#define CMDR_MST_ABORT 8
136#define CMDR_NACK_RESP 9
137#define CMDR_INVALID_DA 10
138#define CMDR_DDR_DROPPED 11
139#define CMDR_ERROR(x) (((x) & GENMASK(27, 24)) >> 24)
140#define CMDR_XFER_BYTES(x) (((x) & GENMASK(19, 8)) >> 8)
141#define CMDR_CMDID_HJACK_DISEC 0xfe
142#define CMDR_CMDID_HJACK_ENTDAA 0xff
143#define CMDR_CMDID(x) ((x) & GENMASK(7, 0))
144
145#define IBIR 0x3c
146#define IBIR_ACKED BIT(12)
147#define IBIR_SLVID(x) (((x) & GENMASK(11, 8)) >> 8)
148#define IBIR_ERROR BIT(7)
149#define IBIR_XFER_BYTES(x) (((x) & GENMASK(6, 2)) >> 2)
150#define IBIR_TYPE_IBI 0
151#define IBIR_TYPE_HJ 1
152#define IBIR_TYPE_MR 2
153#define IBIR_TYPE(x) ((x) & GENMASK(1, 0))
154
155#define SLV_IER 0x40
156#define SLV_IDR 0x44
157#define SLV_IMR 0x48
158#define SLV_ICR 0x4c
159#define SLV_ISR 0x50
160#define SLV_INT_TM BIT(20)
161#define SLV_INT_ERROR BIT(19)
162#define SLV_INT_EVENT_UP BIT(18)
163#define SLV_INT_HJ_DONE BIT(17)
164#define SLV_INT_MR_DONE BIT(16)
165#define SLV_INT_DA_UPD BIT(15)
166#define SLV_INT_SDR_FAIL BIT(14)
167#define SLV_INT_DDR_FAIL BIT(13)
168#define SLV_INT_M_RD_ABORT BIT(12)
169#define SLV_INT_DDR_RX_THR BIT(11)
170#define SLV_INT_DDR_TX_THR BIT(10)
171#define SLV_INT_SDR_RX_THR BIT(9)
172#define SLV_INT_SDR_TX_THR BIT(8)
173#define SLV_INT_DDR_RX_UNF BIT(7)
174#define SLV_INT_DDR_TX_OVF BIT(6)
175#define SLV_INT_SDR_RX_UNF BIT(5)
176#define SLV_INT_SDR_TX_OVF BIT(4)
177#define SLV_INT_DDR_RD_COMP BIT(3)
178#define SLV_INT_DDR_WR_COMP BIT(2)
179#define SLV_INT_SDR_RD_COMP BIT(1)
180#define SLV_INT_SDR_WR_COMP BIT(0)
181
182#define SLV_STATUS0 0x54
183#define SLV_STATUS0_REG_ADDR(s) (((s) & GENMASK(23, 16)) >> 16)
184#define SLV_STATUS0_XFRD_BYTES(s) ((s) & GENMASK(15, 0))
185
186#define SLV_STATUS1 0x58
187#define SLV_STATUS1_AS(s) (((s) & GENMASK(21, 20)) >> 20)
188#define SLV_STATUS1_VEN_TM BIT(19)
189#define SLV_STATUS1_HJ_DIS BIT(18)
190#define SLV_STATUS1_MR_DIS BIT(17)
191#define SLV_STATUS1_PROT_ERR BIT(16)
192#define SLV_STATUS1_DA(x) (((s) & GENMASK(15, 9)) >> 9)
193#define SLV_STATUS1_HAS_DA BIT(8)
194#define SLV_STATUS1_DDR_RX_FULL BIT(7)
195#define SLV_STATUS1_DDR_TX_FULL BIT(6)
196#define SLV_STATUS1_DDR_RX_EMPTY BIT(5)
197#define SLV_STATUS1_DDR_TX_EMPTY BIT(4)
198#define SLV_STATUS1_SDR_RX_FULL BIT(3)
199#define SLV_STATUS1_SDR_TX_FULL BIT(2)
200#define SLV_STATUS1_SDR_RX_EMPTY BIT(1)
201#define SLV_STATUS1_SDR_TX_EMPTY BIT(0)
202
203#define CMD0_FIFO 0x60
204#define CMD0_FIFO_IS_DDR BIT(31)
205#define CMD0_FIFO_IS_CCC BIT(30)
206#define CMD0_FIFO_BCH BIT(29)
207#define XMIT_BURST_STATIC_SUBADDR 0
208#define XMIT_SINGLE_INC_SUBADDR 1
209#define XMIT_SINGLE_STATIC_SUBADDR 2
210#define XMIT_BURST_WITHOUT_SUBADDR 3
211#define CMD0_FIFO_PRIV_XMIT_MODE(m) ((m) << 27)
212#define CMD0_FIFO_SBCA BIT(26)
213#define CMD0_FIFO_RSBC BIT(25)
214#define CMD0_FIFO_IS_10B BIT(24)
215#define CMD0_FIFO_PL_LEN(l) ((l) << 12)
216#define CMD0_FIFO_PL_LEN_MAX 4095
217#define CMD0_FIFO_DEV_ADDR(a) ((a) << 1)
218#define CMD0_FIFO_RNW BIT(0)
219
220#define CMD1_FIFO 0x64
221#define CMD1_FIFO_CMDID(id) ((id) << 24)
222#define CMD1_FIFO_CSRADDR(a) (a)
223#define CMD1_FIFO_CCC(id) (id)
224
225#define TX_FIFO 0x68
226
227#define IMD_CMD0 0x70
228#define IMD_CMD0_PL_LEN(l) ((l) << 12)
229#define IMD_CMD0_DEV_ADDR(a) ((a) << 1)
230#define IMD_CMD0_RNW BIT(0)
231
232#define IMD_CMD1 0x74
233#define IMD_CMD1_CCC(id) (id)
234
235#define IMD_DATA 0x78
236#define RX_FIFO 0x80
237#define IBI_DATA_FIFO 0x84
238#define SLV_DDR_TX_FIFO 0x88
239#define SLV_DDR_RX_FIFO 0x8c
240
241#define CMD_IBI_THR_CTRL 0x90
242#define IBIR_THR(t) ((t) << 24)
243#define CMDR_THR(t) ((t) << 16)
244#define IBI_THR(t) ((t) << 8)
245#define CMD_THR(t) (t)
246
247#define TX_RX_THR_CTRL 0x94
248#define RX_THR(t) ((t) << 16)
249#define TX_THR(t) (t)
250
251#define SLV_DDR_TX_RX_THR_CTRL 0x98
252#define SLV_DDR_RX_THR(t) ((t) << 16)
253#define SLV_DDR_TX_THR(t) (t)
254
255#define FLUSH_CTRL 0x9c
256#define FLUSH_IBI_RESP BIT(23)
257#define FLUSH_CMD_RESP BIT(22)
258#define FLUSH_SLV_DDR_RX_FIFO BIT(22)
259#define FLUSH_SLV_DDR_TX_FIFO BIT(21)
260#define FLUSH_IMM_FIFO BIT(20)
261#define FLUSH_IBI_FIFO BIT(19)
262#define FLUSH_RX_FIFO BIT(18)
263#define FLUSH_TX_FIFO BIT(17)
264#define FLUSH_CMD_FIFO BIT(16)
265
266#define TTO_PRESCL_CTRL0 0xb0
267#define TTO_PRESCL_CTRL0_DIVB(x) ((x) << 16)
268#define TTO_PRESCL_CTRL0_DIVA(x) (x)
269
270#define TTO_PRESCL_CTRL1 0xb4
271#define TTO_PRESCL_CTRL1_DIVB(x) ((x) << 16)
272#define TTO_PRESCL_CTRL1_DIVA(x) (x)
273
274#define DEVS_CTRL 0xb8
275#define DEVS_CTRL_DEV_CLR_SHIFT 16
276#define DEVS_CTRL_DEV_CLR_ALL GENMASK(31, 16)
277#define DEVS_CTRL_DEV_CLR(dev) BIT(16 + (dev))
278#define DEVS_CTRL_DEV_ACTIVE(dev) BIT(dev)
279#define DEVS_CTRL_DEVS_ACTIVE_MASK GENMASK(15, 0)
280#define MAX_DEVS 16
281
282#define DEV_ID_RR0(d) (0xc0 + ((d) * 0x10))
283#define DEV_ID_RR0_LVR_EXT_ADDR BIT(11)
284#define DEV_ID_RR0_HDR_CAP BIT(10)
285#define DEV_ID_RR0_IS_I3C BIT(9)
286#define DEV_ID_RR0_DEV_ADDR_MASK (GENMASK(6, 0) | GENMASK(15, 13))
287#define DEV_ID_RR0_SET_DEV_ADDR(a) (((a) & GENMASK(6, 0)) | \
288 (((a) & GENMASK(9, 7)) << 6))
289#define DEV_ID_RR0_GET_DEV_ADDR(x) ((((x) >> 1) & GENMASK(6, 0)) | \
290 (((x) >> 6) & GENMASK(9, 7)))
291
292#define DEV_ID_RR1(d) (0xc4 + ((d) * 0x10))
293#define DEV_ID_RR1_PID_MSB(pid) (pid)
294
295#define DEV_ID_RR2(d) (0xc8 + ((d) * 0x10))
296#define DEV_ID_RR2_PID_LSB(pid) ((pid) << 16)
297#define DEV_ID_RR2_BCR(bcr) ((bcr) << 8)
298#define DEV_ID_RR2_DCR(dcr) (dcr)
299#define DEV_ID_RR2_LVR(lvr) (lvr)
300
301#define SIR_MAP(x) (0x180 + ((x) * 4))
302#define SIR_MAP_DEV_REG(d) SIR_MAP((d) / 2)
303#define SIR_MAP_DEV_SHIFT(d, fs) ((fs) + (((d) % 2) ? 16 : 0))
304#define SIR_MAP_DEV_CONF_MASK(d) (GENMASK(15, 0) << (((d) % 2) ? 16 : 0))
305#define SIR_MAP_DEV_CONF(d, c) ((c) << (((d) % 2) ? 16 : 0))
306#define DEV_ROLE_SLAVE 0
307#define DEV_ROLE_MASTER 1
308#define SIR_MAP_DEV_ROLE(role) ((role) << 14)
309#define SIR_MAP_DEV_SLOW BIT(13)
310#define SIR_MAP_DEV_PL(l) ((l) << 8)
311#define SIR_MAP_PL_MAX GENMASK(4, 0)
312#define SIR_MAP_DEV_DA(a) ((a) << 1)
313#define SIR_MAP_DEV_ACK BIT(0)
314
315#define GPIR_WORD(x) (0x200 + ((x) * 4))
316#define GPI_REG(val, id) \
317 (((val) >> (((id) % 4) * 8)) & GENMASK(7, 0))
318
319#define GPOR_WORD(x) (0x220 + ((x) * 4))
320#define GPO_REG(val, id) \
321 (((val) >> (((id) % 4) * 8)) & GENMASK(7, 0))
322
323#define ASF_INT_STATUS 0x300
324#define ASF_INT_RAW_STATUS 0x304
325#define ASF_INT_MASK 0x308
326#define ASF_INT_TEST 0x30c
327#define ASF_INT_FATAL_SELECT 0x310
328#define ASF_INTEGRITY_ERR BIT(6)
329#define ASF_PROTOCOL_ERR BIT(5)
330#define ASF_TRANS_TIMEOUT_ERR BIT(4)
331#define ASF_CSR_ERR BIT(3)
332#define ASF_DAP_ERR BIT(2)
333#define ASF_SRAM_UNCORR_ERR BIT(1)
334#define ASF_SRAM_CORR_ERR BIT(0)
335
336#define ASF_SRAM_CORR_FAULT_STATUS 0x320
337#define ASF_SRAM_UNCORR_FAULT_STATUS 0x324
338#define ASF_SRAM_CORR_FAULT_INSTANCE(x) ((x) >> 24)
339#define ASF_SRAM_CORR_FAULT_ADDR(x) ((x) & GENMASK(23, 0))
340
341#define ASF_SRAM_FAULT_STATS 0x328
342#define ASF_SRAM_FAULT_UNCORR_STATS(x) ((x) >> 16)
343#define ASF_SRAM_FAULT_CORR_STATS(x) ((x) & GENMASK(15, 0))
344
345#define ASF_TRANS_TOUT_CTRL 0x330
346#define ASF_TRANS_TOUT_EN BIT(31)
347#define ASF_TRANS_TOUT_VAL(x) (x)
348
349#define ASF_TRANS_TOUT_FAULT_MASK 0x334
350#define ASF_TRANS_TOUT_FAULT_STATUS 0x338
351#define ASF_TRANS_TOUT_FAULT_APB BIT(3)
352#define ASF_TRANS_TOUT_FAULT_SCL_LOW BIT(2)
353#define ASF_TRANS_TOUT_FAULT_SCL_HIGH BIT(1)
354#define ASF_TRANS_TOUT_FAULT_FSCL_HIGH BIT(0)
355
356#define ASF_PROTO_FAULT_MASK 0x340
357#define ASF_PROTO_FAULT_STATUS 0x344
358#define ASF_PROTO_FAULT_SLVSDR_RD_ABORT BIT(31)
359#define ASF_PROTO_FAULT_SLVDDR_FAIL BIT(30)
360#define ASF_PROTO_FAULT_S(x) BIT(16 + (x))
361#define ASF_PROTO_FAULT_MSTSDR_RD_ABORT BIT(15)
362#define ASF_PROTO_FAULT_MSTDDR_FAIL BIT(14)
363#define ASF_PROTO_FAULT_M(x) BIT(x)
364
365struct cdns_i3c_master_caps {
366 u32 cmdfifodepth;
367 u32 cmdrfifodepth;
368 u32 txfifodepth;
369 u32 rxfifodepth;
370 u32 ibirfifodepth;
371};
372
373struct cdns_i3c_cmd {
374 u32 cmd0;
375 u32 cmd1;
376 u32 tx_len;
377 const void *tx_buf;
378 u32 rx_len;
379 void *rx_buf;
380 u32 error;
381};
382
383struct cdns_i3c_xfer {
384 struct list_head node;
385 struct completion comp;
386 int ret;
387 unsigned int ncmds;
388 struct cdns_i3c_cmd cmds[0];
389};
390
391struct cdns_i3c_master {
392 struct work_struct hj_work;
393 struct i3c_master_controller base;
394 u32 free_rr_slots;
395 unsigned int maxdevs;
396 struct {
397 unsigned int num_slots;
398 struct i3c_dev_desc **slots;
399 spinlock_t lock;
400 } ibi;
401 struct {
402 struct list_head list;
403 struct cdns_i3c_xfer *cur;
404 spinlock_t lock;
405 } xferqueue;
406 void __iomem *regs;
407 struct clk *sysclk;
408 struct clk *pclk;
409 struct cdns_i3c_master_caps caps;
410 unsigned long i3c_scl_lim;
411};
412
413static inline struct cdns_i3c_master *
414to_cdns_i3c_master(struct i3c_master_controller *master)
415{
416 return container_of(master, struct cdns_i3c_master, base);
417}
418
419static void cdns_i3c_master_wr_to_tx_fifo(struct cdns_i3c_master *master,
420 const u8 *bytes, int nbytes)
421{
422 writesl(master->regs + TX_FIFO, bytes, nbytes / 4);
423 if (nbytes & 3) {
424 u32 tmp = 0;
425
426 memcpy(&tmp, bytes + (nbytes & ~3), nbytes & 3);
427 writesl(master->regs + TX_FIFO, &tmp, 1);
428 }
429}
430
431static void cdns_i3c_master_rd_from_rx_fifo(struct cdns_i3c_master *master,
432 u8 *bytes, int nbytes)
433{
434 readsl(master->regs + RX_FIFO, bytes, nbytes / 4);
435 if (nbytes & 3) {
436 u32 tmp;
437
438 readsl(master->regs + RX_FIFO, &tmp, 1);
439 memcpy(bytes + (nbytes & ~3), &tmp, nbytes & 3);
440 }
441}
442
443static bool cdns_i3c_master_supports_ccc_cmd(struct i3c_master_controller *m,
444 const struct i3c_ccc_cmd *cmd)
445{
446 if (cmd->ndests > 1)
447 return false;
448
449 switch (cmd->id) {
450 case I3C_CCC_ENEC(true):
451 case I3C_CCC_ENEC(false):
452 case I3C_CCC_DISEC(true):
453 case I3C_CCC_DISEC(false):
454 case I3C_CCC_ENTAS(0, true):
455 case I3C_CCC_ENTAS(0, false):
456 case I3C_CCC_RSTDAA(true):
457 case I3C_CCC_RSTDAA(false):
458 case I3C_CCC_ENTDAA:
459 case I3C_CCC_SETMWL(true):
460 case I3C_CCC_SETMWL(false):
461 case I3C_CCC_SETMRL(true):
462 case I3C_CCC_SETMRL(false):
463 case I3C_CCC_DEFSLVS:
464 case I3C_CCC_ENTHDR(0):
465 case I3C_CCC_SETDASA:
466 case I3C_CCC_SETNEWDA:
467 case I3C_CCC_GETMWL:
468 case I3C_CCC_GETMRL:
469 case I3C_CCC_GETPID:
470 case I3C_CCC_GETBCR:
471 case I3C_CCC_GETDCR:
472 case I3C_CCC_GETSTATUS:
473 case I3C_CCC_GETACCMST:
474 case I3C_CCC_GETMXDS:
475 case I3C_CCC_GETHDRCAP:
476 return true;
477 default:
478 break;
479 }
480
481 return false;
482}
483
484static int cdns_i3c_master_disable(struct cdns_i3c_master *master)
485{
486 u32 status;
487
488 writel(readl(master->regs + CTRL) & ~CTRL_DEV_EN, master->regs + CTRL);
489
490 return readl_poll_timeout(master->regs + MST_STATUS0, status,
491 status & MST_STATUS0_IDLE, 10, 1000000);
492}
493
494static void cdns_i3c_master_enable(struct cdns_i3c_master *master)
495{
496 writel(readl(master->regs + CTRL) | CTRL_DEV_EN, master->regs + CTRL);
497}
498
499static struct cdns_i3c_xfer *
500cdns_i3c_master_alloc_xfer(struct cdns_i3c_master *master, unsigned int ncmds)
501{
502 struct cdns_i3c_xfer *xfer;
503
504 xfer = kzalloc(struct_size(xfer, cmds, ncmds), GFP_KERNEL);
505 if (!xfer)
506 return NULL;
507
508 INIT_LIST_HEAD(&xfer->node);
509 xfer->ncmds = ncmds;
510 xfer->ret = -ETIMEDOUT;
511
512 return xfer;
513}
514
515static void cdns_i3c_master_free_xfer(struct cdns_i3c_xfer *xfer)
516{
517 kfree(xfer);
518}
519
520static void cdns_i3c_master_start_xfer_locked(struct cdns_i3c_master *master)
521{
522 struct cdns_i3c_xfer *xfer = master->xferqueue.cur;
523 unsigned int i;
524
525 if (!xfer)
526 return;
527
528 writel(MST_INT_CMDD_EMP, master->regs + MST_ICR);
529 for (i = 0; i < xfer->ncmds; i++) {
530 struct cdns_i3c_cmd *cmd = &xfer->cmds[i];
531
532 cdns_i3c_master_wr_to_tx_fifo(master, cmd->tx_buf,
533 cmd->tx_len);
534 }
535
536 for (i = 0; i < xfer->ncmds; i++) {
537 struct cdns_i3c_cmd *cmd = &xfer->cmds[i];
538
539 writel(cmd->cmd1 | CMD1_FIFO_CMDID(i),
540 master->regs + CMD1_FIFO);
541 writel(cmd->cmd0, master->regs + CMD0_FIFO);
542 }
543
544 writel(readl(master->regs + CTRL) | CTRL_MCS,
545 master->regs + CTRL);
546 writel(MST_INT_CMDD_EMP, master->regs + MST_IER);
547}
548
549static void cdns_i3c_master_end_xfer_locked(struct cdns_i3c_master *master,
550 u32 isr)
551{
552 struct cdns_i3c_xfer *xfer = master->xferqueue.cur;
553 int i, ret = 0;
554 u32 status0;
555
556 if (!xfer)
557 return;
558
559 if (!(isr & MST_INT_CMDD_EMP))
560 return;
561
562 writel(MST_INT_CMDD_EMP, master->regs + MST_IDR);
563
564 for (status0 = readl(master->regs + MST_STATUS0);
565 !(status0 & MST_STATUS0_CMDR_EMP);
566 status0 = readl(master->regs + MST_STATUS0)) {
567 struct cdns_i3c_cmd *cmd;
568 u32 cmdr, rx_len, id;
569
570 cmdr = readl(master->regs + CMDR);
571 id = CMDR_CMDID(cmdr);
572 if (id == CMDR_CMDID_HJACK_DISEC ||
573 id == CMDR_CMDID_HJACK_ENTDAA ||
574 WARN_ON(id >= xfer->ncmds))
575 continue;
576
577 cmd = &xfer->cmds[CMDR_CMDID(cmdr)];
578 rx_len = min_t(u32, CMDR_XFER_BYTES(cmdr), cmd->rx_len);
579 cdns_i3c_master_rd_from_rx_fifo(master, cmd->rx_buf, rx_len);
580 cmd->error = CMDR_ERROR(cmdr);
581 }
582
583 for (i = 0; i < xfer->ncmds; i++) {
584 switch (xfer->cmds[i].error) {
585 case CMDR_NO_ERROR:
586 break;
587
588 case CMDR_DDR_PREAMBLE_ERROR:
589 case CMDR_DDR_PARITY_ERROR:
590 case CMDR_M0_ERROR:
591 case CMDR_M1_ERROR:
592 case CMDR_M2_ERROR:
593 case CMDR_MST_ABORT:
594 case CMDR_NACK_RESP:
595 case CMDR_DDR_DROPPED:
596 ret = -EIO;
597 break;
598
599 case CMDR_DDR_RX_FIFO_OVF:
600 case CMDR_DDR_TX_FIFO_UNF:
601 ret = -ENOSPC;
602 break;
603
604 case CMDR_INVALID_DA:
605 default:
606 ret = -EINVAL;
607 break;
608 }
609 }
610
611 xfer->ret = ret;
612 complete(&xfer->comp);
613
614 xfer = list_first_entry_or_null(&master->xferqueue.list,
615 struct cdns_i3c_xfer, node);
616 if (xfer)
617 list_del_init(&xfer->node);
618
619 master->xferqueue.cur = xfer;
620 cdns_i3c_master_start_xfer_locked(master);
621}
622
623static void cdns_i3c_master_queue_xfer(struct cdns_i3c_master *master,
624 struct cdns_i3c_xfer *xfer)
625{
626 unsigned long flags;
627
628 init_completion(&xfer->comp);
629 spin_lock_irqsave(&master->xferqueue.lock, flags);
630 if (master->xferqueue.cur) {
631 list_add_tail(&xfer->node, &master->xferqueue.list);
632 } else {
633 master->xferqueue.cur = xfer;
634 cdns_i3c_master_start_xfer_locked(master);
635 }
636 spin_unlock_irqrestore(&master->xferqueue.lock, flags);
637}
638
639static void cdns_i3c_master_unqueue_xfer(struct cdns_i3c_master *master,
640 struct cdns_i3c_xfer *xfer)
641{
642 unsigned long flags;
643
644 spin_lock_irqsave(&master->xferqueue.lock, flags);
645 if (master->xferqueue.cur == xfer) {
646 u32 status;
647
648 writel(readl(master->regs + CTRL) & ~CTRL_DEV_EN,
649 master->regs + CTRL);
650 readl_poll_timeout_atomic(master->regs + MST_STATUS0, status,
651 status & MST_STATUS0_IDLE, 10,
652 1000000);
653 master->xferqueue.cur = NULL;
654 writel(FLUSH_RX_FIFO | FLUSH_TX_FIFO | FLUSH_CMD_FIFO |
655 FLUSH_CMD_RESP,
656 master->regs + FLUSH_CTRL);
657 writel(MST_INT_CMDD_EMP, master->regs + MST_IDR);
658 writel(readl(master->regs + CTRL) | CTRL_DEV_EN,
659 master->regs + CTRL);
660 } else {
661 list_del_init(&xfer->node);
662 }
663 spin_unlock_irqrestore(&master->xferqueue.lock, flags);
664}
665
666static enum i3c_error_code cdns_i3c_cmd_get_err(struct cdns_i3c_cmd *cmd)
667{
668 switch (cmd->error) {
669 case CMDR_M0_ERROR:
670 return I3C_ERROR_M0;
671
672 case CMDR_M1_ERROR:
673 return I3C_ERROR_M1;
674
675 case CMDR_M2_ERROR:
676 case CMDR_NACK_RESP:
677 return I3C_ERROR_M2;
678
679 default:
680 break;
681 }
682
683 return I3C_ERROR_UNKNOWN;
684}
685
686static int cdns_i3c_master_send_ccc_cmd(struct i3c_master_controller *m,
687 struct i3c_ccc_cmd *cmd)
688{
689 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
690 struct cdns_i3c_xfer *xfer;
691 struct cdns_i3c_cmd *ccmd;
692 int ret;
693
694 xfer = cdns_i3c_master_alloc_xfer(master, 1);
695 if (!xfer)
696 return -ENOMEM;
697
698 ccmd = xfer->cmds;
699 ccmd->cmd1 = CMD1_FIFO_CCC(cmd->id);
700 ccmd->cmd0 = CMD0_FIFO_IS_CCC |
701 CMD0_FIFO_PL_LEN(cmd->dests[0].payload.len);
702
703 if (cmd->id & I3C_CCC_DIRECT)
704 ccmd->cmd0 |= CMD0_FIFO_DEV_ADDR(cmd->dests[0].addr);
705
706 if (cmd->rnw) {
707 ccmd->cmd0 |= CMD0_FIFO_RNW;
708 ccmd->rx_buf = cmd->dests[0].payload.data;
709 ccmd->rx_len = cmd->dests[0].payload.len;
710 } else {
711 ccmd->tx_buf = cmd->dests[0].payload.data;
712 ccmd->tx_len = cmd->dests[0].payload.len;
713 }
714
715 cdns_i3c_master_queue_xfer(master, xfer);
716 if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000)))
717 cdns_i3c_master_unqueue_xfer(master, xfer);
718
719 ret = xfer->ret;
720 cmd->err = cdns_i3c_cmd_get_err(&xfer->cmds[0]);
721 cdns_i3c_master_free_xfer(xfer);
722
723 return ret;
724}
725
726static int cdns_i3c_master_priv_xfers(struct i3c_dev_desc *dev,
727 struct i3c_priv_xfer *xfers,
728 int nxfers)
729{
730 struct i3c_master_controller *m = i3c_dev_get_master(dev);
731 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
732 int txslots = 0, rxslots = 0, i, ret;
733 struct cdns_i3c_xfer *cdns_xfer;
734
735 for (i = 0; i < nxfers; i++) {
736 if (xfers[i].len > CMD0_FIFO_PL_LEN_MAX)
737 return -ENOTSUPP;
738 }
739
740 if (!nxfers)
741 return 0;
742
743 if (nxfers > master->caps.cmdfifodepth ||
744 nxfers > master->caps.cmdrfifodepth)
745 return -ENOTSUPP;
746
747 /*
748 * First make sure that all transactions (block of transfers separated
749 * by a STOP marker) fit in the FIFOs.
750 */
751 for (i = 0; i < nxfers; i++) {
752 if (xfers[i].rnw)
753 rxslots += DIV_ROUND_UP(xfers[i].len, 4);
754 else
755 txslots += DIV_ROUND_UP(xfers[i].len, 4);
756 }
757
758 if (rxslots > master->caps.rxfifodepth ||
759 txslots > master->caps.txfifodepth)
760 return -ENOTSUPP;
761
762 cdns_xfer = cdns_i3c_master_alloc_xfer(master, nxfers);
763 if (!cdns_xfer)
764 return -ENOMEM;
765
766 for (i = 0; i < nxfers; i++) {
767 struct cdns_i3c_cmd *ccmd = &cdns_xfer->cmds[i];
768 u32 pl_len = xfers[i].len;
769
770 ccmd->cmd0 = CMD0_FIFO_DEV_ADDR(dev->info.dyn_addr) |
771 CMD0_FIFO_PRIV_XMIT_MODE(XMIT_BURST_WITHOUT_SUBADDR);
772
773 if (xfers[i].rnw) {
774 ccmd->cmd0 |= CMD0_FIFO_RNW;
775 ccmd->rx_buf = xfers[i].data.in;
776 ccmd->rx_len = xfers[i].len;
777 pl_len++;
778 } else {
779 ccmd->tx_buf = xfers[i].data.out;
780 ccmd->tx_len = xfers[i].len;
781 }
782
783 ccmd->cmd0 |= CMD0_FIFO_PL_LEN(pl_len);
784
785 if (i < nxfers - 1)
786 ccmd->cmd0 |= CMD0_FIFO_RSBC;
787
788 if (!i)
789 ccmd->cmd0 |= CMD0_FIFO_BCH;
790 }
791
792 cdns_i3c_master_queue_xfer(master, cdns_xfer);
793 if (!wait_for_completion_timeout(&cdns_xfer->comp,
794 msecs_to_jiffies(1000)))
795 cdns_i3c_master_unqueue_xfer(master, cdns_xfer);
796
797 ret = cdns_xfer->ret;
798
799 for (i = 0; i < nxfers; i++)
800 xfers[i].err = cdns_i3c_cmd_get_err(&cdns_xfer->cmds[i]);
801
802 cdns_i3c_master_free_xfer(cdns_xfer);
803
804 return ret;
805}
806
807static int cdns_i3c_master_i2c_xfers(struct i2c_dev_desc *dev,
808 const struct i2c_msg *xfers, int nxfers)
809{
810 struct i3c_master_controller *m = i2c_dev_get_master(dev);
811 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
812 unsigned int nrxwords = 0, ntxwords = 0;
813 struct cdns_i3c_xfer *xfer;
814 int i, ret = 0;
815
816 if (nxfers > master->caps.cmdfifodepth)
817 return -ENOTSUPP;
818
819 for (i = 0; i < nxfers; i++) {
820 if (xfers[i].len > CMD0_FIFO_PL_LEN_MAX)
821 return -ENOTSUPP;
822
823 if (xfers[i].flags & I2C_M_RD)
824 nrxwords += DIV_ROUND_UP(xfers[i].len, 4);
825 else
826 ntxwords += DIV_ROUND_UP(xfers[i].len, 4);
827 }
828
829 if (ntxwords > master->caps.txfifodepth ||
830 nrxwords > master->caps.rxfifodepth)
831 return -ENOTSUPP;
832
833 xfer = cdns_i3c_master_alloc_xfer(master, nxfers);
834 if (!xfer)
835 return -ENOMEM;
836
837 for (i = 0; i < nxfers; i++) {
838 struct cdns_i3c_cmd *ccmd = &xfer->cmds[i];
839
840 ccmd->cmd0 = CMD0_FIFO_DEV_ADDR(xfers[i].addr) |
841 CMD0_FIFO_PL_LEN(xfers[i].len) |
842 CMD0_FIFO_PRIV_XMIT_MODE(XMIT_BURST_WITHOUT_SUBADDR);
843
844 if (xfers[i].flags & I2C_M_TEN)
845 ccmd->cmd0 |= CMD0_FIFO_IS_10B;
846
847 if (xfers[i].flags & I2C_M_RD) {
848 ccmd->cmd0 |= CMD0_FIFO_RNW;
849 ccmd->rx_buf = xfers[i].buf;
850 ccmd->rx_len = xfers[i].len;
851 } else {
852 ccmd->tx_buf = xfers[i].buf;
853 ccmd->tx_len = xfers[i].len;
854 }
855 }
856
857 cdns_i3c_master_queue_xfer(master, xfer);
858 if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000)))
859 cdns_i3c_master_unqueue_xfer(master, xfer);
860
861 ret = xfer->ret;
862 cdns_i3c_master_free_xfer(xfer);
863
864 return ret;
865}
866
867static u32 cdns_i3c_master_i2c_funcs(struct i3c_master_controller *m)
868{
869 return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR;
870}
871
872struct cdns_i3c_i2c_dev_data {
873 u16 id;
874 s16 ibi;
875 struct i3c_generic_ibi_pool *ibi_pool;
876};
877
878static u32 prepare_rr0_dev_address(u32 addr)
879{
880 u32 ret = (addr << 1) & 0xff;
881
882 /* RR0[7:1] = addr[6:0] */
883 ret |= (addr & GENMASK(6, 0)) << 1;
884
885 /* RR0[15:13] = addr[9:7] */
886 ret |= (addr & GENMASK(9, 7)) << 6;
887
888 /* RR0[0] = ~XOR(addr[6:0]) */
889 if (!(hweight8(addr & 0x7f) & 1))
890 ret |= 1;
891
892 return ret;
893}
894
895static void cdns_i3c_master_upd_i3c_addr(struct i3c_dev_desc *dev)
896{
897 struct i3c_master_controller *m = i3c_dev_get_master(dev);
898 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
899 struct cdns_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
900 u32 rr;
901
902 rr = prepare_rr0_dev_address(dev->info.dyn_addr ?
903 dev->info.dyn_addr :
904 dev->info.static_addr);
905 writel(DEV_ID_RR0_IS_I3C | rr, master->regs + DEV_ID_RR0(data->id));
906}
907
908static int cdns_i3c_master_get_rr_slot(struct cdns_i3c_master *master,
909 u8 dyn_addr)
910{
911 u32 activedevs, rr;
912 int i;
913
914 if (!dyn_addr) {
915 if (!master->free_rr_slots)
916 return -ENOSPC;
917
918 return ffs(master->free_rr_slots) - 1;
919 }
920
921 activedevs = readl(master->regs + DEVS_CTRL) &
922 DEVS_CTRL_DEVS_ACTIVE_MASK;
923
924 for (i = 1; i <= master->maxdevs; i++) {
925 if (!(BIT(i) & activedevs))
926 continue;
927
928 rr = readl(master->regs + DEV_ID_RR0(i));
929 if (!(rr & DEV_ID_RR0_IS_I3C) ||
930 DEV_ID_RR0_GET_DEV_ADDR(rr) != dyn_addr)
931 continue;
932
933 return i;
934 }
935
936 return -EINVAL;
937}
938
939static int cdns_i3c_master_reattach_i3c_dev(struct i3c_dev_desc *dev,
940 u8 old_dyn_addr)
941{
942 cdns_i3c_master_upd_i3c_addr(dev);
943
944 return 0;
945}
946
947static int cdns_i3c_master_attach_i3c_dev(struct i3c_dev_desc *dev)
948{
949 struct i3c_master_controller *m = i3c_dev_get_master(dev);
950 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
951 struct cdns_i3c_i2c_dev_data *data;
952 int slot;
953
954 data = kzalloc(sizeof(*data), GFP_KERNEL);
955 if (!data)
956 return -ENOMEM;
957
958 slot = cdns_i3c_master_get_rr_slot(master, dev->info.dyn_addr);
959 if (slot < 0) {
960 kfree(data);
961 return slot;
962 }
963
964 data->ibi = -1;
965 data->id = slot;
966 i3c_dev_set_master_data(dev, data);
967 master->free_rr_slots &= ~BIT(slot);
968
969 if (!dev->info.dyn_addr) {
970 cdns_i3c_master_upd_i3c_addr(dev);
971 writel(readl(master->regs + DEVS_CTRL) |
972 DEVS_CTRL_DEV_ACTIVE(data->id),
973 master->regs + DEVS_CTRL);
974 }
975
976 return 0;
977}
978
979static void cdns_i3c_master_detach_i3c_dev(struct i3c_dev_desc *dev)
980{
981 struct i3c_master_controller *m = i3c_dev_get_master(dev);
982 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
983 struct cdns_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
984
985 writel(readl(master->regs + DEVS_CTRL) |
986 DEVS_CTRL_DEV_CLR(data->id),
987 master->regs + DEVS_CTRL);
988
989 i3c_dev_set_master_data(dev, NULL);
990 master->free_rr_slots |= BIT(data->id);
991 kfree(data);
992}
993
994static int cdns_i3c_master_attach_i2c_dev(struct i2c_dev_desc *dev)
995{
996 struct i3c_master_controller *m = i2c_dev_get_master(dev);
997 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
998 struct cdns_i3c_i2c_dev_data *data;
999 int slot;
1000
1001 slot = cdns_i3c_master_get_rr_slot(master, 0);
1002 if (slot < 0)
1003 return slot;
1004
1005 data = kzalloc(sizeof(*data), GFP_KERNEL);
1006 if (!data)
1007 return -ENOMEM;
1008
1009 data->id = slot;
1010 master->free_rr_slots &= ~BIT(slot);
1011 i2c_dev_set_master_data(dev, data);
1012
1013 writel(prepare_rr0_dev_address(dev->boardinfo->base.addr) |
1014 (dev->boardinfo->base.flags & I2C_CLIENT_TEN ?
1015 DEV_ID_RR0_LVR_EXT_ADDR : 0),
1016 master->regs + DEV_ID_RR0(data->id));
1017 writel(dev->boardinfo->lvr, master->regs + DEV_ID_RR2(data->id));
1018 writel(readl(master->regs + DEVS_CTRL) |
1019 DEVS_CTRL_DEV_ACTIVE(data->id),
1020 master->regs + DEVS_CTRL);
1021
1022 return 0;
1023}
1024
1025static void cdns_i3c_master_detach_i2c_dev(struct i2c_dev_desc *dev)
1026{
1027 struct i3c_master_controller *m = i2c_dev_get_master(dev);
1028 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
1029 struct cdns_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev);
1030
1031 writel(readl(master->regs + DEVS_CTRL) |
1032 DEVS_CTRL_DEV_CLR(data->id),
1033 master->regs + DEVS_CTRL);
1034 master->free_rr_slots |= BIT(data->id);
1035
1036 i2c_dev_set_master_data(dev, NULL);
1037 kfree(data);
1038}
1039
1040static void cdns_i3c_master_bus_cleanup(struct i3c_master_controller *m)
1041{
1042 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
1043
1044 cdns_i3c_master_disable(master);
1045}
1046
1047static void cdns_i3c_master_dev_rr_to_info(struct cdns_i3c_master *master,
1048 unsigned int slot,
1049 struct i3c_device_info *info)
1050{
1051 u32 rr;
1052
1053 memset(info, 0, sizeof(*info));
1054 rr = readl(master->regs + DEV_ID_RR0(slot));
1055 info->dyn_addr = DEV_ID_RR0_GET_DEV_ADDR(rr);
1056 rr = readl(master->regs + DEV_ID_RR2(slot));
1057 info->dcr = rr;
1058 info->bcr = rr >> 8;
1059 info->pid = rr >> 16;
1060 info->pid |= (u64)readl(master->regs + DEV_ID_RR1(slot)) << 16;
1061}
1062
1063static void cdns_i3c_master_upd_i3c_scl_lim(struct cdns_i3c_master *master)
1064{
1065 struct i3c_master_controller *m = &master->base;
1066 unsigned long i3c_lim_period, pres_step, ncycles;
1067 struct i3c_bus *bus = i3c_master_get_bus(m);
1068 unsigned long new_i3c_scl_lim = 0;
1069 struct i3c_dev_desc *dev;
1070 u32 prescl1, ctrl;
1071
1072 i3c_bus_for_each_i3cdev(bus, dev) {
1073 unsigned long max_fscl;
1074
1075 max_fscl = max(I3C_CCC_MAX_SDR_FSCL(dev->info.max_read_ds),
1076 I3C_CCC_MAX_SDR_FSCL(dev->info.max_write_ds));
1077 switch (max_fscl) {
1078 case I3C_SDR1_FSCL_8MHZ:
1079 max_fscl = 8000000;
1080 break;
1081 case I3C_SDR2_FSCL_6MHZ:
1082 max_fscl = 6000000;
1083 break;
1084 case I3C_SDR3_FSCL_4MHZ:
1085 max_fscl = 4000000;
1086 break;
1087 case I3C_SDR4_FSCL_2MHZ:
1088 max_fscl = 2000000;
1089 break;
1090 case I3C_SDR0_FSCL_MAX:
1091 default:
1092 max_fscl = 0;
1093 break;
1094 }
1095
1096 if (max_fscl &&
1097 (new_i3c_scl_lim > max_fscl || !new_i3c_scl_lim))
1098 new_i3c_scl_lim = max_fscl;
1099 }
1100
1101 /* Only update PRESCL_CTRL1 if the I3C SCL limitation has changed. */
1102 if (new_i3c_scl_lim == master->i3c_scl_lim)
1103 return;
1104 master->i3c_scl_lim = new_i3c_scl_lim;
1105 if (!new_i3c_scl_lim)
1106 return;
1107 pres_step = 1000000000UL / (bus->scl_rate.i3c * 4);
1108
1109 /* Configure PP_LOW to meet I3C slave limitations. */
1110 prescl1 = readl(master->regs + PRESCL_CTRL1) &
1111 ~PRESCL_CTRL1_PP_LOW_MASK;
1112 ctrl = readl(master->regs + CTRL);
1113
1114 i3c_lim_period = DIV_ROUND_UP(1000000000, master->i3c_scl_lim);
1115 ncycles = DIV_ROUND_UP(i3c_lim_period, pres_step);
1116 if (ncycles < 4)
1117 ncycles = 0;
1118 else
1119 ncycles -= 4;
1120
1121 prescl1 |= PRESCL_CTRL1_PP_LOW(ncycles);
1122
1123 /* Disable I3C master before updating PRESCL_CTRL1. */
1124 if (ctrl & CTRL_DEV_EN)
1125 cdns_i3c_master_disable(master);
1126
1127 writel(prescl1, master->regs + PRESCL_CTRL1);
1128
1129 if (ctrl & CTRL_DEV_EN)
1130 cdns_i3c_master_enable(master);
1131}
1132
1133static int cdns_i3c_master_do_daa(struct i3c_master_controller *m)
1134{
1135 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
1136 u32 olddevs, newdevs;
1137 int ret, slot;
1138 u8 addrs[MAX_DEVS] = { };
1139 u8 last_addr = 0;
1140
1141 olddevs = readl(master->regs + DEVS_CTRL) & DEVS_CTRL_DEVS_ACTIVE_MASK;
1142
1143 /* Prepare RR slots before launching DAA. */
1144 for (slot = 1; slot <= master->maxdevs; slot++) {
1145 if (olddevs & BIT(slot))
1146 continue;
1147
1148 ret = i3c_master_get_free_addr(m, last_addr + 1);
1149 if (ret < 0)
1150 return -ENOSPC;
1151
1152 last_addr = ret;
1153 addrs[slot] = last_addr;
1154 writel(prepare_rr0_dev_address(last_addr) | DEV_ID_RR0_IS_I3C,
1155 master->regs + DEV_ID_RR0(slot));
1156 writel(0, master->regs + DEV_ID_RR1(slot));
1157 writel(0, master->regs + DEV_ID_RR2(slot));
1158 }
1159
1160 ret = i3c_master_entdaa_locked(&master->base);
1161 if (ret && ret != I3C_ERROR_M2)
1162 return ret;
1163
1164 newdevs = readl(master->regs + DEVS_CTRL) & DEVS_CTRL_DEVS_ACTIVE_MASK;
1165 newdevs &= ~olddevs;
1166
1167 /*
1168 * Clear all retaining registers filled during DAA. We already
1169 * have the addressed assigned to them in the addrs array.
1170 */
1171 for (slot = 1; slot <= master->maxdevs; slot++) {
1172 if (newdevs & BIT(slot))
1173 i3c_master_add_i3c_dev_locked(m, addrs[slot]);
1174 }
1175
1176 /*
1177 * Clear slots that ended up not being used. Can be caused by I3C
1178 * device creation failure or when the I3C device was already known
1179 * by the system but with a different address (in this case the device
1180 * already has a slot and does not need a new one).
1181 */
1182 writel(readl(master->regs + DEVS_CTRL) |
1183 master->free_rr_slots << DEVS_CTRL_DEV_CLR_SHIFT,
1184 master->regs + DEVS_CTRL);
1185
1186 i3c_master_defslvs_locked(&master->base);
1187
1188 cdns_i3c_master_upd_i3c_scl_lim(master);
1189
1190 /* Unmask Hot-Join and Mastership request interrupts. */
1191 i3c_master_enec_locked(m, I3C_BROADCAST_ADDR,
1192 I3C_CCC_EVENT_HJ | I3C_CCC_EVENT_MR);
1193
1194 return 0;
1195}
1196
1197static int cdns_i3c_master_bus_init(struct i3c_master_controller *m)
1198{
1199 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
1200 unsigned long pres_step, sysclk_rate, max_i2cfreq;
1201 struct i3c_bus *bus = i3c_master_get_bus(m);
1202 u32 ctrl, prescl0, prescl1, pres, low;
1203 struct i3c_device_info info = { };
1204 int ret, ncycles;
1205
1206 switch (bus->mode) {
1207 case I3C_BUS_MODE_PURE:
1208 ctrl = CTRL_PURE_BUS_MODE;
1209 break;
1210
1211 case I3C_BUS_MODE_MIXED_FAST:
1212 ctrl = CTRL_MIXED_FAST_BUS_MODE;
1213 break;
1214
1215 case I3C_BUS_MODE_MIXED_SLOW:
1216 ctrl = CTRL_MIXED_SLOW_BUS_MODE;
1217 break;
1218
1219 default:
1220 return -EINVAL;
1221 }
1222
1223 sysclk_rate = clk_get_rate(master->sysclk);
1224 if (!sysclk_rate)
1225 return -EINVAL;
1226
1227 pres = DIV_ROUND_UP(sysclk_rate, (bus->scl_rate.i3c * 4)) - 1;
1228 if (pres > PRESCL_CTRL0_MAX)
1229 return -ERANGE;
1230
1231 bus->scl_rate.i3c = sysclk_rate / ((pres + 1) * 4);
1232
1233 prescl0 = PRESCL_CTRL0_I3C(pres);
1234
1235 low = ((I3C_BUS_TLOW_OD_MIN_NS * sysclk_rate) / (pres + 1)) - 2;
1236 prescl1 = PRESCL_CTRL1_OD_LOW(low);
1237
1238 max_i2cfreq = bus->scl_rate.i2c;
1239
1240 pres = (sysclk_rate / (max_i2cfreq * 5)) - 1;
1241 if (pres > PRESCL_CTRL0_MAX)
1242 return -ERANGE;
1243
1244 bus->scl_rate.i2c = sysclk_rate / ((pres + 1) * 5);
1245
1246 prescl0 |= PRESCL_CTRL0_I2C(pres);
1247 writel(prescl0, master->regs + PRESCL_CTRL0);
1248
1249 /* Calculate OD and PP low. */
1250 pres_step = 1000000000 / (bus->scl_rate.i3c * 4);
1251 ncycles = DIV_ROUND_UP(I3C_BUS_TLOW_OD_MIN_NS, pres_step) - 2;
1252 if (ncycles < 0)
1253 ncycles = 0;
1254 prescl1 = PRESCL_CTRL1_OD_LOW(ncycles);
1255 writel(prescl1, master->regs + PRESCL_CTRL1);
1256
1257 /* Get an address for the master. */
1258 ret = i3c_master_get_free_addr(m, 0);
1259 if (ret < 0)
1260 return ret;
1261
1262 writel(prepare_rr0_dev_address(ret) | DEV_ID_RR0_IS_I3C,
1263 master->regs + DEV_ID_RR0(0));
1264
1265 cdns_i3c_master_dev_rr_to_info(master, 0, &info);
1266 if (info.bcr & I3C_BCR_HDR_CAP)
1267 info.hdr_cap = I3C_CCC_HDR_MODE(I3C_HDR_DDR);
1268
1269 ret = i3c_master_set_info(&master->base, &info);
1270 if (ret)
1271 return ret;
1272
1273 /*
1274 * Enable Hot-Join, and, when a Hot-Join request happens, disable all
1275 * events coming from this device.
1276 *
1277 * We will issue ENTDAA afterwards from the threaded IRQ handler.
1278 */
1279 ctrl |= CTRL_HJ_ACK | CTRL_HJ_DISEC | CTRL_HALT_EN | CTRL_MCS_EN;
1280 writel(ctrl, master->regs + CTRL);
1281
1282 cdns_i3c_master_enable(master);
1283
1284 return 0;
1285}
1286
1287static void cdns_i3c_master_handle_ibi(struct cdns_i3c_master *master,
1288 u32 ibir)
1289{
1290 struct cdns_i3c_i2c_dev_data *data;
1291 bool data_consumed = false;
1292 struct i3c_ibi_slot *slot;
1293 u32 id = IBIR_SLVID(ibir);
1294 struct i3c_dev_desc *dev;
1295 size_t nbytes;
1296 u8 *buf;
1297
1298 /*
1299 * FIXME: maybe we should report the FIFO OVF errors to the upper
1300 * layer.
1301 */
1302 if (id >= master->ibi.num_slots || (ibir & IBIR_ERROR))
1303 goto out;
1304
1305 dev = master->ibi.slots[id];
1306 spin_lock(&master->ibi.lock);
1307
1308 data = i3c_dev_get_master_data(dev);
1309 slot = i3c_generic_ibi_get_free_slot(data->ibi_pool);
1310 if (!slot)
1311 goto out_unlock;
1312
1313 buf = slot->data;
1314
1315 nbytes = IBIR_XFER_BYTES(ibir);
1316 readsl(master->regs + IBI_DATA_FIFO, buf, nbytes / 4);
1317 if (nbytes % 3) {
1318 u32 tmp = __raw_readl(master->regs + IBI_DATA_FIFO);
1319
1320 memcpy(buf + (nbytes & ~3), &tmp, nbytes & 3);
1321 }
1322
1323 slot->len = min_t(unsigned int, IBIR_XFER_BYTES(ibir),
1324 dev->ibi->max_payload_len);
1325 i3c_master_queue_ibi(dev, slot);
1326 data_consumed = true;
1327
1328out_unlock:
1329 spin_unlock(&master->ibi.lock);
1330
1331out:
1332 /* Consume data from the FIFO if it's not been done already. */
1333 if (!data_consumed) {
1334 int i;
1335
1336 for (i = 0; i < IBIR_XFER_BYTES(ibir); i += 4)
1337 readl(master->regs + IBI_DATA_FIFO);
1338 }
1339}
1340
1341static void cnds_i3c_master_demux_ibis(struct cdns_i3c_master *master)
1342{
1343 u32 status0;
1344
1345 writel(MST_INT_IBIR_THR, master->regs + MST_ICR);
1346
1347 for (status0 = readl(master->regs + MST_STATUS0);
1348 !(status0 & MST_STATUS0_IBIR_EMP);
1349 status0 = readl(master->regs + MST_STATUS0)) {
1350 u32 ibir = readl(master->regs + IBIR);
1351
1352 switch (IBIR_TYPE(ibir)) {
1353 case IBIR_TYPE_IBI:
1354 cdns_i3c_master_handle_ibi(master, ibir);
1355 break;
1356
1357 case IBIR_TYPE_HJ:
1358 WARN_ON(IBIR_XFER_BYTES(ibir) || (ibir & IBIR_ERROR));
1359 queue_work(master->base.wq, &master->hj_work);
1360 break;
1361
1362 case IBIR_TYPE_MR:
1363 WARN_ON(IBIR_XFER_BYTES(ibir) || (ibir & IBIR_ERROR));
1364 default:
1365 break;
1366 }
1367 }
1368}
1369
1370static irqreturn_t cdns_i3c_master_interrupt(int irq, void *data)
1371{
1372 struct cdns_i3c_master *master = data;
1373 u32 status;
1374
1375 status = readl(master->regs + MST_ISR);
1376 if (!(status & readl(master->regs + MST_IMR)))
1377 return IRQ_NONE;
1378
1379 spin_lock(&master->xferqueue.lock);
1380 cdns_i3c_master_end_xfer_locked(master, status);
1381 spin_unlock(&master->xferqueue.lock);
1382
1383 if (status & MST_INT_IBIR_THR)
1384 cnds_i3c_master_demux_ibis(master);
1385
1386 return IRQ_HANDLED;
1387}
1388
1389static int cdns_i3c_master_disable_ibi(struct i3c_dev_desc *dev)
1390{
1391 struct i3c_master_controller *m = i3c_dev_get_master(dev);
1392 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
1393 struct cdns_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
1394 unsigned long flags;
1395 u32 sirmap;
1396 int ret;
1397
1398 ret = i3c_master_disec_locked(m, dev->info.dyn_addr,
1399 I3C_CCC_EVENT_SIR);
1400 if (ret)
1401 return ret;
1402
1403 spin_lock_irqsave(&master->ibi.lock, flags);
1404 sirmap = readl(master->regs + SIR_MAP_DEV_REG(data->ibi));
1405 sirmap &= ~SIR_MAP_DEV_CONF_MASK(data->ibi);
1406 sirmap |= SIR_MAP_DEV_CONF(data->ibi,
1407 SIR_MAP_DEV_DA(I3C_BROADCAST_ADDR));
1408 writel(sirmap, master->regs + SIR_MAP_DEV_REG(data->ibi));
1409 spin_unlock_irqrestore(&master->ibi.lock, flags);
1410
1411 return ret;
1412}
1413
1414static int cdns_i3c_master_enable_ibi(struct i3c_dev_desc *dev)
1415{
1416 struct i3c_master_controller *m = i3c_dev_get_master(dev);
1417 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
1418 struct cdns_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
1419 unsigned long flags;
1420 u32 sircfg, sirmap;
1421 int ret;
1422
1423 spin_lock_irqsave(&master->ibi.lock, flags);
1424 sirmap = readl(master->regs + SIR_MAP_DEV_REG(data->ibi));
1425 sirmap &= ~SIR_MAP_DEV_CONF_MASK(data->ibi);
1426 sircfg = SIR_MAP_DEV_ROLE(dev->info.bcr >> 6) |
1427 SIR_MAP_DEV_DA(dev->info.dyn_addr) |
1428 SIR_MAP_DEV_PL(dev->info.max_ibi_len) |
1429 SIR_MAP_DEV_ACK;
1430
1431 if (dev->info.bcr & I3C_BCR_MAX_DATA_SPEED_LIM)
1432 sircfg |= SIR_MAP_DEV_SLOW;
1433
1434 sirmap |= SIR_MAP_DEV_CONF(data->ibi, sircfg);
1435 writel(sirmap, master->regs + SIR_MAP_DEV_REG(data->ibi));
1436 spin_unlock_irqrestore(&master->ibi.lock, flags);
1437
1438 ret = i3c_master_enec_locked(m, dev->info.dyn_addr,
1439 I3C_CCC_EVENT_SIR);
1440 if (ret) {
1441 spin_lock_irqsave(&master->ibi.lock, flags);
1442 sirmap = readl(master->regs + SIR_MAP_DEV_REG(data->ibi));
1443 sirmap &= ~SIR_MAP_DEV_CONF_MASK(data->ibi);
1444 sirmap |= SIR_MAP_DEV_CONF(data->ibi,
1445 SIR_MAP_DEV_DA(I3C_BROADCAST_ADDR));
1446 writel(sirmap, master->regs + SIR_MAP_DEV_REG(data->ibi));
1447 spin_unlock_irqrestore(&master->ibi.lock, flags);
1448 }
1449
1450 return ret;
1451}
1452
1453static int cdns_i3c_master_request_ibi(struct i3c_dev_desc *dev,
1454 const struct i3c_ibi_setup *req)
1455{
1456 struct i3c_master_controller *m = i3c_dev_get_master(dev);
1457 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
1458 struct cdns_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
1459 unsigned long flags;
1460 unsigned int i;
1461
1462 data->ibi_pool = i3c_generic_ibi_alloc_pool(dev, req);
1463 if (IS_ERR(data->ibi_pool))
1464 return PTR_ERR(data->ibi_pool);
1465
1466 spin_lock_irqsave(&master->ibi.lock, flags);
1467 for (i = 0; i < master->ibi.num_slots; i++) {
1468 if (!master->ibi.slots[i]) {
1469 data->ibi = i;
1470 master->ibi.slots[i] = dev;
1471 break;
1472 }
1473 }
1474 spin_unlock_irqrestore(&master->ibi.lock, flags);
1475
1476 if (i < master->ibi.num_slots)
1477 return 0;
1478
1479 i3c_generic_ibi_free_pool(data->ibi_pool);
1480 data->ibi_pool = NULL;
1481
1482 return -ENOSPC;
1483}
1484
1485static void cdns_i3c_master_free_ibi(struct i3c_dev_desc *dev)
1486{
1487 struct i3c_master_controller *m = i3c_dev_get_master(dev);
1488 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
1489 struct cdns_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
1490 unsigned long flags;
1491
1492 spin_lock_irqsave(&master->ibi.lock, flags);
1493 master->ibi.slots[data->ibi] = NULL;
1494 data->ibi = -1;
1495 spin_unlock_irqrestore(&master->ibi.lock, flags);
1496
1497 i3c_generic_ibi_free_pool(data->ibi_pool);
1498}
1499
1500static void cdns_i3c_master_recycle_ibi_slot(struct i3c_dev_desc *dev,
1501 struct i3c_ibi_slot *slot)
1502{
1503 struct cdns_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
1504
1505 i3c_generic_ibi_recycle_slot(data->ibi_pool, slot);
1506}
1507
1508static const struct i3c_master_controller_ops cdns_i3c_master_ops = {
1509 .bus_init = cdns_i3c_master_bus_init,
1510 .bus_cleanup = cdns_i3c_master_bus_cleanup,
1511 .do_daa = cdns_i3c_master_do_daa,
1512 .attach_i3c_dev = cdns_i3c_master_attach_i3c_dev,
1513 .reattach_i3c_dev = cdns_i3c_master_reattach_i3c_dev,
1514 .detach_i3c_dev = cdns_i3c_master_detach_i3c_dev,
1515 .attach_i2c_dev = cdns_i3c_master_attach_i2c_dev,
1516 .detach_i2c_dev = cdns_i3c_master_detach_i2c_dev,
1517 .supports_ccc_cmd = cdns_i3c_master_supports_ccc_cmd,
1518 .send_ccc_cmd = cdns_i3c_master_send_ccc_cmd,
1519 .priv_xfers = cdns_i3c_master_priv_xfers,
1520 .i2c_xfers = cdns_i3c_master_i2c_xfers,
1521 .i2c_funcs = cdns_i3c_master_i2c_funcs,
1522 .enable_ibi = cdns_i3c_master_enable_ibi,
1523 .disable_ibi = cdns_i3c_master_disable_ibi,
1524 .request_ibi = cdns_i3c_master_request_ibi,
1525 .free_ibi = cdns_i3c_master_free_ibi,
1526 .recycle_ibi_slot = cdns_i3c_master_recycle_ibi_slot,
1527};
1528
1529static void cdns_i3c_master_hj(struct work_struct *work)
1530{
1531 struct cdns_i3c_master *master = container_of(work,
1532 struct cdns_i3c_master,
1533 hj_work);
1534
1535 i3c_master_do_daa(&master->base);
1536}
1537
1538static int cdns_i3c_master_probe(struct platform_device *pdev)
1539{
1540 struct cdns_i3c_master *master;
1541 struct resource *res;
1542 int ret, irq;
1543 u32 val;
1544
1545 master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL);
1546 if (!master)
1547 return -ENOMEM;
1548
1549 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1550 master->regs = devm_ioremap_resource(&pdev->dev, res);
1551 if (IS_ERR(master->regs))
1552 return PTR_ERR(master->regs);
1553
1554 master->pclk = devm_clk_get(&pdev->dev, "pclk");
1555 if (IS_ERR(master->pclk))
1556 return PTR_ERR(master->pclk);
1557
1558 master->sysclk = devm_clk_get(&pdev->dev, "sysclk");
1559 if (IS_ERR(master->pclk))
1560 return PTR_ERR(master->pclk);
1561
1562 irq = platform_get_irq(pdev, 0);
1563 if (irq < 0)
1564 return irq;
1565
1566 ret = clk_prepare_enable(master->pclk);
1567 if (ret)
1568 return ret;
1569
1570 ret = clk_prepare_enable(master->sysclk);
1571 if (ret)
1572 goto err_disable_pclk;
1573
1574 if (readl(master->regs + DEV_ID) != DEV_ID_I3C_MASTER) {
1575 ret = -EINVAL;
1576 goto err_disable_sysclk;
1577 }
1578
1579 spin_lock_init(&master->xferqueue.lock);
1580 INIT_LIST_HEAD(&master->xferqueue.list);
1581
1582 INIT_WORK(&master->hj_work, cdns_i3c_master_hj);
1583 writel(0xffffffff, master->regs + MST_IDR);
1584 writel(0xffffffff, master->regs + SLV_IDR);
1585 ret = devm_request_irq(&pdev->dev, irq, cdns_i3c_master_interrupt, 0,
1586 dev_name(&pdev->dev), master);
1587 if (ret)
1588 goto err_disable_sysclk;
1589
1590 platform_set_drvdata(pdev, master);
1591
1592 val = readl(master->regs + CONF_STATUS0);
1593
1594 /* Device ID0 is reserved to describe this master. */
1595 master->maxdevs = CONF_STATUS0_DEVS_NUM(val);
1596 master->free_rr_slots = GENMASK(master->maxdevs, 1);
1597
1598 val = readl(master->regs + CONF_STATUS1);
1599 master->caps.cmdfifodepth = CONF_STATUS1_CMD_DEPTH(val);
1600 master->caps.rxfifodepth = CONF_STATUS1_RX_DEPTH(val);
1601 master->caps.txfifodepth = CONF_STATUS1_TX_DEPTH(val);
1602 master->caps.ibirfifodepth = CONF_STATUS0_IBIR_DEPTH(val);
1603 master->caps.cmdrfifodepth = CONF_STATUS0_CMDR_DEPTH(val);
1604
1605 spin_lock_init(&master->ibi.lock);
1606 master->ibi.num_slots = CONF_STATUS1_IBI_HW_RES(val);
1607 master->ibi.slots = devm_kcalloc(&pdev->dev, master->ibi.num_slots,
1608 sizeof(*master->ibi.slots),
1609 GFP_KERNEL);
1610 if (!master->ibi.slots)
1611 goto err_disable_sysclk;
1612
1613 writel(IBIR_THR(1), master->regs + CMD_IBI_THR_CTRL);
1614 writel(MST_INT_IBIR_THR, master->regs + MST_IER);
1615 writel(DEVS_CTRL_DEV_CLR_ALL, master->regs + DEVS_CTRL);
1616
1617 ret = i3c_master_register(&master->base, &pdev->dev,
1618 &cdns_i3c_master_ops, false);
1619 if (ret)
1620 goto err_disable_sysclk;
1621
1622 return 0;
1623
1624err_disable_sysclk:
1625 clk_disable_unprepare(master->sysclk);
1626
1627err_disable_pclk:
1628 clk_disable_unprepare(master->pclk);
1629
1630 return ret;
1631}
1632
1633static int cdns_i3c_master_remove(struct platform_device *pdev)
1634{
1635 struct cdns_i3c_master *master = platform_get_drvdata(pdev);
1636 int ret;
1637
1638 ret = i3c_master_unregister(&master->base);
1639 if (ret)
1640 return ret;
1641
1642 clk_disable_unprepare(master->sysclk);
1643 clk_disable_unprepare(master->pclk);
1644
1645 return 0;
1646}
1647
1648static const struct of_device_id cdns_i3c_master_of_ids[] = {
1649 { .compatible = "cdns,i3c-master" },
1650 { /* sentinel */ },
1651};
1652
1653static struct platform_driver cdns_i3c_master = {
1654 .probe = cdns_i3c_master_probe,
1655 .remove = cdns_i3c_master_remove,
1656 .driver = {
1657 .name = "cdns-i3c-master",
1658 .of_match_table = cdns_i3c_master_of_ids,
1659 },
1660};
1661module_platform_driver(cdns_i3c_master);
1662
1663MODULE_AUTHOR("Boris Brezillon <boris.brezillon@bootlin.com>");
1664MODULE_DESCRIPTION("Cadence I3C master driver");
1665MODULE_LICENSE("GPL v2");
1666MODULE_ALIAS("platform:cdns-i3c-master");
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-26 09:11:36 -0400