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Diffstat (limited to 'drivers/i2c/busses/i2c-stm32f7.c')
-rw-r--r--drivers/i2c/busses/i2c-stm32f7.c1045
1 files changed, 1017 insertions, 28 deletions
diff --git a/drivers/i2c/busses/i2c-stm32f7.c b/drivers/i2c/busses/i2c-stm32f7.c
index f273e28c39db..62d023e737d9 100644
--- a/drivers/i2c/busses/i2c-stm32f7.c
+++ b/drivers/i2c/busses/i2c-stm32f7.c
@@ -35,6 +35,9 @@
35/* STM32F7 I2C registers */ 35/* STM32F7 I2C registers */
36#define STM32F7_I2C_CR1 0x00 36#define STM32F7_I2C_CR1 0x00
37#define STM32F7_I2C_CR2 0x04 37#define STM32F7_I2C_CR2 0x04
38#define STM32F7_I2C_OAR1 0x08
39#define STM32F7_I2C_OAR2 0x0C
40#define STM32F7_I2C_PECR 0x20
38#define STM32F7_I2C_TIMINGR 0x10 41#define STM32F7_I2C_TIMINGR 0x10
39#define STM32F7_I2C_ISR 0x18 42#define STM32F7_I2C_ISR 0x18
40#define STM32F7_I2C_ICR 0x1C 43#define STM32F7_I2C_ICR 0x1C
@@ -42,6 +45,10 @@
42#define STM32F7_I2C_TXDR 0x28 45#define STM32F7_I2C_TXDR 0x28
43 46
44/* STM32F7 I2C control 1 */ 47/* STM32F7 I2C control 1 */
48#define STM32F7_I2C_CR1_PECEN BIT(23)
49#define STM32F7_I2C_CR1_SBC BIT(16)
50#define STM32F7_I2C_CR1_RXDMAEN BIT(15)
51#define STM32F7_I2C_CR1_TXDMAEN BIT(14)
45#define STM32F7_I2C_CR1_ANFOFF BIT(12) 52#define STM32F7_I2C_CR1_ANFOFF BIT(12)
46#define STM32F7_I2C_CR1_ERRIE BIT(7) 53#define STM32F7_I2C_CR1_ERRIE BIT(7)
47#define STM32F7_I2C_CR1_TCIE BIT(6) 54#define STM32F7_I2C_CR1_TCIE BIT(6)
@@ -57,34 +64,77 @@
57 | STM32F7_I2C_CR1_NACKIE \ 64 | STM32F7_I2C_CR1_NACKIE \
58 | STM32F7_I2C_CR1_RXIE \ 65 | STM32F7_I2C_CR1_RXIE \
59 | STM32F7_I2C_CR1_TXIE) 66 | STM32F7_I2C_CR1_TXIE)
67#define STM32F7_I2C_XFER_IRQ_MASK (STM32F7_I2C_CR1_TCIE \
68 | STM32F7_I2C_CR1_STOPIE \
69 | STM32F7_I2C_CR1_NACKIE \
70 | STM32F7_I2C_CR1_RXIE \
71 | STM32F7_I2C_CR1_TXIE)
60 72
61/* STM32F7 I2C control 2 */ 73/* STM32F7 I2C control 2 */
74#define STM32F7_I2C_CR2_PECBYTE BIT(26)
62#define STM32F7_I2C_CR2_RELOAD BIT(24) 75#define STM32F7_I2C_CR2_RELOAD BIT(24)
63#define STM32F7_I2C_CR2_NBYTES_MASK GENMASK(23, 16) 76#define STM32F7_I2C_CR2_NBYTES_MASK GENMASK(23, 16)
64#define STM32F7_I2C_CR2_NBYTES(n) (((n) & 0xff) << 16) 77#define STM32F7_I2C_CR2_NBYTES(n) (((n) & 0xff) << 16)
65#define STM32F7_I2C_CR2_NACK BIT(15) 78#define STM32F7_I2C_CR2_NACK BIT(15)
66#define STM32F7_I2C_CR2_STOP BIT(14) 79#define STM32F7_I2C_CR2_STOP BIT(14)
67#define STM32F7_I2C_CR2_START BIT(13) 80#define STM32F7_I2C_CR2_START BIT(13)
81#define STM32F7_I2C_CR2_HEAD10R BIT(12)
82#define STM32F7_I2C_CR2_ADD10 BIT(11)
68#define STM32F7_I2C_CR2_RD_WRN BIT(10) 83#define STM32F7_I2C_CR2_RD_WRN BIT(10)
84#define STM32F7_I2C_CR2_SADD10_MASK GENMASK(9, 0)
85#define STM32F7_I2C_CR2_SADD10(n) (((n) & \
86 STM32F7_I2C_CR2_SADD10_MASK))
69#define STM32F7_I2C_CR2_SADD7_MASK GENMASK(7, 1) 87#define STM32F7_I2C_CR2_SADD7_MASK GENMASK(7, 1)
70#define STM32F7_I2C_CR2_SADD7(n) (((n) & 0x7f) << 1) 88#define STM32F7_I2C_CR2_SADD7(n) (((n) & 0x7f) << 1)
71 89
90/* STM32F7 I2C Own Address 1 */
91#define STM32F7_I2C_OAR1_OA1EN BIT(15)
92#define STM32F7_I2C_OAR1_OA1MODE BIT(10)
93#define STM32F7_I2C_OAR1_OA1_10_MASK GENMASK(9, 0)
94#define STM32F7_I2C_OAR1_OA1_10(n) (((n) & \
95 STM32F7_I2C_OAR1_OA1_10_MASK))
96#define STM32F7_I2C_OAR1_OA1_7_MASK GENMASK(7, 1)
97#define STM32F7_I2C_OAR1_OA1_7(n) (((n) & 0x7f) << 1)
98#define STM32F7_I2C_OAR1_MASK (STM32F7_I2C_OAR1_OA1_7_MASK \
99 | STM32F7_I2C_OAR1_OA1_10_MASK \
100 | STM32F7_I2C_OAR1_OA1EN \
101 | STM32F7_I2C_OAR1_OA1MODE)
102
103/* STM32F7 I2C Own Address 2 */
104#define STM32F7_I2C_OAR2_OA2EN BIT(15)
105#define STM32F7_I2C_OAR2_OA2MSK_MASK GENMASK(10, 8)
106#define STM32F7_I2C_OAR2_OA2MSK(n) (((n) & 0x7) << 8)
107#define STM32F7_I2C_OAR2_OA2_7_MASK GENMASK(7, 1)
108#define STM32F7_I2C_OAR2_OA2_7(n) (((n) & 0x7f) << 1)
109#define STM32F7_I2C_OAR2_MASK (STM32F7_I2C_OAR2_OA2MSK_MASK \
110 | STM32F7_I2C_OAR2_OA2_7_MASK \
111 | STM32F7_I2C_OAR2_OA2EN)
112
72/* STM32F7 I2C Interrupt Status */ 113/* STM32F7 I2C Interrupt Status */
114#define STM32F7_I2C_ISR_ADDCODE_MASK GENMASK(23, 17)
115#define STM32F7_I2C_ISR_ADDCODE_GET(n) \
116 (((n) & STM32F7_I2C_ISR_ADDCODE_MASK) >> 17)
117#define STM32F7_I2C_ISR_DIR BIT(16)
73#define STM32F7_I2C_ISR_BUSY BIT(15) 118#define STM32F7_I2C_ISR_BUSY BIT(15)
119#define STM32F7_I2C_ISR_PECERR BIT(11)
74#define STM32F7_I2C_ISR_ARLO BIT(9) 120#define STM32F7_I2C_ISR_ARLO BIT(9)
75#define STM32F7_I2C_ISR_BERR BIT(8) 121#define STM32F7_I2C_ISR_BERR BIT(8)
76#define STM32F7_I2C_ISR_TCR BIT(7) 122#define STM32F7_I2C_ISR_TCR BIT(7)
77#define STM32F7_I2C_ISR_TC BIT(6) 123#define STM32F7_I2C_ISR_TC BIT(6)
78#define STM32F7_I2C_ISR_STOPF BIT(5) 124#define STM32F7_I2C_ISR_STOPF BIT(5)
79#define STM32F7_I2C_ISR_NACKF BIT(4) 125#define STM32F7_I2C_ISR_NACKF BIT(4)
126#define STM32F7_I2C_ISR_ADDR BIT(3)
80#define STM32F7_I2C_ISR_RXNE BIT(2) 127#define STM32F7_I2C_ISR_RXNE BIT(2)
81#define STM32F7_I2C_ISR_TXIS BIT(1) 128#define STM32F7_I2C_ISR_TXIS BIT(1)
129#define STM32F7_I2C_ISR_TXE BIT(0)
82 130
83/* STM32F7 I2C Interrupt Clear */ 131/* STM32F7 I2C Interrupt Clear */
132#define STM32F7_I2C_ICR_PECCF BIT(11)
84#define STM32F7_I2C_ICR_ARLOCF BIT(9) 133#define STM32F7_I2C_ICR_ARLOCF BIT(9)
85#define STM32F7_I2C_ICR_BERRCF BIT(8) 134#define STM32F7_I2C_ICR_BERRCF BIT(8)
86#define STM32F7_I2C_ICR_STOPCF BIT(5) 135#define STM32F7_I2C_ICR_STOPCF BIT(5)
87#define STM32F7_I2C_ICR_NACKCF BIT(4) 136#define STM32F7_I2C_ICR_NACKCF BIT(4)
137#define STM32F7_I2C_ICR_ADDRCF BIT(3)
88 138
89/* STM32F7 I2C Timing */ 139/* STM32F7 I2C Timing */
90#define STM32F7_I2C_TIMINGR_PRESC(n) (((n) & 0xf) << 28) 140#define STM32F7_I2C_TIMINGR_PRESC(n) (((n) & 0xf) << 28)
@@ -94,6 +144,8 @@
94#define STM32F7_I2C_TIMINGR_SCLL(n) ((n) & 0xff) 144#define STM32F7_I2C_TIMINGR_SCLL(n) ((n) & 0xff)
95 145
96#define STM32F7_I2C_MAX_LEN 0xff 146#define STM32F7_I2C_MAX_LEN 0xff
147#define STM32F7_I2C_DMA_LEN_MIN 0x16
148#define STM32F7_I2C_MAX_SLAVE 0x2
97 149
98#define STM32F7_I2C_DNF_DEFAULT 0 150#define STM32F7_I2C_DNF_DEFAULT 0
99#define STM32F7_I2C_DNF_MAX 16 151#define STM32F7_I2C_DNF_MAX 16
@@ -159,11 +211,12 @@ struct stm32f7_i2c_setup {
159 211
160/** 212/**
161 * struct stm32f7_i2c_timings - private I2C output parameters 213 * struct stm32f7_i2c_timings - private I2C output parameters
162 * @prec: Prescaler value 214 * @node: List entry
215 * @presc: Prescaler value
163 * @scldel: Data setup time 216 * @scldel: Data setup time
164 * @sdadel: Data hold time 217 * @sdadel: Data hold time
165 * @sclh: SCL high period (master mode) 218 * @sclh: SCL high period (master mode)
166 * @sclh: SCL low period (master mode) 219 * @scll: SCL low period (master mode)
167 */ 220 */
168struct stm32f7_i2c_timings { 221struct stm32f7_i2c_timings {
169 struct list_head node; 222 struct list_head node;
@@ -176,18 +229,30 @@ struct stm32f7_i2c_timings {
176 229
177/** 230/**
178 * struct stm32f7_i2c_msg - client specific data 231 * struct stm32f7_i2c_msg - client specific data
179 * @addr: 8-bit slave addr, including r/w bit 232 * @addr: 8-bit or 10-bit slave addr, including r/w bit
180 * @count: number of bytes to be transferred 233 * @count: number of bytes to be transferred
181 * @buf: data buffer 234 * @buf: data buffer
182 * @result: result of the transfer 235 * @result: result of the transfer
183 * @stop: last I2C msg to be sent, i.e. STOP to be generated 236 * @stop: last I2C msg to be sent, i.e. STOP to be generated
237 * @smbus: boolean to know if the I2C IP is used in SMBus mode
238 * @size: type of SMBus protocol
239 * @read_write: direction of SMBus protocol
240 * SMBus block read and SMBus block write - block read process call protocols
241 * @smbus_buf: buffer to be used for SMBus protocol transfer. It will
242 * contain a maximum of 32 bytes of data + byte command + byte count + PEC
243 * This buffer has to be 32-bit aligned to be compliant with memory address
244 * register in DMA mode.
184 */ 245 */
185struct stm32f7_i2c_msg { 246struct stm32f7_i2c_msg {
186 u8 addr; 247 u16 addr;
187 u32 count; 248 u32 count;
188 u8 *buf; 249 u8 *buf;
189 int result; 250 int result;
190 bool stop; 251 bool stop;
252 bool smbus;
253 int size;
254 char read_write;
255 u8 smbus_buf[I2C_SMBUS_BLOCK_MAX + 3] __aligned(4);
191}; 256};
192 257
193/** 258/**
@@ -204,6 +269,13 @@ struct stm32f7_i2c_msg {
204 * @f7_msg: customized i2c msg for driver usage 269 * @f7_msg: customized i2c msg for driver usage
205 * @setup: I2C timing input setup 270 * @setup: I2C timing input setup
206 * @timing: I2C computed timings 271 * @timing: I2C computed timings
272 * @slave: list of slave devices registered on the I2C bus
273 * @slave_running: slave device currently used
274 * @slave_dir: transfer direction for the current slave device
275 * @master_mode: boolean to know in which mode the I2C is running (master or
276 * slave)
277 * @dma: dma data
278 * @use_dma: boolean to know if dma is used in the current transfer
207 */ 279 */
208struct stm32f7_i2c_dev { 280struct stm32f7_i2c_dev {
209 struct i2c_adapter adap; 281 struct i2c_adapter adap;
@@ -218,6 +290,12 @@ struct stm32f7_i2c_dev {
218 struct stm32f7_i2c_msg f7_msg; 290 struct stm32f7_i2c_msg f7_msg;
219 struct stm32f7_i2c_setup setup; 291 struct stm32f7_i2c_setup setup;
220 struct stm32f7_i2c_timings timing; 292 struct stm32f7_i2c_timings timing;
293 struct i2c_client *slave[STM32F7_I2C_MAX_SLAVE];
294 struct i2c_client *slave_running;
295 u32 slave_dir;
296 bool master_mode;
297 struct stm32_i2c_dma *dma;
298 bool use_dma;
221}; 299};
222 300
223/** 301/**
@@ -283,6 +361,11 @@ static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask)
283 writel_relaxed(readl_relaxed(reg) & ~mask, reg); 361 writel_relaxed(readl_relaxed(reg) & ~mask, reg);
284} 362}
285 363
364static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask)
365{
366 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask);
367}
368
286static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev, 369static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev,
287 struct stm32f7_i2c_setup *setup, 370 struct stm32f7_i2c_setup *setup,
288 struct stm32f7_i2c_timings *output) 371 struct stm32f7_i2c_timings *output)
@@ -524,6 +607,25 @@ static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev,
524 return 0; 607 return 0;
525} 608}
526 609
610static void stm32f7_i2c_disable_dma_req(struct stm32f7_i2c_dev *i2c_dev)
611{
612 void __iomem *base = i2c_dev->base;
613 u32 mask = STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN;
614
615 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
616}
617
618static void stm32f7_i2c_dma_callback(void *arg)
619{
620 struct stm32f7_i2c_dev *i2c_dev = (struct stm32f7_i2c_dev *)arg;
621 struct stm32_i2c_dma *dma = i2c_dev->dma;
622 struct device *dev = dma->chan_using->device->dev;
623
624 stm32f7_i2c_disable_dma_req(i2c_dev);
625 dma_unmap_single(dev, dma->dma_buf, dma->dma_len, dma->dma_data_dir);
626 complete(&dma->dma_complete);
627}
628
527static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev) 629static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev)
528{ 630{
529 struct stm32f7_i2c_timings *t = &i2c_dev->timing; 631 struct stm32f7_i2c_timings *t = &i2c_dev->timing;
@@ -567,6 +669,9 @@ static void stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev)
567 if (f7_msg->count) { 669 if (f7_msg->count) {
568 *f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR); 670 *f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR);
569 f7_msg->count--; 671 f7_msg->count--;
672 } else {
673 /* Flush RX buffer has no data is expected */
674 readb_relaxed(base + STM32F7_I2C_RXDR);
570 } 675 }
571} 676}
572 677
@@ -575,6 +680,9 @@ static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev)
575 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 680 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
576 u32 cr2; 681 u32 cr2;
577 682
683 if (i2c_dev->use_dma)
684 f7_msg->count -= STM32F7_I2C_MAX_LEN;
685
578 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); 686 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
579 687
580 cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK; 688 cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK;
@@ -588,6 +696,43 @@ static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev)
588 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); 696 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
589} 697}
590 698
699static void stm32f7_i2c_smbus_reload(struct stm32f7_i2c_dev *i2c_dev)
700{
701 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
702 u32 cr2;
703 u8 *val;
704
705 /*
706 * For I2C_SMBUS_BLOCK_DATA && I2C_SMBUS_BLOCK_PROC_CALL, the first
707 * data received inform us how many data will follow.
708 */
709 stm32f7_i2c_read_rx_data(i2c_dev);
710
711 /*
712 * Update NBYTES with the value read to continue the transfer
713 */
714 val = f7_msg->buf - sizeof(u8);
715 f7_msg->count = *val;
716 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
717 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
718 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
719 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
720}
721
722static int stm32f7_i2c_release_bus(struct i2c_adapter *i2c_adap)
723{
724 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
725
726 dev_info(i2c_dev->dev, "Trying to recover bus\n");
727
728 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
729 STM32F7_I2C_CR1_PE);
730
731 stm32f7_i2c_hw_config(i2c_dev);
732
733 return 0;
734}
735
591static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev) 736static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev)
592{ 737{
593 u32 status; 738 u32 status;
@@ -597,12 +742,18 @@ static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev)
597 status, 742 status,
598 !(status & STM32F7_I2C_ISR_BUSY), 743 !(status & STM32F7_I2C_ISR_BUSY),
599 10, 1000); 744 10, 1000);
745 if (!ret)
746 return 0;
747
748 dev_info(i2c_dev->dev, "bus busy\n");
749
750 ret = stm32f7_i2c_release_bus(&i2c_dev->adap);
600 if (ret) { 751 if (ret) {
601 dev_dbg(i2c_dev->dev, "bus busy\n"); 752 dev_err(i2c_dev->dev, "Failed to recover the bus (%d)\n", ret);
602 ret = -EBUSY; 753 return ret;
603 } 754 }
604 755
605 return ret; 756 return -EBUSY;
606} 757}
607 758
608static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev, 759static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
@@ -611,6 +762,7 @@ static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
611 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 762 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
612 void __iomem *base = i2c_dev->base; 763 void __iomem *base = i2c_dev->base;
613 u32 cr1, cr2; 764 u32 cr1, cr2;
765 int ret;
614 766
615 f7_msg->addr = msg->addr; 767 f7_msg->addr = msg->addr;
616 f7_msg->buf = msg->buf; 768 f7_msg->buf = msg->buf;
@@ -629,8 +781,15 @@ static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
629 cr2 |= STM32F7_I2C_CR2_RD_WRN; 781 cr2 |= STM32F7_I2C_CR2_RD_WRN;
630 782
631 /* Set slave address */ 783 /* Set slave address */
632 cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK; 784 cr2 &= ~(STM32F7_I2C_CR2_HEAD10R | STM32F7_I2C_CR2_ADD10);
633 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr); 785 if (msg->flags & I2C_M_TEN) {
786 cr2 &= ~STM32F7_I2C_CR2_SADD10_MASK;
787 cr2 |= STM32F7_I2C_CR2_SADD10(f7_msg->addr);
788 cr2 |= STM32F7_I2C_CR2_ADD10;
789 } else {
790 cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK;
791 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
792 }
634 793
635 /* Set nb bytes to transfer and reload if needed */ 794 /* Set nb bytes to transfer and reload if needed */
636 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD); 795 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
@@ -645,16 +804,286 @@ static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
645 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE | 804 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
646 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE; 805 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
647 806
648 /* Clear TX/RX interrupt */ 807 /* Clear DMA req and TX/RX interrupt */
808 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
809 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
810
811 /* Configure DMA or enable RX/TX interrupt */
812 i2c_dev->use_dma = false;
813 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
814 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
815 msg->flags & I2C_M_RD,
816 f7_msg->count, f7_msg->buf,
817 stm32f7_i2c_dma_callback,
818 i2c_dev);
819 if (!ret)
820 i2c_dev->use_dma = true;
821 else
822 dev_warn(i2c_dev->dev, "can't use DMA\n");
823 }
824
825 if (!i2c_dev->use_dma) {
826 if (msg->flags & I2C_M_RD)
827 cr1 |= STM32F7_I2C_CR1_RXIE;
828 else
829 cr1 |= STM32F7_I2C_CR1_TXIE;
830 } else {
831 if (msg->flags & I2C_M_RD)
832 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
833 else
834 cr1 |= STM32F7_I2C_CR1_TXDMAEN;
835 }
836
837 /* Configure Start/Repeated Start */
838 cr2 |= STM32F7_I2C_CR2_START;
839
840 i2c_dev->master_mode = true;
841
842 /* Write configurations registers */
843 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
844 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
845}
846
847static int stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
848 unsigned short flags, u8 command,
849 union i2c_smbus_data *data)
850{
851 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
852 struct device *dev = i2c_dev->dev;
853 void __iomem *base = i2c_dev->base;
854 u32 cr1, cr2;
855 int i, ret;
856
857 f7_msg->result = 0;
858 reinit_completion(&i2c_dev->complete);
859
860 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
861 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
862
863 /* Set transfer direction */
864 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
865 if (f7_msg->read_write)
866 cr2 |= STM32F7_I2C_CR2_RD_WRN;
867
868 /* Set slave address */
869 cr2 &= ~(STM32F7_I2C_CR2_ADD10 | STM32F7_I2C_CR2_SADD7_MASK);
870 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
871
872 f7_msg->smbus_buf[0] = command;
873 switch (f7_msg->size) {
874 case I2C_SMBUS_QUICK:
875 f7_msg->stop = true;
876 f7_msg->count = 0;
877 break;
878 case I2C_SMBUS_BYTE:
879 f7_msg->stop = true;
880 f7_msg->count = 1;
881 break;
882 case I2C_SMBUS_BYTE_DATA:
883 if (f7_msg->read_write) {
884 f7_msg->stop = false;
885 f7_msg->count = 1;
886 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
887 } else {
888 f7_msg->stop = true;
889 f7_msg->count = 2;
890 f7_msg->smbus_buf[1] = data->byte;
891 }
892 break;
893 case I2C_SMBUS_WORD_DATA:
894 if (f7_msg->read_write) {
895 f7_msg->stop = false;
896 f7_msg->count = 1;
897 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
898 } else {
899 f7_msg->stop = true;
900 f7_msg->count = 3;
901 f7_msg->smbus_buf[1] = data->word & 0xff;
902 f7_msg->smbus_buf[2] = data->word >> 8;
903 }
904 break;
905 case I2C_SMBUS_BLOCK_DATA:
906 if (f7_msg->read_write) {
907 f7_msg->stop = false;
908 f7_msg->count = 1;
909 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
910 } else {
911 f7_msg->stop = true;
912 if (data->block[0] > I2C_SMBUS_BLOCK_MAX ||
913 !data->block[0]) {
914 dev_err(dev, "Invalid block write size %d\n",
915 data->block[0]);
916 return -EINVAL;
917 }
918 f7_msg->count = data->block[0] + 2;
919 for (i = 1; i < f7_msg->count; i++)
920 f7_msg->smbus_buf[i] = data->block[i - 1];
921 }
922 break;
923 case I2C_SMBUS_PROC_CALL:
924 f7_msg->stop = false;
925 f7_msg->count = 3;
926 f7_msg->smbus_buf[1] = data->word & 0xff;
927 f7_msg->smbus_buf[2] = data->word >> 8;
928 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
929 f7_msg->read_write = I2C_SMBUS_READ;
930 break;
931 case I2C_SMBUS_BLOCK_PROC_CALL:
932 f7_msg->stop = false;
933 if (data->block[0] > I2C_SMBUS_BLOCK_MAX - 1) {
934 dev_err(dev, "Invalid block write size %d\n",
935 data->block[0]);
936 return -EINVAL;
937 }
938 f7_msg->count = data->block[0] + 2;
939 for (i = 1; i < f7_msg->count; i++)
940 f7_msg->smbus_buf[i] = data->block[i - 1];
941 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
942 f7_msg->read_write = I2C_SMBUS_READ;
943 break;
944 default:
945 dev_err(dev, "Unsupported smbus protocol %d\n", f7_msg->size);
946 return -EOPNOTSUPP;
947 }
948
949 f7_msg->buf = f7_msg->smbus_buf;
950
951 /* Configure PEC */
952 if ((flags & I2C_CLIENT_PEC) && f7_msg->size != I2C_SMBUS_QUICK) {
953 cr1 |= STM32F7_I2C_CR1_PECEN;
954 cr2 |= STM32F7_I2C_CR2_PECBYTE;
955 if (!f7_msg->read_write)
956 f7_msg->count++;
957 } else {
958 cr1 &= ~STM32F7_I2C_CR1_PECEN;
959 cr2 &= ~STM32F7_I2C_CR2_PECBYTE;
960 }
961
962 /* Set number of bytes to be transferred */
963 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
964 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
965
966 /* Enable NACK, STOP, error and transfer complete interrupts */
967 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
968 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
969
970 /* Clear DMA req and TX/RX interrupt */
971 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
972 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
973
974 /* Configure DMA or enable RX/TX interrupt */
975 i2c_dev->use_dma = false;
976 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
977 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
978 cr2 & STM32F7_I2C_CR2_RD_WRN,
979 f7_msg->count, f7_msg->buf,
980 stm32f7_i2c_dma_callback,
981 i2c_dev);
982 if (!ret)
983 i2c_dev->use_dma = true;
984 else
985 dev_warn(i2c_dev->dev, "can't use DMA\n");
986 }
987
988 if (!i2c_dev->use_dma) {
989 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
990 cr1 |= STM32F7_I2C_CR1_RXIE;
991 else
992 cr1 |= STM32F7_I2C_CR1_TXIE;
993 } else {
994 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
995 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
996 else
997 cr1 |= STM32F7_I2C_CR1_TXDMAEN;
998 }
999
1000 /* Set Start bit */
1001 cr2 |= STM32F7_I2C_CR2_START;
1002
1003 i2c_dev->master_mode = true;
1004
1005 /* Write configurations registers */
1006 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1007 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1008
1009 return 0;
1010}
1011
1012static void stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev *i2c_dev)
1013{
1014 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1015 void __iomem *base = i2c_dev->base;
1016 u32 cr1, cr2;
1017 int ret;
1018
1019 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
1020 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
1021
1022 /* Set transfer direction */
1023 cr2 |= STM32F7_I2C_CR2_RD_WRN;
1024
1025 switch (f7_msg->size) {
1026 case I2C_SMBUS_BYTE_DATA:
1027 f7_msg->count = 1;
1028 break;
1029 case I2C_SMBUS_WORD_DATA:
1030 case I2C_SMBUS_PROC_CALL:
1031 f7_msg->count = 2;
1032 break;
1033 case I2C_SMBUS_BLOCK_DATA:
1034 case I2C_SMBUS_BLOCK_PROC_CALL:
1035 f7_msg->count = 1;
1036 cr2 |= STM32F7_I2C_CR2_RELOAD;
1037 break;
1038 }
1039
1040 f7_msg->buf = f7_msg->smbus_buf;
1041 f7_msg->stop = true;
1042
1043 /* Add one byte for PEC if needed */
1044 if (cr1 & STM32F7_I2C_CR1_PECEN)
1045 f7_msg->count++;
1046
1047 /* Set number of bytes to be transferred */
1048 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK);
1049 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1050
1051 /*
1052 * Configure RX/TX interrupt:
1053 */
649 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE); 1054 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE);
1055 cr1 |= STM32F7_I2C_CR1_RXIE;
650 1056
651 /* Enable RX/TX interrupt according to msg direction */ 1057 /*
652 if (msg->flags & I2C_M_RD) 1058 * Configure DMA or enable RX/TX interrupt:
1059 * For I2C_SMBUS_BLOCK_DATA and I2C_SMBUS_BLOCK_PROC_CALL we don't use
1060 * dma as we don't know in advance how many data will be received
1061 */
1062 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1063 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
1064
1065 i2c_dev->use_dma = false;
1066 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN &&
1067 f7_msg->size != I2C_SMBUS_BLOCK_DATA &&
1068 f7_msg->size != I2C_SMBUS_BLOCK_PROC_CALL) {
1069 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
1070 cr2 & STM32F7_I2C_CR2_RD_WRN,
1071 f7_msg->count, f7_msg->buf,
1072 stm32f7_i2c_dma_callback,
1073 i2c_dev);
1074
1075 if (!ret)
1076 i2c_dev->use_dma = true;
1077 else
1078 dev_warn(i2c_dev->dev, "can't use DMA\n");
1079 }
1080
1081 if (!i2c_dev->use_dma)
653 cr1 |= STM32F7_I2C_CR1_RXIE; 1082 cr1 |= STM32F7_I2C_CR1_RXIE;
654 else 1083 else
655 cr1 |= STM32F7_I2C_CR1_TXIE; 1084 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
656 1085
657 /* Configure Start/Repeated Start */ 1086 /* Configure Repeated Start */
658 cr2 |= STM32F7_I2C_CR2_START; 1087 cr2 |= STM32F7_I2C_CR2_START;
659 1088
660 /* Write configurations registers */ 1089 /* Write configurations registers */
@@ -662,9 +1091,278 @@ static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
662 writel_relaxed(cr2, base + STM32F7_I2C_CR2); 1091 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
663} 1092}
664 1093
665static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask) 1094static int stm32f7_i2c_smbus_check_pec(struct stm32f7_i2c_dev *i2c_dev)
666{ 1095{
667 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask); 1096 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1097 u8 count, internal_pec, received_pec;
1098
1099 internal_pec = readl_relaxed(i2c_dev->base + STM32F7_I2C_PECR);
1100
1101 switch (f7_msg->size) {
1102 case I2C_SMBUS_BYTE:
1103 case I2C_SMBUS_BYTE_DATA:
1104 received_pec = f7_msg->smbus_buf[1];
1105 break;
1106 case I2C_SMBUS_WORD_DATA:
1107 case I2C_SMBUS_PROC_CALL:
1108 received_pec = f7_msg->smbus_buf[2];
1109 break;
1110 case I2C_SMBUS_BLOCK_DATA:
1111 case I2C_SMBUS_BLOCK_PROC_CALL:
1112 count = f7_msg->smbus_buf[0];
1113 received_pec = f7_msg->smbus_buf[count];
1114 break;
1115 default:
1116 dev_err(i2c_dev->dev, "Unsupported smbus protocol for PEC\n");
1117 return -EINVAL;
1118 }
1119
1120 if (internal_pec != received_pec) {
1121 dev_err(i2c_dev->dev, "Bad PEC 0x%02x vs. 0x%02x\n",
1122 internal_pec, received_pec);
1123 return -EBADMSG;
1124 }
1125
1126 return 0;
1127}
1128
1129static bool stm32f7_i2c_is_addr_match(struct i2c_client *slave, u32 addcode)
1130{
1131 u32 addr;
1132
1133 if (!slave)
1134 return false;
1135
1136 if (slave->flags & I2C_CLIENT_TEN) {
1137 /*
1138 * For 10-bit addr, addcode = 11110XY with
1139 * X = Bit 9 of slave address
1140 * Y = Bit 8 of slave address
1141 */
1142 addr = slave->addr >> 8;
1143 addr |= 0x78;
1144 if (addr == addcode)
1145 return true;
1146 } else {
1147 addr = slave->addr & 0x7f;
1148 if (addr == addcode)
1149 return true;
1150 }
1151
1152 return false;
1153}
1154
1155static void stm32f7_i2c_slave_start(struct stm32f7_i2c_dev *i2c_dev)
1156{
1157 struct i2c_client *slave = i2c_dev->slave_running;
1158 void __iomem *base = i2c_dev->base;
1159 u32 mask;
1160 u8 value = 0;
1161
1162 if (i2c_dev->slave_dir) {
1163 /* Notify i2c slave that new read transfer is starting */
1164 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
1165
1166 /*
1167 * Disable slave TX config in case of I2C combined message
1168 * (I2C Write followed by I2C Read)
1169 */
1170 mask = STM32F7_I2C_CR2_RELOAD;
1171 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, mask);
1172 mask = STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1173 STM32F7_I2C_CR1_TCIE;
1174 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
1175
1176 /* Enable TX empty, STOP, NACK interrupts */
1177 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1178 STM32F7_I2C_CR1_TXIE;
1179 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1180
1181 } else {
1182 /* Notify i2c slave that new write transfer is starting */
1183 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
1184
1185 /* Set reload mode to be able to ACK/NACK each received byte */
1186 mask = STM32F7_I2C_CR2_RELOAD;
1187 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1188
1189 /*
1190 * Set STOP, NACK, RX empty and transfer complete interrupts.*
1191 * Set Slave Byte Control to be able to ACK/NACK each data
1192 * byte received
1193 */
1194 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1195 STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1196 STM32F7_I2C_CR1_TCIE;
1197 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1198 }
1199}
1200
1201static void stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev *i2c_dev)
1202{
1203 void __iomem *base = i2c_dev->base;
1204 u32 isr, addcode, dir, mask;
1205 int i;
1206
1207 isr = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1208 addcode = STM32F7_I2C_ISR_ADDCODE_GET(isr);
1209 dir = isr & STM32F7_I2C_ISR_DIR;
1210
1211 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1212 if (stm32f7_i2c_is_addr_match(i2c_dev->slave[i], addcode)) {
1213 i2c_dev->slave_running = i2c_dev->slave[i];
1214 i2c_dev->slave_dir = dir;
1215
1216 /* Start I2C slave processing */
1217 stm32f7_i2c_slave_start(i2c_dev);
1218
1219 /* Clear ADDR flag */
1220 mask = STM32F7_I2C_ICR_ADDRCF;
1221 writel_relaxed(mask, base + STM32F7_I2C_ICR);
1222 break;
1223 }
1224 }
1225}
1226
1227static int stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1228 struct i2c_client *slave, int *id)
1229{
1230 int i;
1231
1232 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1233 if (i2c_dev->slave[i] == slave) {
1234 *id = i;
1235 return 0;
1236 }
1237 }
1238
1239 dev_err(i2c_dev->dev, "Slave 0x%x not registered\n", slave->addr);
1240
1241 return -ENODEV;
1242}
1243
1244static int stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1245 struct i2c_client *slave, int *id)
1246{
1247 struct device *dev = i2c_dev->dev;
1248 int i;
1249
1250 /*
1251 * slave[0] supports 7-bit and 10-bit slave address
1252 * slave[1] supports 7-bit slave address only
1253 */
1254 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1255 if (i == 1 && (slave->flags & I2C_CLIENT_PEC))
1256 continue;
1257 if (!i2c_dev->slave[i]) {
1258 *id = i;
1259 return 0;
1260 }
1261 }
1262
1263 dev_err(dev, "Slave 0x%x could not be registered\n", slave->addr);
1264
1265 return -EINVAL;
1266}
1267
1268static bool stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev *i2c_dev)
1269{
1270 int i;
1271
1272 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1273 if (i2c_dev->slave[i])
1274 return true;
1275 }
1276
1277 return false;
1278}
1279
1280static bool stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev *i2c_dev)
1281{
1282 int i, busy;
1283
1284 busy = 0;
1285 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1286 if (i2c_dev->slave[i])
1287 busy++;
1288 }
1289
1290 return i == busy;
1291}
1292
1293static irqreturn_t stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev *i2c_dev)
1294{
1295 void __iomem *base = i2c_dev->base;
1296 u32 cr2, status, mask;
1297 u8 val;
1298 int ret;
1299
1300 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1301
1302 /* Slave transmitter mode */
1303 if (status & STM32F7_I2C_ISR_TXIS) {
1304 i2c_slave_event(i2c_dev->slave_running,
1305 I2C_SLAVE_READ_PROCESSED,
1306 &val);
1307
1308 /* Write data byte */
1309 writel_relaxed(val, base + STM32F7_I2C_TXDR);
1310 }
1311
1312 /* Transfer Complete Reload for Slave receiver mode */
1313 if (status & STM32F7_I2C_ISR_TCR || status & STM32F7_I2C_ISR_RXNE) {
1314 /*
1315 * Read data byte then set NBYTES to receive next byte or NACK
1316 * the current received byte
1317 */
1318 val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR);
1319 ret = i2c_slave_event(i2c_dev->slave_running,
1320 I2C_SLAVE_WRITE_RECEIVED,
1321 &val);
1322 if (!ret) {
1323 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
1324 cr2 |= STM32F7_I2C_CR2_NBYTES(1);
1325 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
1326 } else {
1327 mask = STM32F7_I2C_CR2_NACK;
1328 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1329 }
1330 }
1331
1332 /* NACK received */
1333 if (status & STM32F7_I2C_ISR_NACKF) {
1334 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__);
1335 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1336 }
1337
1338 /* STOP received */
1339 if (status & STM32F7_I2C_ISR_STOPF) {
1340 /* Disable interrupts */
1341 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_XFER_IRQ_MASK);
1342
1343 if (i2c_dev->slave_dir) {
1344 /*
1345 * Flush TX buffer in order to not used the byte in
1346 * TXDR for the next transfer
1347 */
1348 mask = STM32F7_I2C_ISR_TXE;
1349 stm32f7_i2c_set_bits(base + STM32F7_I2C_ISR, mask);
1350 }
1351
1352 /* Clear STOP flag */
1353 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1354
1355 /* Notify i2c slave that a STOP flag has been detected */
1356 i2c_slave_event(i2c_dev->slave_running, I2C_SLAVE_STOP, &val);
1357
1358 i2c_dev->slave_running = NULL;
1359 }
1360
1361 /* Address match received */
1362 if (status & STM32F7_I2C_ISR_ADDR)
1363 stm32f7_i2c_slave_addr(i2c_dev);
1364
1365 return IRQ_HANDLED;
668} 1366}
669 1367
670static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data) 1368static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)
@@ -673,6 +1371,13 @@ static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)
673 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1371 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
674 void __iomem *base = i2c_dev->base; 1372 void __iomem *base = i2c_dev->base;
675 u32 status, mask; 1373 u32 status, mask;
1374 int ret = IRQ_HANDLED;
1375
1376 /* Check if the interrupt if for a slave device */
1377 if (!i2c_dev->master_mode) {
1378 ret = stm32f7_i2c_slave_isr_event(i2c_dev);
1379 return ret;
1380 }
676 1381
677 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1382 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
678 1383
@@ -694,12 +1399,21 @@ static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)
694 /* STOP detection flag */ 1399 /* STOP detection flag */
695 if (status & STM32F7_I2C_ISR_STOPF) { 1400 if (status & STM32F7_I2C_ISR_STOPF) {
696 /* Disable interrupts */ 1401 /* Disable interrupts */
697 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK); 1402 if (stm32f7_i2c_is_slave_registered(i2c_dev))
1403 mask = STM32F7_I2C_XFER_IRQ_MASK;
1404 else
1405 mask = STM32F7_I2C_ALL_IRQ_MASK;
1406 stm32f7_i2c_disable_irq(i2c_dev, mask);
698 1407
699 /* Clear STOP flag */ 1408 /* Clear STOP flag */
700 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR); 1409 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
701 1410
702 complete(&i2c_dev->complete); 1411 if (i2c_dev->use_dma) {
1412 ret = IRQ_WAKE_THREAD;
1413 } else {
1414 i2c_dev->master_mode = false;
1415 complete(&i2c_dev->complete);
1416 }
703 } 1417 }
704 1418
705 /* Transfer complete */ 1419 /* Transfer complete */
@@ -707,6 +1421,10 @@ static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)
707 if (f7_msg->stop) { 1421 if (f7_msg->stop) {
708 mask = STM32F7_I2C_CR2_STOP; 1422 mask = STM32F7_I2C_CR2_STOP;
709 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask); 1423 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1424 } else if (i2c_dev->use_dma) {
1425 ret = IRQ_WAKE_THREAD;
1426 } else if (f7_msg->smbus) {
1427 stm32f7_i2c_smbus_rep_start(i2c_dev);
710 } else { 1428 } else {
711 i2c_dev->msg_id++; 1429 i2c_dev->msg_id++;
712 i2c_dev->msg++; 1430 i2c_dev->msg++;
@@ -714,13 +1432,50 @@ static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)
714 } 1432 }
715 } 1433 }
716 1434
1435 if (status & STM32F7_I2C_ISR_TCR) {
1436 if (f7_msg->smbus)
1437 stm32f7_i2c_smbus_reload(i2c_dev);
1438 else
1439 stm32f7_i2c_reload(i2c_dev);
1440 }
1441
1442 return ret;
1443}
1444
1445static irqreturn_t stm32f7_i2c_isr_event_thread(int irq, void *data)
1446{
1447 struct stm32f7_i2c_dev *i2c_dev = data;
1448 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1449 struct stm32_i2c_dma *dma = i2c_dev->dma;
1450 u32 status;
1451 int ret;
1452
717 /* 1453 /*
718 * Transfer Complete Reload: 255 data bytes have been transferred 1454 * Wait for dma transfer completion before sending next message or
719 * We have to prepare the I2C controller to transfer the remaining 1455 * notity the end of xfer to the client
720 * data.
721 */ 1456 */
722 if (status & STM32F7_I2C_ISR_TCR) 1457 ret = wait_for_completion_timeout(&i2c_dev->dma->dma_complete, HZ);
723 stm32f7_i2c_reload(i2c_dev); 1458 if (!ret) {
1459 dev_dbg(i2c_dev->dev, "<%s>: Timed out\n", __func__);
1460 stm32f7_i2c_disable_dma_req(i2c_dev);
1461 dmaengine_terminate_all(dma->chan_using);
1462 f7_msg->result = -ETIMEDOUT;
1463 }
1464
1465 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1466
1467 if (status & STM32F7_I2C_ISR_TC) {
1468 if (f7_msg->smbus) {
1469 stm32f7_i2c_smbus_rep_start(i2c_dev);
1470 } else {
1471 i2c_dev->msg_id++;
1472 i2c_dev->msg++;
1473 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1474 }
1475 } else {
1476 i2c_dev->master_mode = false;
1477 complete(&i2c_dev->complete);
1478 }
724 1479
725 return IRQ_HANDLED; 1480 return IRQ_HANDLED;
726} 1481}
@@ -731,7 +1486,8 @@ static irqreturn_t stm32f7_i2c_isr_error(int irq, void *data)
731 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1486 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
732 void __iomem *base = i2c_dev->base; 1487 void __iomem *base = i2c_dev->base;
733 struct device *dev = i2c_dev->dev; 1488 struct device *dev = i2c_dev->dev;
734 u32 status; 1489 struct stm32_i2c_dma *dma = i2c_dev->dma;
1490 u32 mask, status;
735 1491
736 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1492 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
737 1493
@@ -739,6 +1495,7 @@ static irqreturn_t stm32f7_i2c_isr_error(int irq, void *data)
739 if (status & STM32F7_I2C_ISR_BERR) { 1495 if (status & STM32F7_I2C_ISR_BERR) {
740 dev_err(dev, "<%s>: Bus error\n", __func__); 1496 dev_err(dev, "<%s>: Bus error\n", __func__);
741 writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR); 1497 writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR);
1498 stm32f7_i2c_release_bus(&i2c_dev->adap);
742 f7_msg->result = -EIO; 1499 f7_msg->result = -EIO;
743 } 1500 }
744 1501
@@ -749,8 +1506,26 @@ static irqreturn_t stm32f7_i2c_isr_error(int irq, void *data)
749 f7_msg->result = -EAGAIN; 1506 f7_msg->result = -EAGAIN;
750 } 1507 }
751 1508
752 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK); 1509 if (status & STM32F7_I2C_ISR_PECERR) {
1510 dev_err(dev, "<%s>: PEC error in reception\n", __func__);
1511 writel_relaxed(STM32F7_I2C_ICR_PECCF, base + STM32F7_I2C_ICR);
1512 f7_msg->result = -EINVAL;
1513 }
1514
1515 /* Disable interrupts */
1516 if (stm32f7_i2c_is_slave_registered(i2c_dev))
1517 mask = STM32F7_I2C_XFER_IRQ_MASK;
1518 else
1519 mask = STM32F7_I2C_ALL_IRQ_MASK;
1520 stm32f7_i2c_disable_irq(i2c_dev, mask);
1521
1522 /* Disable dma */
1523 if (i2c_dev->use_dma) {
1524 stm32f7_i2c_disable_dma_req(i2c_dev);
1525 dmaengine_terminate_all(dma->chan_using);
1526 }
753 1527
1528 i2c_dev->master_mode = false;
754 complete(&i2c_dev->complete); 1529 complete(&i2c_dev->complete);
755 1530
756 return IRQ_HANDLED; 1531 return IRQ_HANDLED;
@@ -761,12 +1536,14 @@ static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap,
761{ 1536{
762 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap); 1537 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
763 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1538 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1539 struct stm32_i2c_dma *dma = i2c_dev->dma;
764 unsigned long time_left; 1540 unsigned long time_left;
765 int ret; 1541 int ret;
766 1542
767 i2c_dev->msg = msgs; 1543 i2c_dev->msg = msgs;
768 i2c_dev->msg_num = num; 1544 i2c_dev->msg_num = num;
769 i2c_dev->msg_id = 0; 1545 i2c_dev->msg_id = 0;
1546 f7_msg->smbus = false;
770 1547
771 ret = clk_enable(i2c_dev->clk); 1548 ret = clk_enable(i2c_dev->clk);
772 if (ret) { 1549 if (ret) {
@@ -787,6 +1564,8 @@ static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap,
787 if (!time_left) { 1564 if (!time_left) {
788 dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n", 1565 dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n",
789 i2c_dev->msg->addr); 1566 i2c_dev->msg->addr);
1567 if (i2c_dev->use_dma)
1568 dmaengine_terminate_all(dma->chan_using);
790 ret = -ETIMEDOUT; 1569 ret = -ETIMEDOUT;
791 } 1570 }
792 1571
@@ -796,14 +1575,209 @@ clk_free:
796 return (ret < 0) ? ret : num; 1575 return (ret < 0) ? ret : num;
797} 1576}
798 1577
1578static int stm32f7_i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr,
1579 unsigned short flags, char read_write,
1580 u8 command, int size,
1581 union i2c_smbus_data *data)
1582{
1583 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adapter);
1584 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1585 struct stm32_i2c_dma *dma = i2c_dev->dma;
1586 struct device *dev = i2c_dev->dev;
1587 unsigned long timeout;
1588 int i, ret;
1589
1590 f7_msg->addr = addr;
1591 f7_msg->size = size;
1592 f7_msg->read_write = read_write;
1593 f7_msg->smbus = true;
1594
1595 ret = clk_enable(i2c_dev->clk);
1596 if (ret) {
1597 dev_err(i2c_dev->dev, "Failed to enable clock\n");
1598 return ret;
1599 }
1600
1601 ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1602 if (ret)
1603 goto clk_free;
1604
1605 ret = stm32f7_i2c_smbus_xfer_msg(i2c_dev, flags, command, data);
1606 if (ret)
1607 goto clk_free;
1608
1609 timeout = wait_for_completion_timeout(&i2c_dev->complete,
1610 i2c_dev->adap.timeout);
1611 ret = f7_msg->result;
1612 if (ret)
1613 goto clk_free;
1614
1615 if (!timeout) {
1616 dev_dbg(dev, "Access to slave 0x%x timed out\n", f7_msg->addr);
1617 if (i2c_dev->use_dma)
1618 dmaengine_terminate_all(dma->chan_using);
1619 ret = -ETIMEDOUT;
1620 goto clk_free;
1621 }
1622
1623 /* Check PEC */
1624 if ((flags & I2C_CLIENT_PEC) && size != I2C_SMBUS_QUICK && read_write) {
1625 ret = stm32f7_i2c_smbus_check_pec(i2c_dev);
1626 if (ret)
1627 goto clk_free;
1628 }
1629
1630 if (read_write && size != I2C_SMBUS_QUICK) {
1631 switch (size) {
1632 case I2C_SMBUS_BYTE:
1633 case I2C_SMBUS_BYTE_DATA:
1634 data->byte = f7_msg->smbus_buf[0];
1635 break;
1636 case I2C_SMBUS_WORD_DATA:
1637 case I2C_SMBUS_PROC_CALL:
1638 data->word = f7_msg->smbus_buf[0] |
1639 (f7_msg->smbus_buf[1] << 8);
1640 break;
1641 case I2C_SMBUS_BLOCK_DATA:
1642 case I2C_SMBUS_BLOCK_PROC_CALL:
1643 for (i = 0; i <= f7_msg->smbus_buf[0]; i++)
1644 data->block[i] = f7_msg->smbus_buf[i];
1645 break;
1646 default:
1647 dev_err(dev, "Unsupported smbus transaction\n");
1648 ret = -EINVAL;
1649 }
1650 }
1651
1652clk_free:
1653 clk_disable(i2c_dev->clk);
1654 return ret;
1655}
1656
1657static int stm32f7_i2c_reg_slave(struct i2c_client *slave)
1658{
1659 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1660 void __iomem *base = i2c_dev->base;
1661 struct device *dev = i2c_dev->dev;
1662 u32 oar1, oar2, mask;
1663 int id, ret;
1664
1665 if (slave->flags & I2C_CLIENT_PEC) {
1666 dev_err(dev, "SMBus PEC not supported in slave mode\n");
1667 return -EINVAL;
1668 }
1669
1670 if (stm32f7_i2c_is_slave_busy(i2c_dev)) {
1671 dev_err(dev, "Too much slave registered\n");
1672 return -EBUSY;
1673 }
1674
1675 ret = stm32f7_i2c_get_free_slave_id(i2c_dev, slave, &id);
1676 if (ret)
1677 return ret;
1678
1679 if (!(stm32f7_i2c_is_slave_registered(i2c_dev))) {
1680 ret = clk_enable(i2c_dev->clk);
1681 if (ret) {
1682 dev_err(dev, "Failed to enable clock\n");
1683 return ret;
1684 }
1685 }
1686
1687 if (id == 0) {
1688 /* Configure Own Address 1 */
1689 oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
1690 oar1 &= ~STM32F7_I2C_OAR1_MASK;
1691 if (slave->flags & I2C_CLIENT_TEN) {
1692 oar1 |= STM32F7_I2C_OAR1_OA1_10(slave->addr);
1693 oar1 |= STM32F7_I2C_OAR1_OA1MODE;
1694 } else {
1695 oar1 |= STM32F7_I2C_OAR1_OA1_7(slave->addr);
1696 }
1697 oar1 |= STM32F7_I2C_OAR1_OA1EN;
1698 i2c_dev->slave[id] = slave;
1699 writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1);
1700 } else if (id == 1) {
1701 /* Configure Own Address 2 */
1702 oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
1703 oar2 &= ~STM32F7_I2C_OAR2_MASK;
1704 if (slave->flags & I2C_CLIENT_TEN) {
1705 ret = -EOPNOTSUPP;
1706 goto exit;
1707 }
1708
1709 oar2 |= STM32F7_I2C_OAR2_OA2_7(slave->addr);
1710 oar2 |= STM32F7_I2C_OAR2_OA2EN;
1711 i2c_dev->slave[id] = slave;
1712 writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2);
1713 } else {
1714 ret = -ENODEV;
1715 goto exit;
1716 }
1717
1718 /* Enable ACK */
1719 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, STM32F7_I2C_CR2_NACK);
1720
1721 /* Enable Address match interrupt, error interrupt and enable I2C */
1722 mask = STM32F7_I2C_CR1_ADDRIE | STM32F7_I2C_CR1_ERRIE |
1723 STM32F7_I2C_CR1_PE;
1724 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1725
1726 return 0;
1727
1728exit:
1729 if (!(stm32f7_i2c_is_slave_registered(i2c_dev)))
1730 clk_disable(i2c_dev->clk);
1731
1732 return ret;
1733}
1734
1735static int stm32f7_i2c_unreg_slave(struct i2c_client *slave)
1736{
1737 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1738 void __iomem *base = i2c_dev->base;
1739 u32 mask;
1740 int id, ret;
1741
1742 ret = stm32f7_i2c_get_slave_id(i2c_dev, slave, &id);
1743 if (ret)
1744 return ret;
1745
1746 WARN_ON(!i2c_dev->slave[id]);
1747
1748 if (id == 0) {
1749 mask = STM32F7_I2C_OAR1_OA1EN;
1750 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR1, mask);
1751 } else {
1752 mask = STM32F7_I2C_OAR2_OA2EN;
1753 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR2, mask);
1754 }
1755
1756 i2c_dev->slave[id] = NULL;
1757
1758 if (!(stm32f7_i2c_is_slave_registered(i2c_dev))) {
1759 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK);
1760 clk_disable(i2c_dev->clk);
1761 }
1762
1763 return 0;
1764}
1765
799static u32 stm32f7_i2c_func(struct i2c_adapter *adap) 1766static u32 stm32f7_i2c_func(struct i2c_adapter *adap)
800{ 1767{
801 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 1768 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SLAVE |
1769 I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
1770 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
1771 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
1772 I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_PEC;
802} 1773}
803 1774
804static struct i2c_algorithm stm32f7_i2c_algo = { 1775static struct i2c_algorithm stm32f7_i2c_algo = {
805 .master_xfer = stm32f7_i2c_xfer, 1776 .master_xfer = stm32f7_i2c_xfer,
1777 .smbus_xfer = stm32f7_i2c_smbus_xfer,
806 .functionality = stm32f7_i2c_func, 1778 .functionality = stm32f7_i2c_func,
1779 .reg_slave = stm32f7_i2c_reg_slave,
1780 .unreg_slave = stm32f7_i2c_unreg_slave,
807}; 1781};
808 1782
809static int stm32f7_i2c_probe(struct platform_device *pdev) 1783static int stm32f7_i2c_probe(struct platform_device *pdev)
@@ -815,6 +1789,7 @@ static int stm32f7_i2c_probe(struct platform_device *pdev)
815 u32 irq_error, irq_event, clk_rate, rise_time, fall_time; 1789 u32 irq_error, irq_event, clk_rate, rise_time, fall_time;
816 struct i2c_adapter *adap; 1790 struct i2c_adapter *adap;
817 struct reset_control *rst; 1791 struct reset_control *rst;
1792 dma_addr_t phy_addr;
818 int ret; 1793 int ret;
819 1794
820 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); 1795 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
@@ -825,6 +1800,7 @@ static int stm32f7_i2c_probe(struct platform_device *pdev)
825 i2c_dev->base = devm_ioremap_resource(&pdev->dev, res); 1800 i2c_dev->base = devm_ioremap_resource(&pdev->dev, res);
826 if (IS_ERR(i2c_dev->base)) 1801 if (IS_ERR(i2c_dev->base))
827 return PTR_ERR(i2c_dev->base); 1802 return PTR_ERR(i2c_dev->base);
1803 phy_addr = (dma_addr_t)res->start;
828 1804
829 irq_event = irq_of_parse_and_map(np, 0); 1805 irq_event = irq_of_parse_and_map(np, 0);
830 if (!irq_event) { 1806 if (!irq_event) {
@@ -871,8 +1847,11 @@ static int stm32f7_i2c_probe(struct platform_device *pdev)
871 1847
872 i2c_dev->dev = &pdev->dev; 1848 i2c_dev->dev = &pdev->dev;
873 1849
874 ret = devm_request_irq(&pdev->dev, irq_event, stm32f7_i2c_isr_event, 0, 1850 ret = devm_request_threaded_irq(&pdev->dev, irq_event,
875 pdev->name, i2c_dev); 1851 stm32f7_i2c_isr_event,
1852 stm32f7_i2c_isr_event_thread,
1853 IRQF_ONESHOT,
1854 pdev->name, i2c_dev);
876 if (ret) { 1855 if (ret) {
877 dev_err(&pdev->dev, "Failed to request irq event %i\n", 1856 dev_err(&pdev->dev, "Failed to request irq event %i\n",
878 irq_event); 1857 irq_event);
@@ -924,6 +1903,11 @@ static int stm32f7_i2c_probe(struct platform_device *pdev)
924 1903
925 init_completion(&i2c_dev->complete); 1904 init_completion(&i2c_dev->complete);
926 1905
1906 /* Init DMA config if supported */
1907 i2c_dev->dma = stm32_i2c_dma_request(i2c_dev->dev, phy_addr,
1908 STM32F7_I2C_TXDR,
1909 STM32F7_I2C_RXDR);
1910
927 ret = i2c_add_adapter(adap); 1911 ret = i2c_add_adapter(adap);
928 if (ret) 1912 if (ret)
929 goto clk_free; 1913 goto clk_free;
@@ -946,6 +1930,11 @@ static int stm32f7_i2c_remove(struct platform_device *pdev)
946{ 1930{
947 struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 1931 struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
948 1932
1933 if (i2c_dev->dma) {
1934 stm32_i2c_dma_free(i2c_dev->dma);
1935 i2c_dev->dma = NULL;
1936 }
1937
949 i2c_del_adapter(&i2c_dev->adap); 1938 i2c_del_adapter(&i2c_dev->adap);
950 1939
951 clk_unprepare(i2c_dev->clk); 1940 clk_unprepare(i2c_dev->clk);
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-01 12:25:35 -0400