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-rw-r--r--drivers/gpu/drm/tegra/sor.c371
-rw-r--r--drivers/gpu/drm/tegra/sor.h208
2 files changed, 290 insertions, 289 deletions
diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c
index 7591d8901f9a..65088ddeeae9 100644
--- a/drivers/gpu/drm/tegra/sor.c
+++ b/drivers/gpu/drm/tegra/sor.c
@@ -94,40 +94,40 @@ static int tegra_sor_dp_train_fast(struct tegra_sor *sor,
94 SOR_LANE_DRIVE_CURRENT_LANE2(0x40) | 94 SOR_LANE_DRIVE_CURRENT_LANE2(0x40) |
95 SOR_LANE_DRIVE_CURRENT_LANE1(0x40) | 95 SOR_LANE_DRIVE_CURRENT_LANE1(0x40) |
96 SOR_LANE_DRIVE_CURRENT_LANE0(0x40); 96 SOR_LANE_DRIVE_CURRENT_LANE0(0x40);
97 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT_0); 97 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0);
98 98
99 value = SOR_LANE_PREEMPHASIS_LANE3(0x0f) | 99 value = SOR_LANE_PREEMPHASIS_LANE3(0x0f) |
100 SOR_LANE_PREEMPHASIS_LANE2(0x0f) | 100 SOR_LANE_PREEMPHASIS_LANE2(0x0f) |
101 SOR_LANE_PREEMPHASIS_LANE1(0x0f) | 101 SOR_LANE_PREEMPHASIS_LANE1(0x0f) |
102 SOR_LANE_PREEMPHASIS_LANE0(0x0f); 102 SOR_LANE_PREEMPHASIS_LANE0(0x0f);
103 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS_0); 103 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0);
104 104
105 value = SOR_LANE_POST_CURSOR_LANE3(0x00) | 105 value = SOR_LANE_POSTCURSOR_LANE3(0x00) |
106 SOR_LANE_POST_CURSOR_LANE2(0x00) | 106 SOR_LANE_POSTCURSOR_LANE2(0x00) |
107 SOR_LANE_POST_CURSOR_LANE1(0x00) | 107 SOR_LANE_POSTCURSOR_LANE1(0x00) |
108 SOR_LANE_POST_CURSOR_LANE0(0x00); 108 SOR_LANE_POSTCURSOR_LANE0(0x00);
109 tegra_sor_writel(sor, value, SOR_LANE_POST_CURSOR_0); 109 tegra_sor_writel(sor, value, SOR_LANE_POSTCURSOR0);
110 110
111 /* disable LVDS mode */ 111 /* disable LVDS mode */
112 tegra_sor_writel(sor, 0, SOR_LVDS); 112 tegra_sor_writel(sor, 0, SOR_LVDS);
113 113
114 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); 114 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
115 value |= SOR_DP_PADCTL_TX_PU_ENABLE; 115 value |= SOR_DP_PADCTL_TX_PU_ENABLE;
116 value &= ~SOR_DP_PADCTL_TX_PU_MASK; 116 value &= ~SOR_DP_PADCTL_TX_PU_MASK;
117 value |= SOR_DP_PADCTL_TX_PU(2); /* XXX: don't hardcode? */ 117 value |= SOR_DP_PADCTL_TX_PU(2); /* XXX: don't hardcode? */
118 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); 118 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
119 119
120 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); 120 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
121 value |= SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | 121 value |= SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
122 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0; 122 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0;
123 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); 123 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
124 124
125 usleep_range(10, 100); 125 usleep_range(10, 100);
126 126
127 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); 127 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
128 value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | 128 value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
129 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0); 129 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0);
130 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); 130 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
131 131
132 err = tegra_dpaux_prepare(sor->dpaux, DP_SET_ANSI_8B10B); 132 err = tegra_dpaux_prepare(sor->dpaux, DP_SET_ANSI_8B10B);
133 if (err < 0) 133 if (err < 0)
@@ -148,11 +148,11 @@ static int tegra_sor_dp_train_fast(struct tegra_sor *sor,
148 if (err < 0) 148 if (err < 0)
149 return err; 149 return err;
150 150
151 value = tegra_sor_readl(sor, SOR_DP_SPARE_0); 151 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
152 value |= SOR_DP_SPARE_SEQ_ENABLE; 152 value |= SOR_DP_SPARE_SEQ_ENABLE;
153 value &= ~SOR_DP_SPARE_PANEL_INTERNAL; 153 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
154 value |= SOR_DP_SPARE_MACRO_SOR_CLK; 154 value |= SOR_DP_SPARE_MACRO_SOR_CLK;
155 tegra_sor_writel(sor, value, SOR_DP_SPARE_0); 155 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
156 156
157 for (i = 0, value = 0; i < link->num_lanes; i++) { 157 for (i = 0, value = 0; i < link->num_lanes; i++) {
158 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | 158 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
@@ -189,16 +189,16 @@ static int tegra_sor_dp_train_fast(struct tegra_sor *sor,
189 189
190static void tegra_sor_super_update(struct tegra_sor *sor) 190static void tegra_sor_super_update(struct tegra_sor *sor)
191{ 191{
192 tegra_sor_writel(sor, 0, SOR_SUPER_STATE_0); 192 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
193 tegra_sor_writel(sor, 1, SOR_SUPER_STATE_0); 193 tegra_sor_writel(sor, 1, SOR_SUPER_STATE0);
194 tegra_sor_writel(sor, 0, SOR_SUPER_STATE_0); 194 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
195} 195}
196 196
197static void tegra_sor_update(struct tegra_sor *sor) 197static void tegra_sor_update(struct tegra_sor *sor)
198{ 198{
199 tegra_sor_writel(sor, 0, SOR_STATE_0); 199 tegra_sor_writel(sor, 0, SOR_STATE0);
200 tegra_sor_writel(sor, 1, SOR_STATE_0); 200 tegra_sor_writel(sor, 1, SOR_STATE0);
201 tegra_sor_writel(sor, 0, SOR_STATE_0); 201 tegra_sor_writel(sor, 0, SOR_STATE0);
202} 202}
203 203
204static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout) 204static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout)
@@ -235,16 +235,16 @@ static int tegra_sor_attach(struct tegra_sor *sor)
235 unsigned long value, timeout; 235 unsigned long value, timeout;
236 236
237 /* wake up in normal mode */ 237 /* wake up in normal mode */
238 value = tegra_sor_readl(sor, SOR_SUPER_STATE_1); 238 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
239 value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE; 239 value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE;
240 value |= SOR_SUPER_STATE_MODE_NORMAL; 240 value |= SOR_SUPER_STATE_MODE_NORMAL;
241 tegra_sor_writel(sor, value, SOR_SUPER_STATE_1); 241 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
242 tegra_sor_super_update(sor); 242 tegra_sor_super_update(sor);
243 243
244 /* attach */ 244 /* attach */
245 value = tegra_sor_readl(sor, SOR_SUPER_STATE_1); 245 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
246 value |= SOR_SUPER_STATE_ATTACHED; 246 value |= SOR_SUPER_STATE_ATTACHED;
247 tegra_sor_writel(sor, value, SOR_SUPER_STATE_1); 247 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
248 tegra_sor_super_update(sor); 248 tegra_sor_super_update(sor);
249 249
250 timeout = jiffies + msecs_to_jiffies(250); 250 timeout = jiffies + msecs_to_jiffies(250);
@@ -481,9 +481,9 @@ static int tegra_sor_detach(struct tegra_sor *sor)
481 unsigned long value, timeout; 481 unsigned long value, timeout;
482 482
483 /* switch to safe mode */ 483 /* switch to safe mode */
484 value = tegra_sor_readl(sor, SOR_SUPER_STATE_1); 484 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
485 value &= ~SOR_SUPER_STATE_MODE_NORMAL; 485 value &= ~SOR_SUPER_STATE_MODE_NORMAL;
486 tegra_sor_writel(sor, value, SOR_SUPER_STATE_1); 486 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
487 tegra_sor_super_update(sor); 487 tegra_sor_super_update(sor);
488 488
489 timeout = jiffies + msecs_to_jiffies(250); 489 timeout = jiffies + msecs_to_jiffies(250);
@@ -498,15 +498,15 @@ static int tegra_sor_detach(struct tegra_sor *sor)
498 return -ETIMEDOUT; 498 return -ETIMEDOUT;
499 499
500 /* go to sleep */ 500 /* go to sleep */
501 value = tegra_sor_readl(sor, SOR_SUPER_STATE_1); 501 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
502 value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK; 502 value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK;
503 tegra_sor_writel(sor, value, SOR_SUPER_STATE_1); 503 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
504 tegra_sor_super_update(sor); 504 tegra_sor_super_update(sor);
505 505
506 /* detach */ 506 /* detach */
507 value = tegra_sor_readl(sor, SOR_SUPER_STATE_1); 507 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
508 value &= ~SOR_SUPER_STATE_ATTACHED; 508 value &= ~SOR_SUPER_STATE_ATTACHED;
509 tegra_sor_writel(sor, value, SOR_SUPER_STATE_1); 509 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
510 tegra_sor_super_update(sor); 510 tegra_sor_super_update(sor);
511 511
512 timeout = jiffies + msecs_to_jiffies(250); 512 timeout = jiffies + msecs_to_jiffies(250);
@@ -552,10 +552,10 @@ static int tegra_sor_power_down(struct tegra_sor *sor)
552 if (err < 0) 552 if (err < 0)
553 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); 553 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
554 554
555 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); 555 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
556 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | 556 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
557 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2); 557 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2);
558 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); 558 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
559 559
560 /* stop lane sequencer */ 560 /* stop lane sequencer */
561 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP | 561 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP |
@@ -575,21 +575,20 @@ static int tegra_sor_power_down(struct tegra_sor *sor)
575 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) 575 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
576 return -ETIMEDOUT; 576 return -ETIMEDOUT;
577 577
578 value = tegra_sor_readl(sor, SOR_PLL_2); 578 value = tegra_sor_readl(sor, SOR_PLL2);
579 value |= SOR_PLL_2_PORT_POWERDOWN; 579 value |= SOR_PLL2_PORT_POWERDOWN;
580 tegra_sor_writel(sor, value, SOR_PLL_2); 580 tegra_sor_writel(sor, value, SOR_PLL2);
581 581
582 usleep_range(20, 100); 582 usleep_range(20, 100);
583 583
584 value = tegra_sor_readl(sor, SOR_PLL_0); 584 value = tegra_sor_readl(sor, SOR_PLL0);
585 value |= SOR_PLL_0_POWER_OFF; 585 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;
586 value |= SOR_PLL_0_VCOPD; 586 tegra_sor_writel(sor, value, SOR_PLL0);
587 tegra_sor_writel(sor, value, SOR_PLL_0);
588 587
589 value = tegra_sor_readl(sor, SOR_PLL_2); 588 value = tegra_sor_readl(sor, SOR_PLL2);
590 value |= SOR_PLL_2_SEQ_PLLCAPPD; 589 value |= SOR_PLL2_SEQ_PLLCAPPD;
591 value |= SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE; 590 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
592 tegra_sor_writel(sor, value, SOR_PLL_2); 591 tegra_sor_writel(sor, value, SOR_PLL2);
593 592
594 usleep_range(20, 100); 593 usleep_range(20, 100);
595 594
@@ -615,8 +614,8 @@ static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout)
615 timeout = jiffies + msecs_to_jiffies(timeout); 614 timeout = jiffies + msecs_to_jiffies(timeout);
616 615
617 while (time_before(jiffies, timeout)) { 616 while (time_before(jiffies, timeout)) {
618 value = tegra_sor_readl(sor, SOR_CRC_A); 617 value = tegra_sor_readl(sor, SOR_CRCA);
619 if (value & SOR_CRC_A_VALID) 618 if (value & SOR_CRCA_VALID)
620 return 0; 619 return 0;
621 620
622 usleep_range(100, 200); 621 usleep_range(100, 200);
@@ -640,9 +639,9 @@ static ssize_t tegra_sor_crc_read(struct file *file, char __user *buffer,
640 goto unlock; 639 goto unlock;
641 } 640 }
642 641
643 value = tegra_sor_readl(sor, SOR_STATE_1); 642 value = tegra_sor_readl(sor, SOR_STATE1);
644 value &= ~SOR_STATE_ASY_CRC_MODE_MASK; 643 value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
645 tegra_sor_writel(sor, value, SOR_STATE_1); 644 tegra_sor_writel(sor, value, SOR_STATE1);
646 645
647 value = tegra_sor_readl(sor, SOR_CRC_CNTRL); 646 value = tegra_sor_readl(sor, SOR_CRC_CNTRL);
648 value |= SOR_CRC_CNTRL_ENABLE; 647 value |= SOR_CRC_CNTRL_ENABLE;
@@ -656,8 +655,8 @@ static ssize_t tegra_sor_crc_read(struct file *file, char __user *buffer,
656 if (err < 0) 655 if (err < 0)
657 goto unlock; 656 goto unlock;
658 657
659 tegra_sor_writel(sor, SOR_CRC_A_RESET, SOR_CRC_A); 658 tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA);
660 value = tegra_sor_readl(sor, SOR_CRC_B); 659 value = tegra_sor_readl(sor, SOR_CRCB);
661 660
662 num = scnprintf(buf, sizeof(buf), "%08x\n", value); 661 num = scnprintf(buf, sizeof(buf), "%08x\n", value);
663 662
@@ -685,36 +684,36 @@ static int tegra_sor_show_regs(struct seq_file *s, void *data)
685 tegra_sor_readl(sor, name)) 684 tegra_sor_readl(sor, name))
686 685
687 DUMP_REG(SOR_CTXSW); 686 DUMP_REG(SOR_CTXSW);
688 DUMP_REG(SOR_SUPER_STATE_0); 687 DUMP_REG(SOR_SUPER_STATE0);
689 DUMP_REG(SOR_SUPER_STATE_1); 688 DUMP_REG(SOR_SUPER_STATE1);
690 DUMP_REG(SOR_STATE_0); 689 DUMP_REG(SOR_STATE0);
691 DUMP_REG(SOR_STATE_1); 690 DUMP_REG(SOR_STATE1);
692 DUMP_REG(SOR_HEAD_STATE_0(0)); 691 DUMP_REG(SOR_HEAD_STATE0(0));
693 DUMP_REG(SOR_HEAD_STATE_0(1)); 692 DUMP_REG(SOR_HEAD_STATE0(1));
694 DUMP_REG(SOR_HEAD_STATE_1(0)); 693 DUMP_REG(SOR_HEAD_STATE1(0));
695 DUMP_REG(SOR_HEAD_STATE_1(1)); 694 DUMP_REG(SOR_HEAD_STATE1(1));
696 DUMP_REG(SOR_HEAD_STATE_2(0)); 695 DUMP_REG(SOR_HEAD_STATE2(0));
697 DUMP_REG(SOR_HEAD_STATE_2(1)); 696 DUMP_REG(SOR_HEAD_STATE2(1));
698 DUMP_REG(SOR_HEAD_STATE_3(0)); 697 DUMP_REG(SOR_HEAD_STATE3(0));
699 DUMP_REG(SOR_HEAD_STATE_3(1)); 698 DUMP_REG(SOR_HEAD_STATE3(1));
700 DUMP_REG(SOR_HEAD_STATE_4(0)); 699 DUMP_REG(SOR_HEAD_STATE4(0));
701 DUMP_REG(SOR_HEAD_STATE_4(1)); 700 DUMP_REG(SOR_HEAD_STATE4(1));
702 DUMP_REG(SOR_HEAD_STATE_5(0)); 701 DUMP_REG(SOR_HEAD_STATE5(0));
703 DUMP_REG(SOR_HEAD_STATE_5(1)); 702 DUMP_REG(SOR_HEAD_STATE5(1));
704 DUMP_REG(SOR_CRC_CNTRL); 703 DUMP_REG(SOR_CRC_CNTRL);
705 DUMP_REG(SOR_DP_DEBUG_MVID); 704 DUMP_REG(SOR_DP_DEBUG_MVID);
706 DUMP_REG(SOR_CLK_CNTRL); 705 DUMP_REG(SOR_CLK_CNTRL);
707 DUMP_REG(SOR_CAP); 706 DUMP_REG(SOR_CAP);
708 DUMP_REG(SOR_PWR); 707 DUMP_REG(SOR_PWR);
709 DUMP_REG(SOR_TEST); 708 DUMP_REG(SOR_TEST);
710 DUMP_REG(SOR_PLL_0); 709 DUMP_REG(SOR_PLL0);
711 DUMP_REG(SOR_PLL_1); 710 DUMP_REG(SOR_PLL1);
712 DUMP_REG(SOR_PLL_2); 711 DUMP_REG(SOR_PLL2);
713 DUMP_REG(SOR_PLL_3); 712 DUMP_REG(SOR_PLL3);
714 DUMP_REG(SOR_CSTM); 713 DUMP_REG(SOR_CSTM);
715 DUMP_REG(SOR_LVDS); 714 DUMP_REG(SOR_LVDS);
716 DUMP_REG(SOR_CRC_A); 715 DUMP_REG(SOR_CRCA);
717 DUMP_REG(SOR_CRC_B); 716 DUMP_REG(SOR_CRCB);
718 DUMP_REG(SOR_BLANK); 717 DUMP_REG(SOR_BLANK);
719 DUMP_REG(SOR_SEQ_CTL); 718 DUMP_REG(SOR_SEQ_CTL);
720 DUMP_REG(SOR_LANE_SEQ_CTL); 719 DUMP_REG(SOR_LANE_SEQ_CTL);
@@ -736,68 +735,68 @@ static int tegra_sor_show_regs(struct seq_file *s, void *data)
736 DUMP_REG(SOR_SEQ_INST(15)); 735 DUMP_REG(SOR_SEQ_INST(15));
737 DUMP_REG(SOR_PWM_DIV); 736 DUMP_REG(SOR_PWM_DIV);
738 DUMP_REG(SOR_PWM_CTL); 737 DUMP_REG(SOR_PWM_CTL);
739 DUMP_REG(SOR_VCRC_A_0); 738 DUMP_REG(SOR_VCRC_A0);
740 DUMP_REG(SOR_VCRC_A_1); 739 DUMP_REG(SOR_VCRC_A1);
741 DUMP_REG(SOR_VCRC_B_0); 740 DUMP_REG(SOR_VCRC_B0);
742 DUMP_REG(SOR_VCRC_B_1); 741 DUMP_REG(SOR_VCRC_B1);
743 DUMP_REG(SOR_CCRC_A_0); 742 DUMP_REG(SOR_CCRC_A0);
744 DUMP_REG(SOR_CCRC_A_1); 743 DUMP_REG(SOR_CCRC_A1);
745 DUMP_REG(SOR_CCRC_B_0); 744 DUMP_REG(SOR_CCRC_B0);
746 DUMP_REG(SOR_CCRC_B_1); 745 DUMP_REG(SOR_CCRC_B1);
747 DUMP_REG(SOR_EDATA_A_0); 746 DUMP_REG(SOR_EDATA_A0);
748 DUMP_REG(SOR_EDATA_A_1); 747 DUMP_REG(SOR_EDATA_A1);
749 DUMP_REG(SOR_EDATA_B_0); 748 DUMP_REG(SOR_EDATA_B0);
750 DUMP_REG(SOR_EDATA_B_1); 749 DUMP_REG(SOR_EDATA_B1);
751 DUMP_REG(SOR_COUNT_A_0); 750 DUMP_REG(SOR_COUNT_A0);
752 DUMP_REG(SOR_COUNT_A_1); 751 DUMP_REG(SOR_COUNT_A1);
753 DUMP_REG(SOR_COUNT_B_0); 752 DUMP_REG(SOR_COUNT_B0);
754 DUMP_REG(SOR_COUNT_B_1); 753 DUMP_REG(SOR_COUNT_B1);
755 DUMP_REG(SOR_DEBUG_A_0); 754 DUMP_REG(SOR_DEBUG_A0);
756 DUMP_REG(SOR_DEBUG_A_1); 755 DUMP_REG(SOR_DEBUG_A1);
757 DUMP_REG(SOR_DEBUG_B_0); 756 DUMP_REG(SOR_DEBUG_B0);
758 DUMP_REG(SOR_DEBUG_B_1); 757 DUMP_REG(SOR_DEBUG_B1);
759 DUMP_REG(SOR_TRIG); 758 DUMP_REG(SOR_TRIG);
760 DUMP_REG(SOR_MSCHECK); 759 DUMP_REG(SOR_MSCHECK);
761 DUMP_REG(SOR_XBAR_CTRL); 760 DUMP_REG(SOR_XBAR_CTRL);
762 DUMP_REG(SOR_XBAR_POL); 761 DUMP_REG(SOR_XBAR_POL);
763 DUMP_REG(SOR_DP_LINKCTL_0); 762 DUMP_REG(SOR_DP_LINKCTL0);
764 DUMP_REG(SOR_DP_LINKCTL_1); 763 DUMP_REG(SOR_DP_LINKCTL1);
765 DUMP_REG(SOR_LANE_DRIVE_CURRENT_0); 764 DUMP_REG(SOR_LANE_DRIVE_CURRENT0);
766 DUMP_REG(SOR_LANE_DRIVE_CURRENT_1); 765 DUMP_REG(SOR_LANE_DRIVE_CURRENT1);
767 DUMP_REG(SOR_LANE4_DRIVE_CURRENT_0); 766 DUMP_REG(SOR_LANE4_DRIVE_CURRENT0);
768 DUMP_REG(SOR_LANE4_DRIVE_CURRENT_1); 767 DUMP_REG(SOR_LANE4_DRIVE_CURRENT1);
769 DUMP_REG(SOR_LANE_PREEMPHASIS_0); 768 DUMP_REG(SOR_LANE_PREEMPHASIS0);
770 DUMP_REG(SOR_LANE_PREEMPHASIS_1); 769 DUMP_REG(SOR_LANE_PREEMPHASIS1);
771 DUMP_REG(SOR_LANE4_PREEMPHASIS_0); 770 DUMP_REG(SOR_LANE4_PREEMPHASIS0);
772 DUMP_REG(SOR_LANE4_PREEMPHASIS_1); 771 DUMP_REG(SOR_LANE4_PREEMPHASIS1);
773 DUMP_REG(SOR_LANE_POST_CURSOR_0); 772 DUMP_REG(SOR_LANE_POSTCURSOR0);
774 DUMP_REG(SOR_LANE_POST_CURSOR_1); 773 DUMP_REG(SOR_LANE_POSTCURSOR1);
775 DUMP_REG(SOR_DP_CONFIG_0); 774 DUMP_REG(SOR_DP_CONFIG0);
776 DUMP_REG(SOR_DP_CONFIG_1); 775 DUMP_REG(SOR_DP_CONFIG1);
777 DUMP_REG(SOR_DP_MN_0); 776 DUMP_REG(SOR_DP_MN0);
778 DUMP_REG(SOR_DP_MN_1); 777 DUMP_REG(SOR_DP_MN1);
779 DUMP_REG(SOR_DP_PADCTL_0); 778 DUMP_REG(SOR_DP_PADCTL0);
780 DUMP_REG(SOR_DP_PADCTL_1); 779 DUMP_REG(SOR_DP_PADCTL1);
781 DUMP_REG(SOR_DP_DEBUG_0); 780 DUMP_REG(SOR_DP_DEBUG0);
782 DUMP_REG(SOR_DP_DEBUG_1); 781 DUMP_REG(SOR_DP_DEBUG1);
783 DUMP_REG(SOR_DP_SPARE_0); 782 DUMP_REG(SOR_DP_SPARE0);
784 DUMP_REG(SOR_DP_SPARE_1); 783 DUMP_REG(SOR_DP_SPARE1);
785 DUMP_REG(SOR_DP_AUDIO_CTRL); 784 DUMP_REG(SOR_DP_AUDIO_CTRL);
786 DUMP_REG(SOR_DP_AUDIO_HBLANK_SYMBOLS); 785 DUMP_REG(SOR_DP_AUDIO_HBLANK_SYMBOLS);
787 DUMP_REG(SOR_DP_AUDIO_VBLANK_SYMBOLS); 786 DUMP_REG(SOR_DP_AUDIO_VBLANK_SYMBOLS);
788 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_HEADER); 787 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_HEADER);
789 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK_0); 788 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK0);
790 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK_1); 789 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK1);
791 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK_2); 790 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK2);
792 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK_3); 791 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK3);
793 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK_4); 792 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK4);
794 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK_5); 793 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK5);
795 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK_6); 794 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK6);
796 DUMP_REG(SOR_DP_TPG); 795 DUMP_REG(SOR_DP_TPG);
797 DUMP_REG(SOR_DP_TPG_CONFIG); 796 DUMP_REG(SOR_DP_TPG_CONFIG);
798 DUMP_REG(SOR_DP_LQ_CSTM_0); 797 DUMP_REG(SOR_DP_LQ_CSTM0);
799 DUMP_REG(SOR_DP_LQ_CSTM_1); 798 DUMP_REG(SOR_DP_LQ_CSTM1);
800 DUMP_REG(SOR_DP_LQ_CSTM_2); 799 DUMP_REG(SOR_DP_LQ_CSTM2);
801 800
802#undef DUMP_REG 801#undef DUMP_REG
803 802
@@ -999,40 +998,40 @@ static void tegra_sor_encoder_mode_set(struct drm_encoder *encoder,
999 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; 998 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
1000 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 999 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1001 1000
1002 value = tegra_sor_readl(sor, SOR_PLL_2); 1001 value = tegra_sor_readl(sor, SOR_PLL2);
1003 value &= ~SOR_PLL_2_BANDGAP_POWERDOWN; 1002 value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
1004 tegra_sor_writel(sor, value, SOR_PLL_2); 1003 tegra_sor_writel(sor, value, SOR_PLL2);
1005 usleep_range(20, 100); 1004 usleep_range(20, 100);
1006 1005
1007 value = tegra_sor_readl(sor, SOR_PLL_3); 1006 value = tegra_sor_readl(sor, SOR_PLL3);
1008 value |= SOR_PLL_3_PLL_VDD_MODE_V3_3; 1007 value |= SOR_PLL3_PLL_VDD_MODE_3V3;
1009 tegra_sor_writel(sor, value, SOR_PLL_3); 1008 tegra_sor_writel(sor, value, SOR_PLL3);
1010 1009
1011 value = SOR_PLL_0_ICHPMP(0xf) | SOR_PLL_0_VCOCAP_RST | 1010 value = SOR_PLL0_ICHPMP(0xf) | SOR_PLL0_VCOCAP_RST |
1012 SOR_PLL_0_PLLREG_LEVEL_V45 | SOR_PLL_0_RESISTOR_EXT; 1011 SOR_PLL0_PLLREG_LEVEL_V45 | SOR_PLL0_RESISTOR_EXT;
1013 tegra_sor_writel(sor, value, SOR_PLL_0); 1012 tegra_sor_writel(sor, value, SOR_PLL0);
1014 1013
1015 value = tegra_sor_readl(sor, SOR_PLL_2); 1014 value = tegra_sor_readl(sor, SOR_PLL2);
1016 value |= SOR_PLL_2_SEQ_PLLCAPPD; 1015 value |= SOR_PLL2_SEQ_PLLCAPPD;
1017 value &= ~SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE; 1016 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1018 value |= SOR_PLL_2_LVDS_ENABLE; 1017 value |= SOR_PLL2_LVDS_ENABLE;
1019 tegra_sor_writel(sor, value, SOR_PLL_2); 1018 tegra_sor_writel(sor, value, SOR_PLL2);
1020 1019
1021 value = SOR_PLL_1_TERM_COMPOUT | SOR_PLL_1_TMDS_TERM; 1020 value = SOR_PLL1_TERM_COMPOUT | SOR_PLL1_TMDS_TERM;
1022 tegra_sor_writel(sor, value, SOR_PLL_1); 1021 tegra_sor_writel(sor, value, SOR_PLL1);
1023 1022
1024 while (true) { 1023 while (true) {
1025 value = tegra_sor_readl(sor, SOR_PLL_2); 1024 value = tegra_sor_readl(sor, SOR_PLL2);
1026 if ((value & SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE) == 0) 1025 if ((value & SOR_PLL2_SEQ_PLLCAPPD_ENFORCE) == 0)
1027 break; 1026 break;
1028 1027
1029 usleep_range(250, 1000); 1028 usleep_range(250, 1000);
1030 } 1029 }
1031 1030
1032 value = tegra_sor_readl(sor, SOR_PLL_2); 1031 value = tegra_sor_readl(sor, SOR_PLL2);
1033 value &= ~SOR_PLL_2_POWERDOWN_OVERRIDE; 1032 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
1034 value &= ~SOR_PLL_2_PORT_POWERDOWN; 1033 value &= ~SOR_PLL2_PORT_POWERDOWN;
1035 tegra_sor_writel(sor, value, SOR_PLL_2); 1034 tegra_sor_writel(sor, value, SOR_PLL2);
1036 1035
1037 /* 1036 /*
1038 * power up 1037 * power up
@@ -1045,18 +1044,18 @@ static void tegra_sor_encoder_mode_set(struct drm_encoder *encoder,
1045 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 1044 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1046 1045
1047 /* step 1 */ 1046 /* step 1 */
1048 value = tegra_sor_readl(sor, SOR_PLL_2); 1047 value = tegra_sor_readl(sor, SOR_PLL2);
1049 value |= SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE | SOR_PLL_2_PORT_POWERDOWN | 1048 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE | SOR_PLL2_PORT_POWERDOWN |
1050 SOR_PLL_2_BANDGAP_POWERDOWN; 1049 SOR_PLL2_BANDGAP_POWERDOWN;
1051 tegra_sor_writel(sor, value, SOR_PLL_2); 1050 tegra_sor_writel(sor, value, SOR_PLL2);
1052 1051
1053 value = tegra_sor_readl(sor, SOR_PLL_0); 1052 value = tegra_sor_readl(sor, SOR_PLL0);
1054 value |= SOR_PLL_0_VCOPD | SOR_PLL_0_POWER_OFF; 1053 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;
1055 tegra_sor_writel(sor, value, SOR_PLL_0); 1054 tegra_sor_writel(sor, value, SOR_PLL0);
1056 1055
1057 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); 1056 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
1058 value &= ~SOR_DP_PADCTL_PAD_CAL_PD; 1057 value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
1059 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); 1058 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
1060 1059
1061 /* step 2 */ 1060 /* step 2 */
1062 err = tegra_io_rail_power_on(TEGRA_IO_RAIL_LVDS); 1061 err = tegra_io_rail_power_on(TEGRA_IO_RAIL_LVDS);
@@ -1068,28 +1067,28 @@ static void tegra_sor_encoder_mode_set(struct drm_encoder *encoder,
1068 usleep_range(5, 100); 1067 usleep_range(5, 100);
1069 1068
1070 /* step 3 */ 1069 /* step 3 */
1071 value = tegra_sor_readl(sor, SOR_PLL_2); 1070 value = tegra_sor_readl(sor, SOR_PLL2);
1072 value &= ~SOR_PLL_2_BANDGAP_POWERDOWN; 1071 value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
1073 tegra_sor_writel(sor, value, SOR_PLL_2); 1072 tegra_sor_writel(sor, value, SOR_PLL2);
1074 1073
1075 usleep_range(20, 100); 1074 usleep_range(20, 100);
1076 1075
1077 /* step 4 */ 1076 /* step 4 */
1078 value = tegra_sor_readl(sor, SOR_PLL_0); 1077 value = tegra_sor_readl(sor, SOR_PLL0);
1079 value &= ~SOR_PLL_0_POWER_OFF; 1078 value &= ~SOR_PLL0_VCOPD;
1080 value &= ~SOR_PLL_0_VCOPD; 1079 value &= ~SOR_PLL0_PWR;
1081 tegra_sor_writel(sor, value, SOR_PLL_0); 1080 tegra_sor_writel(sor, value, SOR_PLL0);
1082 1081
1083 value = tegra_sor_readl(sor, SOR_PLL_2); 1082 value = tegra_sor_readl(sor, SOR_PLL2);
1084 value &= ~SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE; 1083 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1085 tegra_sor_writel(sor, value, SOR_PLL_2); 1084 tegra_sor_writel(sor, value, SOR_PLL2);
1086 1085
1087 usleep_range(200, 1000); 1086 usleep_range(200, 1000);
1088 1087
1089 /* step 5 */ 1088 /* step 5 */
1090 value = tegra_sor_readl(sor, SOR_PLL_2); 1089 value = tegra_sor_readl(sor, SOR_PLL2);
1091 value &= ~SOR_PLL_2_PORT_POWERDOWN; 1090 value &= ~SOR_PLL2_PORT_POWERDOWN;
1092 tegra_sor_writel(sor, value, SOR_PLL_2); 1091 tegra_sor_writel(sor, value, SOR_PLL2);
1093 1092
1094 /* switch to DP clock */ 1093 /* switch to DP clock */
1095 err = clk_set_parent(sor->clk, sor->clk_dp); 1094 err = clk_set_parent(sor->clk, sor->clk_dp);
@@ -1097,7 +1096,7 @@ static void tegra_sor_encoder_mode_set(struct drm_encoder *encoder,
1097 dev_err(sor->dev, "failed to set DP parent clock: %d\n", err); 1096 dev_err(sor->dev, "failed to set DP parent clock: %d\n", err);
1098 1097
1099 /* power DP lanes */ 1098 /* power DP lanes */
1100 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); 1099 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
1101 1100
1102 if (link.num_lanes <= 2) 1101 if (link.num_lanes <= 2)
1103 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2); 1102 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2);
@@ -1114,12 +1113,12 @@ static void tegra_sor_encoder_mode_set(struct drm_encoder *encoder,
1114 else 1113 else
1115 value |= SOR_DP_PADCTL_PD_TXD_0; 1114 value |= SOR_DP_PADCTL_PD_TXD_0;
1116 1115
1117 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); 1116 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
1118 1117
1119 value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0); 1118 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1120 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; 1119 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
1121 value |= SOR_DP_LINKCTL_LANE_COUNT(link.num_lanes); 1120 value |= SOR_DP_LINKCTL_LANE_COUNT(link.num_lanes);
1122 tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0); 1121 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1123 1122
1124 /* start lane sequencer */ 1123 /* start lane sequencer */
1125 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | 1124 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
@@ -1141,14 +1140,14 @@ static void tegra_sor_encoder_mode_set(struct drm_encoder *encoder,
1141 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 1140 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1142 1141
1143 /* set linkctl */ 1142 /* set linkctl */
1144 value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0); 1143 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1145 value |= SOR_DP_LINKCTL_ENABLE; 1144 value |= SOR_DP_LINKCTL_ENABLE;
1146 1145
1147 value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK; 1146 value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK;
1148 value |= SOR_DP_LINKCTL_TU_SIZE(config.tu_size); 1147 value |= SOR_DP_LINKCTL_TU_SIZE(config.tu_size);
1149 1148
1150 value |= SOR_DP_LINKCTL_ENHANCED_FRAME; 1149 value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
1151 tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0); 1150 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1152 1151
1153 for (i = 0, value = 0; i < 4; i++) { 1152 for (i = 0, value = 0; i < 4; i++) {
1154 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | 1153 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
@@ -1159,7 +1158,7 @@ static void tegra_sor_encoder_mode_set(struct drm_encoder *encoder,
1159 1158
1160 tegra_sor_writel(sor, value, SOR_DP_TPG); 1159 tegra_sor_writel(sor, value, SOR_DP_TPG);
1161 1160
1162 value = tegra_sor_readl(sor, SOR_DP_CONFIG_0); 1161 value = tegra_sor_readl(sor, SOR_DP_CONFIG0);
1163 value &= ~SOR_DP_CONFIG_WATERMARK_MASK; 1162 value &= ~SOR_DP_CONFIG_WATERMARK_MASK;
1164 value |= SOR_DP_CONFIG_WATERMARK(config.watermark); 1163 value |= SOR_DP_CONFIG_WATERMARK(config.watermark);
1165 1164
@@ -1176,7 +1175,7 @@ static void tegra_sor_encoder_mode_set(struct drm_encoder *encoder,
1176 1175
1177 value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE; 1176 value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE;
1178 value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE; 1177 value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE;
1179 tegra_sor_writel(sor, value, SOR_DP_CONFIG_0); 1178 tegra_sor_writel(sor, value, SOR_DP_CONFIG0);
1180 1179
1181 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS); 1180 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1182 value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK; 1181 value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK;
@@ -1189,9 +1188,9 @@ static void tegra_sor_encoder_mode_set(struct drm_encoder *encoder,
1189 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS); 1188 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1190 1189
1191 /* enable pad calibration logic */ 1190 /* enable pad calibration logic */
1192 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); 1191 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
1193 value |= SOR_DP_PADCTL_PAD_CAL_PD; 1192 value |= SOR_DP_PADCTL_PAD_CAL_PD;
1194 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); 1193 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
1195 1194
1196 if (sor->dpaux) { 1195 if (sor->dpaux) {
1197 u8 rate, lanes; 1196 u8 rate, lanes;
@@ -1225,14 +1224,14 @@ static void tegra_sor_encoder_mode_set(struct drm_encoder *encoder,
1225 value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate); 1224 value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate);
1226 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 1225 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1227 1226
1228 value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0); 1227 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1229 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; 1228 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
1230 value |= SOR_DP_LINKCTL_LANE_COUNT(lanes); 1229 value |= SOR_DP_LINKCTL_LANE_COUNT(lanes);
1231 1230
1232 if (link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) 1231 if (link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
1233 value |= SOR_DP_LINKCTL_ENHANCED_FRAME; 1232 value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
1234 1233
1235 tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0); 1234 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1236 1235
1237 /* disable training pattern generator */ 1236 /* disable training pattern generator */
1238 1237
@@ -1295,7 +1294,7 @@ static void tegra_sor_encoder_mode_set(struct drm_encoder *encoder,
1295 break; 1294 break;
1296 } 1295 }
1297 1296
1298 tegra_sor_writel(sor, value, SOR_STATE_1); 1297 tegra_sor_writel(sor, value, SOR_STATE1);
1299 1298
1300 /* 1299 /*
1301 * TODO: The video timing programming below doesn't seem to match the 1300 * TODO: The video timing programming below doesn't seem to match the
@@ -1303,25 +1302,25 @@ static void tegra_sor_encoder_mode_set(struct drm_encoder *encoder,
1303 */ 1302 */
1304 1303
1305 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff); 1304 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff);
1306 tegra_sor_writel(sor, value, SOR_HEAD_STATE_1(0)); 1305 tegra_sor_writel(sor, value, SOR_HEAD_STATE1(0));
1307 1306
1308 vse = mode->vsync_end - mode->vsync_start - 1; 1307 vse = mode->vsync_end - mode->vsync_start - 1;
1309 hse = mode->hsync_end - mode->hsync_start - 1; 1308 hse = mode->hsync_end - mode->hsync_start - 1;
1310 1309
1311 value = ((vse & 0x7fff) << 16) | (hse & 0x7fff); 1310 value = ((vse & 0x7fff) << 16) | (hse & 0x7fff);
1312 tegra_sor_writel(sor, value, SOR_HEAD_STATE_2(0)); 1311 tegra_sor_writel(sor, value, SOR_HEAD_STATE2(0));
1313 1312
1314 vbe = vse + (mode->vsync_start - mode->vdisplay); 1313 vbe = vse + (mode->vsync_start - mode->vdisplay);
1315 hbe = hse + (mode->hsync_start - mode->hdisplay); 1314 hbe = hse + (mode->hsync_start - mode->hdisplay);
1316 1315
1317 value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff); 1316 value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff);
1318 tegra_sor_writel(sor, value, SOR_HEAD_STATE_3(0)); 1317 tegra_sor_writel(sor, value, SOR_HEAD_STATE3(0));
1319 1318
1320 vbs = vbe + mode->vdisplay; 1319 vbs = vbe + mode->vdisplay;
1321 hbs = hbe + mode->hdisplay; 1320 hbs = hbe + mode->hdisplay;
1322 1321
1323 value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff); 1322 value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff);
1324 tegra_sor_writel(sor, value, SOR_HEAD_STATE_4(0)); 1323 tegra_sor_writel(sor, value, SOR_HEAD_STATE4(0));
1325 1324
1326 /* CSTM (LVDS, link A/B, upper) */ 1325 /* CSTM (LVDS, link A/B, upper) */
1327 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B | 1326 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B |
@@ -1386,7 +1385,7 @@ static void tegra_sor_encoder_disable(struct drm_encoder *encoder)
1386 goto unlock; 1385 goto unlock;
1387 } 1386 }
1388 1387
1389 tegra_sor_writel(sor, 0, SOR_STATE_1); 1388 tegra_sor_writel(sor, 0, SOR_STATE1);
1390 tegra_sor_update(sor); 1389 tegra_sor_update(sor);
1391 1390
1392 /* 1391 /*
diff --git a/drivers/gpu/drm/tegra/sor.h b/drivers/gpu/drm/tegra/sor.h
index a5f8853fedb5..561b03ba969d 100644
--- a/drivers/gpu/drm/tegra/sor.h
+++ b/drivers/gpu/drm/tegra/sor.h
@@ -11,9 +11,9 @@
11 11
12#define SOR_CTXSW 0x00 12#define SOR_CTXSW 0x00
13 13
14#define SOR_SUPER_STATE_0 0x01 14#define SOR_SUPER_STATE0 0x01
15 15
16#define SOR_SUPER_STATE_1 0x02 16#define SOR_SUPER_STATE1 0x02
17#define SOR_SUPER_STATE_ATTACHED (1 << 3) 17#define SOR_SUPER_STATE_ATTACHED (1 << 3)
18#define SOR_SUPER_STATE_MODE_NORMAL (1 << 2) 18#define SOR_SUPER_STATE_MODE_NORMAL (1 << 2)
19#define SOR_SUPER_STATE_HEAD_MODE_MASK (3 << 0) 19#define SOR_SUPER_STATE_HEAD_MODE_MASK (3 << 0)
@@ -21,9 +21,9 @@
21#define SOR_SUPER_STATE_HEAD_MODE_SNOOZE (1 << 0) 21#define SOR_SUPER_STATE_HEAD_MODE_SNOOZE (1 << 0)
22#define SOR_SUPER_STATE_HEAD_MODE_SLEEP (0 << 0) 22#define SOR_SUPER_STATE_HEAD_MODE_SLEEP (0 << 0)
23 23
24#define SOR_STATE_0 0x03 24#define SOR_STATE0 0x03
25 25
26#define SOR_STATE_1 0x04 26#define SOR_STATE1 0x04
27#define SOR_STATE_ASY_PIXELDEPTH_MASK (0xf << 17) 27#define SOR_STATE_ASY_PIXELDEPTH_MASK (0xf << 17)
28#define SOR_STATE_ASY_PIXELDEPTH_BPP_18_444 (0x2 << 17) 28#define SOR_STATE_ASY_PIXELDEPTH_BPP_18_444 (0x2 << 17)
29#define SOR_STATE_ASY_PIXELDEPTH_BPP_24_444 (0x5 << 17) 29#define SOR_STATE_ASY_PIXELDEPTH_BPP_24_444 (0x5 << 17)
@@ -33,19 +33,21 @@
33#define SOR_STATE_ASY_PROTOCOL_CUSTOM (0xf << 8) 33#define SOR_STATE_ASY_PROTOCOL_CUSTOM (0xf << 8)
34#define SOR_STATE_ASY_PROTOCOL_DP_A (0x8 << 8) 34#define SOR_STATE_ASY_PROTOCOL_DP_A (0x8 << 8)
35#define SOR_STATE_ASY_PROTOCOL_DP_B (0x9 << 8) 35#define SOR_STATE_ASY_PROTOCOL_DP_B (0x9 << 8)
36#define SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A (0x1 << 8)
36#define SOR_STATE_ASY_PROTOCOL_LVDS (0x0 << 8) 37#define SOR_STATE_ASY_PROTOCOL_LVDS (0x0 << 8)
37#define SOR_STATE_ASY_CRC_MODE_MASK (0x3 << 6) 38#define SOR_STATE_ASY_CRC_MODE_MASK (0x3 << 6)
38#define SOR_STATE_ASY_CRC_MODE_NON_ACTIVE (0x2 << 6) 39#define SOR_STATE_ASY_CRC_MODE_NON_ACTIVE (0x2 << 6)
39#define SOR_STATE_ASY_CRC_MODE_COMPLETE (0x1 << 6) 40#define SOR_STATE_ASY_CRC_MODE_COMPLETE (0x1 << 6)
40#define SOR_STATE_ASY_CRC_MODE_ACTIVE (0x0 << 6) 41#define SOR_STATE_ASY_CRC_MODE_ACTIVE (0x0 << 6)
42#define SOR_STATE_ASY_OWNER_MASK 0xf
41#define SOR_STATE_ASY_OWNER(x) (((x) & 0xf) << 0) 43#define SOR_STATE_ASY_OWNER(x) (((x) & 0xf) << 0)
42 44
43#define SOR_HEAD_STATE_0(x) (0x05 + (x)) 45#define SOR_HEAD_STATE0(x) (0x05 + (x))
44#define SOR_HEAD_STATE_1(x) (0x07 + (x)) 46#define SOR_HEAD_STATE1(x) (0x07 + (x))
45#define SOR_HEAD_STATE_2(x) (0x09 + (x)) 47#define SOR_HEAD_STATE2(x) (0x09 + (x))
46#define SOR_HEAD_STATE_3(x) (0x0b + (x)) 48#define SOR_HEAD_STATE3(x) (0x0b + (x))
47#define SOR_HEAD_STATE_4(x) (0x0d + (x)) 49#define SOR_HEAD_STATE4(x) (0x0d + (x))
48#define SOR_HEAD_STATE_5(x) (0x0f + (x)) 50#define SOR_HEAD_STATE5(x) (0x0f + (x))
49#define SOR_CRC_CNTRL 0x11 51#define SOR_CRC_CNTRL 0x11
50#define SOR_CRC_CNTRL_ENABLE (1 << 0) 52#define SOR_CRC_CNTRL_ENABLE (1 << 0)
51#define SOR_DP_DEBUG_MVID 0x12 53#define SOR_DP_DEBUG_MVID 0x12
@@ -75,39 +77,39 @@
75#define SOR_TEST_HEAD_MODE_MASK (3 << 8) 77#define SOR_TEST_HEAD_MODE_MASK (3 << 8)
76#define SOR_TEST_HEAD_MODE_AWAKE (2 << 8) 78#define SOR_TEST_HEAD_MODE_AWAKE (2 << 8)
77 79
78#define SOR_PLL_0 0x17 80#define SOR_PLL0 0x17
79#define SOR_PLL_0_ICHPMP_MASK (0xf << 24) 81#define SOR_PLL0_ICHPMP_MASK (0xf << 24)
80#define SOR_PLL_0_ICHPMP(x) (((x) & 0xf) << 24) 82#define SOR_PLL0_ICHPMP(x) (((x) & 0xf) << 24)
81#define SOR_PLL_0_VCOCAP_MASK (0xf << 8) 83#define SOR_PLL0_VCOCAP_MASK (0xf << 8)
82#define SOR_PLL_0_VCOCAP(x) (((x) & 0xf) << 8) 84#define SOR_PLL0_VCOCAP(x) (((x) & 0xf) << 8)
83#define SOR_PLL_0_VCOCAP_RST SOR_PLL_0_VCOCAP(3) 85#define SOR_PLL0_VCOCAP_RST SOR_PLL0_VCOCAP(3)
84#define SOR_PLL_0_PLLREG_MASK (0x3 << 6) 86#define SOR_PLL0_PLLREG_MASK (0x3 << 6)
85#define SOR_PLL_0_PLLREG_LEVEL(x) (((x) & 0x3) << 6) 87#define SOR_PLL0_PLLREG_LEVEL(x) (((x) & 0x3) << 6)
86#define SOR_PLL_0_PLLREG_LEVEL_V25 SOR_PLL_0_PLLREG_LEVEL(0) 88#define SOR_PLL0_PLLREG_LEVEL_V25 SOR_PLL0_PLLREG_LEVEL(0)
87#define SOR_PLL_0_PLLREG_LEVEL_V15 SOR_PLL_0_PLLREG_LEVEL(1) 89#define SOR_PLL0_PLLREG_LEVEL_V15 SOR_PLL0_PLLREG_LEVEL(1)
88#define SOR_PLL_0_PLLREG_LEVEL_V35 SOR_PLL_0_PLLREG_LEVEL(2) 90#define SOR_PLL0_PLLREG_LEVEL_V35 SOR_PLL0_PLLREG_LEVEL(2)
89#define SOR_PLL_0_PLLREG_LEVEL_V45 SOR_PLL_0_PLLREG_LEVEL(3) 91#define SOR_PLL0_PLLREG_LEVEL_V45 SOR_PLL0_PLLREG_LEVEL(3)
90#define SOR_PLL_0_PULLDOWN (1 << 5) 92#define SOR_PLL0_PULLDOWN (1 << 5)
91#define SOR_PLL_0_RESISTOR_EXT (1 << 4) 93#define SOR_PLL0_RESISTOR_EXT (1 << 4)
92#define SOR_PLL_0_VCOPD (1 << 2) 94#define SOR_PLL0_VCOPD (1 << 2)
93#define SOR_PLL_0_POWER_OFF (1 << 0) 95#define SOR_PLL0_PWR (1 << 0)
94 96
95#define SOR_PLL_1 0x18 97#define SOR_PLL1 0x18
96/* XXX: read-only bit? */ 98/* XXX: read-only bit? */
97#define SOR_PLL_1_TERM_COMPOUT (1 << 15) 99#define SOR_PLL1_TERM_COMPOUT (1 << 15)
98#define SOR_PLL_1_TMDS_TERM (1 << 8) 100#define SOR_PLL1_TMDS_TERM (1 << 8)
99 101
100#define SOR_PLL_2 0x19 102#define SOR_PLL2 0x19
101#define SOR_PLL_2_LVDS_ENABLE (1 << 25) 103#define SOR_PLL2_LVDS_ENABLE (1 << 25)
102#define SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE (1 << 24) 104#define SOR_PLL2_SEQ_PLLCAPPD_ENFORCE (1 << 24)
103#define SOR_PLL_2_PORT_POWERDOWN (1 << 23) 105#define SOR_PLL2_PORT_POWERDOWN (1 << 23)
104#define SOR_PLL_2_BANDGAP_POWERDOWN (1 << 22) 106#define SOR_PLL2_BANDGAP_POWERDOWN (1 << 22)
105#define SOR_PLL_2_POWERDOWN_OVERRIDE (1 << 18) 107#define SOR_PLL2_POWERDOWN_OVERRIDE (1 << 18)
106#define SOR_PLL_2_SEQ_PLLCAPPD (1 << 17) 108#define SOR_PLL2_SEQ_PLLCAPPD (1 << 17)
107 109
108#define SOR_PLL_3 0x1a 110#define SOR_PLL3 0x1a
109#define SOR_PLL_3_PLL_VDD_MODE_V1_8 (0 << 13) 111#define SOR_PLL3_PLL_VDD_MODE_1V8 (0 << 13)
110#define SOR_PLL_3_PLL_VDD_MODE_V3_3 (1 << 13) 112#define SOR_PLL3_PLL_VDD_MODE_3V3 (1 << 13)
111 113
112#define SOR_CSTM 0x1b 114#define SOR_CSTM 0x1b
113#define SOR_CSTM_LVDS (1 << 16) 115#define SOR_CSTM_LVDS (1 << 16)
@@ -116,10 +118,10 @@
116#define SOR_CSTM_UPPER (1 << 11) 118#define SOR_CSTM_UPPER (1 << 11)
117 119
118#define SOR_LVDS 0x1c 120#define SOR_LVDS 0x1c
119#define SOR_CRC_A 0x1d 121#define SOR_CRCA 0x1d
120#define SOR_CRC_A_VALID (1 << 0) 122#define SOR_CRCA_VALID (1 << 0)
121#define SOR_CRC_A_RESET (1 << 0) 123#define SOR_CRCA_RESET (1 << 0)
122#define SOR_CRC_B 0x1e 124#define SOR_CRCB 0x1e
123#define SOR_BLANK 0x1f 125#define SOR_BLANK 0x1f
124#define SOR_SEQ_CTL 0x20 126#define SOR_SEQ_CTL 0x20
125 127
@@ -140,32 +142,32 @@
140#define SOR_PWM_CTL_CLK_SEL (1 << 30) 142#define SOR_PWM_CTL_CLK_SEL (1 << 30)
141#define SOR_PWM_CTL_DUTY_CYCLE_MASK 0xffffff 143#define SOR_PWM_CTL_DUTY_CYCLE_MASK 0xffffff
142 144
143#define SOR_VCRC_A_0 0x34 145#define SOR_VCRC_A0 0x34
144#define SOR_VCRC_A_1 0x35 146#define SOR_VCRC_A1 0x35
145#define SOR_VCRC_B_0 0x36 147#define SOR_VCRC_B0 0x36
146#define SOR_VCRC_B_1 0x37 148#define SOR_VCRC_B1 0x37
147#define SOR_CCRC_A_0 0x38 149#define SOR_CCRC_A0 0x38
148#define SOR_CCRC_A_1 0x39 150#define SOR_CCRC_A1 0x39
149#define SOR_CCRC_B_0 0x3a 151#define SOR_CCRC_B0 0x3a
150#define SOR_CCRC_B_1 0x3b 152#define SOR_CCRC_B1 0x3b
151#define SOR_EDATA_A_0 0x3c 153#define SOR_EDATA_A0 0x3c
152#define SOR_EDATA_A_1 0x3d 154#define SOR_EDATA_A1 0x3d
153#define SOR_EDATA_B_0 0x3e 155#define SOR_EDATA_B0 0x3e
154#define SOR_EDATA_B_1 0x3f 156#define SOR_EDATA_B1 0x3f
155#define SOR_COUNT_A_0 0x40 157#define SOR_COUNT_A0 0x40
156#define SOR_COUNT_A_1 0x41 158#define SOR_COUNT_A1 0x41
157#define SOR_COUNT_B_0 0x42 159#define SOR_COUNT_B0 0x42
158#define SOR_COUNT_B_1 0x43 160#define SOR_COUNT_B1 0x43
159#define SOR_DEBUG_A_0 0x44 161#define SOR_DEBUG_A0 0x44
160#define SOR_DEBUG_A_1 0x45 162#define SOR_DEBUG_A1 0x45
161#define SOR_DEBUG_B_0 0x46 163#define SOR_DEBUG_B0 0x46
162#define SOR_DEBUG_B_1 0x47 164#define SOR_DEBUG_B1 0x47
163#define SOR_TRIG 0x48 165#define SOR_TRIG 0x48
164#define SOR_MSCHECK 0x49 166#define SOR_MSCHECK 0x49
165#define SOR_XBAR_CTRL 0x4a 167#define SOR_XBAR_CTRL 0x4a
166#define SOR_XBAR_POL 0x4b 168#define SOR_XBAR_POL 0x4b
167 169
168#define SOR_DP_LINKCTL_0 0x4c 170#define SOR_DP_LINKCTL0 0x4c
169#define SOR_DP_LINKCTL_LANE_COUNT_MASK (0x1f << 16) 171#define SOR_DP_LINKCTL_LANE_COUNT_MASK (0x1f << 16)
170#define SOR_DP_LINKCTL_LANE_COUNT(x) (((1 << (x)) - 1) << 16) 172#define SOR_DP_LINKCTL_LANE_COUNT(x) (((1 << (x)) - 1) << 16)
171#define SOR_DP_LINKCTL_ENHANCED_FRAME (1 << 14) 173#define SOR_DP_LINKCTL_ENHANCED_FRAME (1 << 14)
@@ -173,34 +175,34 @@
173#define SOR_DP_LINKCTL_TU_SIZE(x) (((x) & 0x7f) << 2) 175#define SOR_DP_LINKCTL_TU_SIZE(x) (((x) & 0x7f) << 2)
174#define SOR_DP_LINKCTL_ENABLE (1 << 0) 176#define SOR_DP_LINKCTL_ENABLE (1 << 0)
175 177
176#define SOR_DP_LINKCTL_1 0x4d 178#define SOR_DP_LINKCTL1 0x4d
177 179
178#define SOR_LANE_DRIVE_CURRENT_0 0x4e 180#define SOR_LANE_DRIVE_CURRENT0 0x4e
179#define SOR_LANE_DRIVE_CURRENT_1 0x4f 181#define SOR_LANE_DRIVE_CURRENT1 0x4f
180#define SOR_LANE4_DRIVE_CURRENT_0 0x50 182#define SOR_LANE4_DRIVE_CURRENT0 0x50
181#define SOR_LANE4_DRIVE_CURRENT_1 0x51 183#define SOR_LANE4_DRIVE_CURRENT1 0x51
182#define SOR_LANE_DRIVE_CURRENT_LANE3(x) (((x) & 0xff) << 24) 184#define SOR_LANE_DRIVE_CURRENT_LANE3(x) (((x) & 0xff) << 24)
183#define SOR_LANE_DRIVE_CURRENT_LANE2(x) (((x) & 0xff) << 16) 185#define SOR_LANE_DRIVE_CURRENT_LANE2(x) (((x) & 0xff) << 16)
184#define SOR_LANE_DRIVE_CURRENT_LANE1(x) (((x) & 0xff) << 8) 186#define SOR_LANE_DRIVE_CURRENT_LANE1(x) (((x) & 0xff) << 8)
185#define SOR_LANE_DRIVE_CURRENT_LANE0(x) (((x) & 0xff) << 0) 187#define SOR_LANE_DRIVE_CURRENT_LANE0(x) (((x) & 0xff) << 0)
186 188
187#define SOR_LANE_PREEMPHASIS_0 0x52 189#define SOR_LANE_PREEMPHASIS0 0x52
188#define SOR_LANE_PREEMPHASIS_1 0x53 190#define SOR_LANE_PREEMPHASIS1 0x53
189#define SOR_LANE4_PREEMPHASIS_0 0x54 191#define SOR_LANE4_PREEMPHASIS0 0x54
190#define SOR_LANE4_PREEMPHASIS_1 0x55 192#define SOR_LANE4_PREEMPHASIS1 0x55
191#define SOR_LANE_PREEMPHASIS_LANE3(x) (((x) & 0xff) << 24) 193#define SOR_LANE_PREEMPHASIS_LANE3(x) (((x) & 0xff) << 24)
192#define SOR_LANE_PREEMPHASIS_LANE2(x) (((x) & 0xff) << 16) 194#define SOR_LANE_PREEMPHASIS_LANE2(x) (((x) & 0xff) << 16)
193#define SOR_LANE_PREEMPHASIS_LANE1(x) (((x) & 0xff) << 8) 195#define SOR_LANE_PREEMPHASIS_LANE1(x) (((x) & 0xff) << 8)
194#define SOR_LANE_PREEMPHASIS_LANE0(x) (((x) & 0xff) << 0) 196#define SOR_LANE_PREEMPHASIS_LANE0(x) (((x) & 0xff) << 0)
195 197
196#define SOR_LANE_POST_CURSOR_0 0x56 198#define SOR_LANE_POSTCURSOR0 0x56
197#define SOR_LANE_POST_CURSOR_1 0x57 199#define SOR_LANE_POSTCURSOR1 0x57
198#define SOR_LANE_POST_CURSOR_LANE3(x) (((x) & 0xff) << 24) 200#define SOR_LANE_POSTCURSOR_LANE3(x) (((x) & 0xff) << 24)
199#define SOR_LANE_POST_CURSOR_LANE2(x) (((x) & 0xff) << 16) 201#define SOR_LANE_POSTCURSOR_LANE2(x) (((x) & 0xff) << 16)
200#define SOR_LANE_POST_CURSOR_LANE1(x) (((x) & 0xff) << 8) 202#define SOR_LANE_POSTCURSOR_LANE1(x) (((x) & 0xff) << 8)
201#define SOR_LANE_POST_CURSOR_LANE0(x) (((x) & 0xff) << 0) 203#define SOR_LANE_POSTCURSOR_LANE0(x) (((x) & 0xff) << 0)
202 204
203#define SOR_DP_CONFIG_0 0x58 205#define SOR_DP_CONFIG0 0x58
204#define SOR_DP_CONFIG_DISPARITY_NEGATIVE (1 << 31) 206#define SOR_DP_CONFIG_DISPARITY_NEGATIVE (1 << 31)
205#define SOR_DP_CONFIG_ACTIVE_SYM_ENABLE (1 << 26) 207#define SOR_DP_CONFIG_ACTIVE_SYM_ENABLE (1 << 26)
206#define SOR_DP_CONFIG_ACTIVE_SYM_POLARITY (1 << 24) 208#define SOR_DP_CONFIG_ACTIVE_SYM_POLARITY (1 << 24)
@@ -211,11 +213,11 @@
211#define SOR_DP_CONFIG_WATERMARK_MASK (0x3f << 0) 213#define SOR_DP_CONFIG_WATERMARK_MASK (0x3f << 0)
212#define SOR_DP_CONFIG_WATERMARK(x) (((x) & 0x3f) << 0) 214#define SOR_DP_CONFIG_WATERMARK(x) (((x) & 0x3f) << 0)
213 215
214#define SOR_DP_CONFIG_1 0x59 216#define SOR_DP_CONFIG1 0x59
215#define SOR_DP_MN_0 0x5a 217#define SOR_DP_MN0 0x5a
216#define SOR_DP_MN_1 0x5b 218#define SOR_DP_MN1 0x5b
217 219
218#define SOR_DP_PADCTL_0 0x5c 220#define SOR_DP_PADCTL0 0x5c
219#define SOR_DP_PADCTL_PAD_CAL_PD (1 << 23) 221#define SOR_DP_PADCTL_PAD_CAL_PD (1 << 23)
220#define SOR_DP_PADCTL_TX_PU_ENABLE (1 << 22) 222#define SOR_DP_PADCTL_TX_PU_ENABLE (1 << 22)
221#define SOR_DP_PADCTL_TX_PU_MASK (0xff << 8) 223#define SOR_DP_PADCTL_TX_PU_MASK (0xff << 8)
@@ -229,17 +231,17 @@
229#define SOR_DP_PADCTL_PD_TXD_1 (1 << 1) 231#define SOR_DP_PADCTL_PD_TXD_1 (1 << 1)
230#define SOR_DP_PADCTL_PD_TXD_2 (1 << 0) 232#define SOR_DP_PADCTL_PD_TXD_2 (1 << 0)
231 233
232#define SOR_DP_PADCTL_1 0x5d 234#define SOR_DP_PADCTL1 0x5d
233 235
234#define SOR_DP_DEBUG_0 0x5e 236#define SOR_DP_DEBUG0 0x5e
235#define SOR_DP_DEBUG_1 0x5f 237#define SOR_DP_DEBUG1 0x5f
236 238
237#define SOR_DP_SPARE_0 0x60 239#define SOR_DP_SPARE0 0x60
238#define SOR_DP_SPARE_MACRO_SOR_CLK (1 << 2) 240#define SOR_DP_SPARE_MACRO_SOR_CLK (1 << 2)
239#define SOR_DP_SPARE_PANEL_INTERNAL (1 << 1) 241#define SOR_DP_SPARE_PANEL_INTERNAL (1 << 1)
240#define SOR_DP_SPARE_SEQ_ENABLE (1 << 0) 242#define SOR_DP_SPARE_SEQ_ENABLE (1 << 0)
241 243
242#define SOR_DP_SPARE_1 0x61 244#define SOR_DP_SPARE1 0x61
243#define SOR_DP_AUDIO_CTRL 0x62 245#define SOR_DP_AUDIO_CTRL 0x62
244 246
245#define SOR_DP_AUDIO_HBLANK_SYMBOLS 0x63 247#define SOR_DP_AUDIO_HBLANK_SYMBOLS 0x63
@@ -249,13 +251,13 @@
249#define SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK (0x1fffff << 0) 251#define SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK (0x1fffff << 0)
250 252
251#define SOR_DP_GENERIC_INFOFRAME_HEADER 0x65 253#define SOR_DP_GENERIC_INFOFRAME_HEADER 0x65
252#define SOR_DP_GENERIC_INFOFRAME_SUBPACK_0 0x66 254#define SOR_DP_GENERIC_INFOFRAME_SUBPACK0 0x66
253#define SOR_DP_GENERIC_INFOFRAME_SUBPACK_1 0x67 255#define SOR_DP_GENERIC_INFOFRAME_SUBPACK1 0x67
254#define SOR_DP_GENERIC_INFOFRAME_SUBPACK_2 0x68 256#define SOR_DP_GENERIC_INFOFRAME_SUBPACK2 0x68
255#define SOR_DP_GENERIC_INFOFRAME_SUBPACK_3 0x69 257#define SOR_DP_GENERIC_INFOFRAME_SUBPACK3 0x69
256#define SOR_DP_GENERIC_INFOFRAME_SUBPACK_4 0x6a 258#define SOR_DP_GENERIC_INFOFRAME_SUBPACK4 0x6a
257#define SOR_DP_GENERIC_INFOFRAME_SUBPACK_5 0x6b 259#define SOR_DP_GENERIC_INFOFRAME_SUBPACK5 0x6b
258#define SOR_DP_GENERIC_INFOFRAME_SUBPACK_6 0x6c 260#define SOR_DP_GENERIC_INFOFRAME_SUBPACK6 0x6c
259 261
260#define SOR_DP_TPG 0x6d 262#define SOR_DP_TPG 0x6d
261#define SOR_DP_TPG_CHANNEL_CODING (1 << 6) 263#define SOR_DP_TPG_CHANNEL_CODING (1 << 6)
@@ -275,8 +277,8 @@
275#define SOR_DP_TPG_PATTERN_NONE (0x0 << 0) 277#define SOR_DP_TPG_PATTERN_NONE (0x0 << 0)
276 278
277#define SOR_DP_TPG_CONFIG 0x6e 279#define SOR_DP_TPG_CONFIG 0x6e
278#define SOR_DP_LQ_CSTM_0 0x6f 280#define SOR_DP_LQ_CSTM0 0x6f
279#define SOR_DP_LQ_CSTM_1 0x70 281#define SOR_DP_LQ_CSTM1 0x70
280#define SOR_DP_LQ_CSTM_2 0x71 282#define SOR_DP_LQ_CSTM2 0x71
281 283
282#endif 284#endif
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-04 15:29:04 -0500