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-rw-r--r--drivers/gpu/drm/amd/amdgpu/Makefile2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c220
-rw-r--r--drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h49
3 files changed, 270 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index 660786aba7d2..20f88276dfda 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -34,7 +34,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \
34amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce_v6_0.o si_dpm.o si_smc.o 34amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce_v6_0.o si_dpm.o si_smc.o
35 35
36amdgpu-y += \ 36amdgpu-y += \
37 vi.o mxgpu_vi.o nbio_v6_1.o soc15.o mxgpu_ai.o 37 vi.o mxgpu_vi.o nbio_v6_1.o soc15.o mxgpu_ai.o nbio_v7_0.o
38 38
39# add GMC block 39# add GMC block
40amdgpu-y += \ 40amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
new file mode 100644
index 000000000000..7e1206d1df6a
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
@@ -0,0 +1,220 @@
1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "amdgpu.h"
24#include "amdgpu_atombios.h"
25#include "nbio_v7_0.h"
26
27#include "vega10/soc15ip.h"
28#include "raven1/NBIO/nbio_7_0_default.h"
29#include "raven1/NBIO/nbio_7_0_offset.h"
30#include "raven1/NBIO/nbio_7_0_sh_mask.h"
31#include "vega10/vega10_enum.h"
32
33#define smnNBIF_MGCG_CTRL_LCLK 0x1013a05c
34
35u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev)
36{
37 u32 tmp = RREG32(SOC15_REG_OFFSET(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0));
38
39 tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
40 tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
41
42 return tmp;
43}
44
45u32 nbio_v7_0_get_atombios_scratch_regs(struct amdgpu_device *adev,
46 uint32_t idx)
47{
48 return RREG32(SOC15_REG_OFFSET(NBIO, 0, mmBIOS_SCRATCH_0) + idx);
49}
50
51void nbio_v7_0_set_atombios_scratch_regs(struct amdgpu_device *adev,
52 uint32_t idx, uint32_t val)
53{
54 WREG32(SOC15_REG_OFFSET(NBIO, 0, mmBIOS_SCRATCH_0) + idx, val);
55}
56
57void nbio_v7_0_mc_access_enable(struct amdgpu_device *adev, bool enable)
58{
59 if (enable)
60 WREG32(SOC15_REG_OFFSET(NBIO, 0, mmBIF_FB_EN),
61 BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
62 else
63 WREG32(SOC15_REG_OFFSET(NBIO, 0, mmBIF_FB_EN), 0);
64}
65
66void nbio_v7_0_hdp_flush(struct amdgpu_device *adev)
67{
68 WREG32(SOC15_REG_OFFSET(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0);
69}
70
71u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev)
72{
73 return RREG32(SOC15_REG_OFFSET(NBIO, 0, mmRCC_CONFIG_MEMSIZE));
74}
75
76static const u32 nbio_sdma_doorbell_range_reg[] =
77{
78 SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE),
79 SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE)
80};
81
82void nbio_v7_0_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
83 bool use_doorbell, int doorbell_index)
84{
85 u32 doorbell_range = RREG32(nbio_sdma_doorbell_range_reg[instance]);
86
87 if (use_doorbell) {
88 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
89 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 2);
90 } else
91 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
92
93 WREG32(nbio_sdma_doorbell_range_reg[instance], doorbell_range);
94}
95
96void nbio_v7_0_enable_doorbell_aperture(struct amdgpu_device *adev,
97 bool enable)
98{
99 u32 tmp;
100
101 tmp = RREG32(SOC15_REG_OFFSET(NBIO, 0, mmRCC_DOORBELL_APER_EN));
102 if (enable)
103 tmp = REG_SET_FIELD(tmp, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 1);
104 else
105 tmp = REG_SET_FIELD(tmp, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 0);
106
107 WREG32(SOC15_REG_OFFSET(NBIO, 0, mmRCC_DOORBELL_APER_EN), tmp);
108}
109
110void nbio_v7_0_ih_doorbell_range(struct amdgpu_device *adev,
111 bool use_doorbell, int doorbell_index)
112{
113 u32 ih_doorbell_range = RREG32(SOC15_REG_OFFSET(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE));
114
115 if (use_doorbell) {
116 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
117 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2);
118 } else
119 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);
120
121 WREG32(SOC15_REG_OFFSET(NBIO, 0, mmBIF_IH_DOORBELL_RANGE), ih_doorbell_range);
122}
123
124static uint32_t nbio_7_0_read_syshub_ind_mmr(struct amdgpu_device *adev, uint32_t offset)
125{
126 uint32_t data;
127
128 WREG32(SOC15_REG_OFFSET(NBIO, 0, mmSYSHUB_INDEX), offset);
129 data = RREG32(SOC15_REG_OFFSET(NBIO, 0, mmSYSHUB_DATA));
130
131 return data;
132}
133
134static void nbio_7_0_write_syshub_ind_mmr(struct amdgpu_device *adev, uint32_t offset,
135 uint32_t data)
136{
137 WREG32(SOC15_REG_OFFSET(NBIO, 0, mmSYSHUB_INDEX), offset);
138 WREG32(SOC15_REG_OFFSET(NBIO, 0, mmSYSHUB_DATA), data);
139}
140
141void nbio_v7_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
142 bool enable)
143{
144 uint32_t def, data;
145
146 /* NBIF_MGCG_CTRL_LCLK */
147 def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK);
148
149 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
150 data |= NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK;
151 else
152 data &= ~NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK;
153
154 if (def != data)
155 WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data);
156
157 /* SYSHUB_MGCG_CTRL_SOCCLK */
158 def = data = nbio_7_0_read_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK);
159
160 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
161 data |= SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK;
162 else
163 data &= ~SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK;
164
165 if (def != data)
166 nbio_7_0_write_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK, data);
167
168 /* SYSHUB_MGCG_CTRL_SHUBCLK */
169 def = data = nbio_7_0_read_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK);
170
171 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
172 data |= SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK_MASK;
173 else
174 data &= ~SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK_MASK;
175
176 if (def != data)
177 nbio_7_0_write_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK, data);
178}
179
180void nbio_v7_0_ih_control(struct amdgpu_device *adev)
181{
182 u32 interrupt_cntl;
183
184 /* setup interrupt control */
185 WREG32(SOC15_REG_OFFSET(NBIO, 0, mmINTERRUPT_CNTL2), adev->dummy_page.addr >> 8);
186 interrupt_cntl = RREG32(SOC15_REG_OFFSET(NBIO, 0, mmINTERRUPT_CNTL));
187 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
188 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
189 */
190 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
191 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
192 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
193 WREG32(SOC15_REG_OFFSET(NBIO, 0, mmINTERRUPT_CNTL), interrupt_cntl);
194}
195
196struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg;
197struct nbio_pcie_index_data nbio_v7_0_pcie_index_data;
198
199int nbio_v7_0_init(struct amdgpu_device *adev)
200{
201 nbio_v7_0_hdp_flush_reg.hdp_flush_req_offset = SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ);
202 nbio_v7_0_hdp_flush_reg.hdp_flush_done_offset = SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE);
203 nbio_v7_0_hdp_flush_reg.ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK;
204 nbio_v7_0_hdp_flush_reg.ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK;
205 nbio_v7_0_hdp_flush_reg.ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK;
206 nbio_v7_0_hdp_flush_reg.ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK;
207 nbio_v7_0_hdp_flush_reg.ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK;
208 nbio_v7_0_hdp_flush_reg.ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK;
209 nbio_v7_0_hdp_flush_reg.ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK;
210 nbio_v7_0_hdp_flush_reg.ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK;
211 nbio_v7_0_hdp_flush_reg.ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK;
212 nbio_v7_0_hdp_flush_reg.ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK;
213 nbio_v7_0_hdp_flush_reg.ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK;
214 nbio_v7_0_hdp_flush_reg.ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK;
215
216 nbio_v7_0_pcie_index_data.index_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
217 nbio_v7_0_pcie_index_data.data_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
218
219 return 0;
220}
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h
new file mode 100644
index 000000000000..054ff49427e6
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h
@@ -0,0 +1,49 @@
1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef __NBIO_V7_0_H__
25#define __NBIO_V7_0_H__
26
27#include "soc15_common.h"
28
29extern struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg;
30extern struct nbio_pcie_index_data nbio_v7_0_pcie_index_data;
31int nbio_v7_0_init(struct amdgpu_device *adev);
32u32 nbio_v7_0_get_atombios_scratch_regs(struct amdgpu_device *adev,
33 uint32_t idx);
34void nbio_v7_0_set_atombios_scratch_regs(struct amdgpu_device *adev,
35 uint32_t idx, uint32_t val);
36void nbio_v7_0_mc_access_enable(struct amdgpu_device *adev, bool enable);
37void nbio_v7_0_hdp_flush(struct amdgpu_device *adev);
38u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev);
39void nbio_v7_0_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
40 bool use_doorbell, int doorbell_index);
41void nbio_v7_0_enable_doorbell_aperture(struct amdgpu_device *adev,
42 bool enable);
43void nbio_v7_0_ih_doorbell_range(struct amdgpu_device *adev,
44 bool use_doorbell, int doorbell_index);
45void nbio_v7_0_ih_control(struct amdgpu_device *adev);
46u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev);
47void nbio_v7_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
48 bool enable);
49#endif
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-08 21:42:33 -0500