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-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v11_0.c5
1 files changed, 2 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index c90408bc0fde..d4bf133908b1 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -307,11 +307,10 @@ static void dce_v11_0_page_flip(struct amdgpu_device *adev,
307 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 307 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
308 u32 tmp; 308 u32 tmp;
309 309
310 /* flip at hsync for async, default is vsync */ 310 /* flip immediate for async, default is vsync */
311 /* use UPDATE_IMMEDIATE_EN instead for async? */
312 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); 311 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
313 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, 312 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
314 GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0); 313 GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0);
315 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 314 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
316 /* update the scanout addresses */ 315 /* update the scanout addresses */
317 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 316 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,