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-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 0637349f9b65..ba36db8002e7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4346,7 +4346,7 @@ static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
4346 struct amdgpu_ring *ring; 4346 struct amdgpu_ring *ring;
4347 u32 tmp; 4347 u32 tmp;
4348 u32 rb_bufsz; 4348 u32 rb_bufsz;
4349 u64 rb_addr, rptr_addr; 4349 u64 rb_addr, rptr_addr, wptr_gpu_addr;
4350 int r; 4350 int r;
4351 4351
4352 /* Set the write pointer delay */ 4352 /* Set the write pointer delay */
@@ -4377,6 +4377,9 @@ static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
4377 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 4377 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
4378 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 4378 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
4379 4379
4380 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
4381 WREG32(mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
4382 WREG32(mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));
4380 mdelay(1); 4383 mdelay(1);
4381 WREG32(mmCP_RB0_CNTL, tmp); 4384 WREG32(mmCP_RB0_CNTL, tmp);
4382 4385