29 files changed, 170 insertions, 131 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
index 236d9950221b..c0d8c6ff6380 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
@@ -425,10 +425,15 @@ bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj)
 
 void amdgpu_fbdev_restore_mode(struct amdgpu_device *adev)
 {
-        struct amdgpu_fbdev *afbdev = adev->mode_info.rfbdev;
+        struct amdgpu_fbdev *afbdev;
         struct drm_fb_helper *fb_helper;
         int ret;
 
+        if (!adev)
+                return;
+
+        afbdev = adev->mode_info.rfbdev;
+
         if (!afbdev)
                 return;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 749a6cde7985..83c172a6e938 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -635,7 +635,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job)
                 mutex_unlock(&id_mgr->lock);
         }
 
-        if (gds_switch_needed) {
+        if (ring->funcs->emit_gds_switch && gds_switch_needed) {
                 id->gds_base = job->gds_base;
                 id->gds_size = job->gds_size;
                 id->gws_base = job->gws_base;
@@ -673,6 +673,7 @@ void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vmhub,
         struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub];
         struct amdgpu_vm_id *id = &id_mgr->ids[vmid];
 
+        atomic64_set(&id->owner, 0);
         id->gds_base = 0;
         id->gds_size = 0;
         id->gws_base = 0;
@@ -682,6 +683,26 @@ void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vmhub,
 }
 
 /**
+ * amdgpu_vm_reset_all_id - reset VMID to zero
+ *
+ * @adev: amdgpu device structure
+ *
+ * Reset VMID to force flush on next use
+ */
+void amdgpu_vm_reset_all_ids(struct amdgpu_device *adev)
+{
+        unsigned i, j;
+
+        for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
+                struct amdgpu_vm_id_manager *id_mgr =
+                        &adev->vm_manager.id_mgr[i];
+
+                for (j = 1; j < id_mgr->num_ids; ++j)
+                        amdgpu_vm_reset_id(adev, i, j);
+        }
+}
+
+/**
  * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
  *
  * @vm: requested vm
@@ -2271,7 +2292,6 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev)
         for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
                 adev->vm_manager.seqno[i] = 0;
 
-
         atomic_set(&adev->vm_manager.vm_pte_next_ring, 0);
         atomic64_set(&adev->vm_manager.client_counter, 0);
         spin_lock_init(&adev->vm_manager.prt_lock);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index d97e28b4bdc4..e1d951ece433 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -204,6 +204,7 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job);
 void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vmhub,
                         unsigned vmid);
+void amdgpu_vm_reset_all_ids(struct amdgpu_device *adev);
 int amdgpu_vm_update_directories(struct amdgpu_device *adev,
                                  struct amdgpu_vm *vm);
 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
index 00e56a28b593..cb508a211b2f 100644
--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
@@ -906,6 +906,12 @@ static bool ci_dpm_vblank_too_short(struct amdgpu_device *adev)
         u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
         u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 300;
 
+        /* disable mclk switching if the refresh is >120Hz, even if the
+         * blanking period would allow it
+         */
+        if (amdgpu_dpm_get_vrefresh(adev) > 120)
+                return true;
+
         if (vblank_time < switch_limit)
                 return true;
         else
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index 2a3983036a30..9776ad3d2d71 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -950,10 +950,6 @@ static int gmc_v6_0_suspend(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-        if (adev->vm_manager.enabled) {
-                gmc_v6_0_vm_fini(adev);
-                adev->vm_manager.enabled = false;
-        }
         gmc_v6_0_hw_fini(adev);
 
         return 0;
@@ -968,16 +964,9 @@ static int gmc_v6_0_resume(void *handle)
         if (r)
                 return r;
 
-        if (!adev->vm_manager.enabled) {
-                r = gmc_v6_0_vm_init(adev);
-                if (r) {
-                        dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
-                        return r;
-                }
-                adev->vm_manager.enabled = true;
-        }
+        amdgpu_vm_reset_all_ids(adev);
 
-        return r;
+        return 0;
 }
 
 static bool gmc_v6_0_is_idle(void *handle)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 6d347c1d2516..fca8e77182c9 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -1117,10 +1117,6 @@ static int gmc_v7_0_suspend(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-        if (adev->vm_manager.enabled) {
-                gmc_v7_0_vm_fini(adev);
-                adev->vm_manager.enabled = false;
-        }
         gmc_v7_0_hw_fini(adev);
 
         return 0;
@@ -1135,16 +1131,9 @@ static int gmc_v7_0_resume(void *handle)
         if (r)
                 return r;
 
-        if (!adev->vm_manager.enabled) {
-                r = gmc_v7_0_vm_init(adev);
-                if (r) {
-                        dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
-                        return r;
-                }
-                adev->vm_manager.enabled = true;
-        }
+        amdgpu_vm_reset_all_ids(adev);
 
-        return r;
+        return 0;
 }
 
 static bool gmc_v7_0_is_idle(void *handle)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 2784ff49cf56..e9c127037b39 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -1209,10 +1209,6 @@ static int gmc_v8_0_suspend(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-        if (adev->vm_manager.enabled) {
-                gmc_v8_0_vm_fini(adev);
-                adev->vm_manager.enabled = false;
-        }
         gmc_v8_0_hw_fini(adev);
 
         return 0;
@@ -1227,16 +1223,9 @@ static int gmc_v8_0_resume(void *handle)
         if (r)
                 return r;
 
-        if (!adev->vm_manager.enabled) {
-                r = gmc_v8_0_vm_init(adev);
-                if (r) {
-                        dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
-                        return r;
-                }
-                adev->vm_manager.enabled = true;
-        }
+        amdgpu_vm_reset_all_ids(adev);
 
-        return r;
+        return 0;
 }
 
 static bool gmc_v8_0_is_idle(void *handle)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index dc1e1c1d6b24..f936332a069d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -791,10 +791,6 @@ static int gmc_v9_0_suspend(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-        if (adev->vm_manager.enabled) {
-                gmc_v9_0_vm_fini(adev);
-                adev->vm_manager.enabled = false;
-        }
         gmc_v9_0_hw_fini(adev);
 
         return 0;
@@ -809,17 +805,9 @@ static int gmc_v9_0_resume(void *handle)
         if (r)
                 return r;
 
-        if (!adev->vm_manager.enabled) {
-                r = gmc_v9_0_vm_init(adev);
-                if (r) {
-                        dev_err(adev->dev,
-                                "vm manager initialization failed (%d).\n", r);
-                        return r;
-                }
-                adev->vm_manager.enabled = true;
-        }
+        amdgpu_vm_reset_all_ids(adev);
 
-        return r;
+        return 0;
 }
 
 static bool gmc_v9_0_is_idle(void *handle)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 975567f6813d..1f01020ce3a9 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -2655,6 +2655,28 @@ static int smu7_get_power_state_size(struct pp_hwmgr *hwmgr)
         return sizeof(struct smu7_power_state);
 }
 
+static int smu7_vblank_too_short(struct pp_hwmgr *hwmgr,
+                                 uint32_t vblank_time_us)
+{
+        struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+        uint32_t switch_limit_us;
+
+        switch (hwmgr->chip_id) {
+        case CHIP_POLARIS10:
+        case CHIP_POLARIS11:
+        case CHIP_POLARIS12:
+                switch_limit_us = data->is_memory_gddr5 ? 190 : 150;
+                break;
+        default:
+                switch_limit_us = data->is_memory_gddr5 ? 450 : 150;
+                break;
+        }
+
+        if (vblank_time_us < switch_limit_us)
+                return true;
+        else
+                return false;
+}
 
 static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
                                 struct pp_power_state *request_ps,
@@ -2669,6 +2691,7 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
         bool disable_mclk_switching;
         bool disable_mclk_switching_for_frame_lock;
         struct cgs_display_info info = {0};
+        struct cgs_mode_info mode_info = {0};
         const struct phm_clock_and_voltage_limits *max_limits;
         uint32_t i;
         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
@@ -2677,6 +2700,7 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
         int32_t count;
         int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
 
+        info.mode_info = &mode_info;
         data->battery_state = (PP_StateUILabel_Battery ==
                         request_ps->classification.ui_label);
 
@@ -2703,8 +2727,6 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
 
         cgs_get_active_displays_info(hwmgr->device, &info);
 
-        /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
-
         minimum_clocks.engineClock = hwmgr->display_config.min_core_set_clock;
         minimum_clocks.memoryClock = hwmgr->display_config.min_mem_set_clock;
 
@@ -2769,8 +2791,10 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
                                     PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
 
 
-        disable_mclk_switching = (1 < info.display_count) ||
-                                    disable_mclk_switching_for_frame_lock;
+        disable_mclk_switching = ((1 < info.display_count) ||
+                                  disable_mclk_switching_for_frame_lock ||
+                                  smu7_vblank_too_short(hwmgr, mode_info.vblank_time_us) ||
+                                  (mode_info.refresh_rate > 120));
 
         sclk = smu7_ps->performance_levels[0].engine_clock;
         mclk = smu7_ps->performance_levels[0].memory_clock;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index cd7bf6d3859a..ab17350e853d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -4187,7 +4187,7 @@ static int vega10_force_clock_level(struct pp_hwmgr *hwmgr,
                 enum pp_clock_type type, uint32_t mask)
 {
         struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
-        uint32_t i;
+        int i;
 
         if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
                 return -EINVAL;
diff --git a/drivers/gpu/drm/arm/hdlcd_crtc.c b/drivers/gpu/drm/arm/hdlcd_crtc.c
index 798a3cc480a2..1a3359c0f6cd 100644
--- a/drivers/gpu/drm/arm/hdlcd_crtc.c
+++ b/drivers/gpu/drm/arm/hdlcd_crtc.c
@@ -10,6 +10,7 @@
  */
 
 #include <drm/drmP.h>
+#include <drm/drm_atomic.h>
 #include <drm/drm_atomic_helper.h>
 #include <drm/drm_crtc.h>
 #include <drm/drm_crtc_helper.h>
@@ -226,16 +227,33 @@ static const struct drm_crtc_helper_funcs hdlcd_crtc_helper_funcs = {
 static int hdlcd_plane_atomic_check(struct drm_plane *plane,
                                     struct drm_plane_state *state)
 {
-        u32 src_w, src_h;
+        struct drm_rect clip = { 0 };
+        struct drm_crtc_state *crtc_state;
+        u32 src_h = state->src_h >> 16;
 
-        src_w = state->src_w >> 16;
-        src_h = state->src_h >> 16;
+        /* only the HDLCD_REG_FB_LINE_COUNT register has a limit */
+        if (src_h >= HDLCD_MAX_YRES) {
+                DRM_DEBUG_KMS("Invalid source width: %d\n", src_h);
+                return -EINVAL;
+        }
+
+        if (!state->fb || !state->crtc)
+                return 0;
 
-        /* we can't do any scaling of the plane source */
-        if ((src_w != state->crtc_w) || (src_h != state->crtc_h))
+        crtc_state = drm_atomic_get_existing_crtc_state(state->state,
+                                                        state->crtc);
+        if (!crtc_state) {
+                DRM_DEBUG_KMS("Invalid crtc state\n");
                 return -EINVAL;
+        }
 
-        return 0;
+        clip.x2 = crtc_state->adjusted_mode.hdisplay;
+        clip.y2 = crtc_state->adjusted_mode.vdisplay;
+
+        return drm_plane_helper_check_state(state, &clip,
+                                            DRM_PLANE_HELPER_NO_SCALING,
+                                            DRM_PLANE_HELPER_NO_SCALING,
+                                            false, true);
 }
 
 static void hdlcd_plane_atomic_update(struct drm_plane *plane,
@@ -244,21 +262,20 @@ static void hdlcd_plane_atomic_update(struct drm_plane *plane,
         struct drm_framebuffer *fb = plane->state->fb;
         struct hdlcd_drm_private *hdlcd;
         struct drm_gem_cma_object *gem;
-        u32 src_w, src_h, dest_w, dest_h;
+        u32 src_x, src_y, dest_h;
         dma_addr_t scanout_start;
 
         if (!fb)
                 return;
 
-        src_w = plane->state->src_w >> 16;
-        src_h = plane->state->src_h >> 16;
-        dest_w = plane->state->crtc_w;
-        dest_h = plane->state->crtc_h;
+        src_x = plane->state->src.x1 >> 16;
+        src_y = plane->state->src.y1 >> 16;
+        dest_h = drm_rect_height(&plane->state->dst);
         gem = drm_fb_cma_get_gem_obj(fb, 0);
+
         scanout_start = gem->paddr + fb->offsets[0] +
-                plane->state->crtc_y * fb->pitches[0] +
-                plane->state->crtc_x *
-                fb->format->cpp[0];
+                        src_y * fb->pitches[0] +
+                        src_x * fb->format->cpp[0];
 
         hdlcd = plane->dev->dev_private;
         hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_LENGTH, fb->pitches[0]);
@@ -305,7 +322,6 @@ static struct drm_plane *hdlcd_plane_init(struct drm_device *drm)
                                        formats, ARRAY_SIZE(formats),
                                        DRM_PLANE_TYPE_PRIMARY, NULL);
         if (ret) {
-                devm_kfree(drm->dev, plane);
                 return ERR_PTR(ret);
         }
 
@@ -329,7 +345,6 @@ int hdlcd_setup_crtc(struct drm_device *drm)
                                         &hdlcd_crtc_funcs, NULL);
         if (ret) {
                 hdlcd_plane_destroy(primary);
-                devm_kfree(drm->dev, primary);
                 return ret;
         }
 
diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c
index 65a3bd7a0c00..423dda2785d4 100644
--- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c
+++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c
@@ -152,8 +152,7 @@ static const struct drm_connector_funcs atmel_hlcdc_panel_connector_funcs = {
         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 };
 
-static int atmel_hlcdc_attach_endpoint(struct drm_device *dev,
-                                       const struct device_node *np)
+static int atmel_hlcdc_attach_endpoint(struct drm_device *dev, int endpoint)
 {
         struct atmel_hlcdc_dc *dc = dev->dev_private;
         struct atmel_hlcdc_rgb_output *output;
@@ -161,6 +160,11 @@ static int atmel_hlcdc_attach_endpoint(struct drm_device *dev,
         struct drm_bridge *bridge;
         int ret;
 
+        ret = drm_of_find_panel_or_bridge(dev->dev->of_node, 0, endpoint,
+                                          &panel, &bridge);
+        if (ret)
+                return ret;
+
         output = devm_kzalloc(dev->dev, sizeof(*output), GFP_KERNEL);
         if (!output)
                 return -EINVAL;
@@ -177,10 +181,6 @@ static int atmel_hlcdc_attach_endpoint(struct drm_device *dev,
 
         output->encoder.possible_crtcs = 0x1;
 
-        ret = drm_of_find_panel_or_bridge(np, 0, 0, &panel, &bridge);
-        if (ret)
-                return ret;
-
         if (panel) {
                 output->connector.dpms = DRM_MODE_DPMS_OFF;
                 output->connector.polled = DRM_CONNECTOR_POLL_CONNECT;
@@ -220,22 +220,14 @@ err_encoder_cleanup:
 
 int atmel_hlcdc_create_outputs(struct drm_device *dev)
 {
-        struct device_node *remote;
-        int ret = -ENODEV;
-        int endpoint = 0;
-
-        while (true) {
-                /* Loop thru possible multiple connections to the output */
-                remote = of_graph_get_remote_node(dev->dev->of_node, 0,
-                                                  endpoint++);
-                if (!remote)
-                        break;
-
-                ret = atmel_hlcdc_attach_endpoint(dev, remote);
-                of_node_put(remote);
-                if (ret)
-                        return ret;
-        }
+        int endpoint, ret = 0;
+
+        for (endpoint = 0; !ret; endpoint++)
+                ret = atmel_hlcdc_attach_endpoint(dev, endpoint);
+
+        /* At least one device was successfully attached.*/
+        if (ret == -ENODEV && endpoint)
+                return 0;
 
         return ret;
 }
diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c
index fedd4d60d9cd..5dc8c4350602 100644
--- a/drivers/gpu/drm/drm_plane.c
+++ b/drivers/gpu/drm/drm_plane.c
@@ -948,8 +948,6 @@ retry:
         }
 
 out:
-        if (ret && crtc->funcs->page_flip_target)
-                drm_crtc_vblank_put(crtc);
         if (fb)
                 drm_framebuffer_put(fb);
         if (crtc->primary->old_fb)
@@ -964,5 +962,8 @@ out:
         drm_modeset_drop_locks(&ctx);
         drm_modeset_acquire_fini(&ctx);
 
+        if (ret && crtc->funcs->page_flip_target)
+                drm_crtc_vblank_put(crtc);
+
         return ret;
 }
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c b/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c
index a13930e1d8c9..ee7069e93eda 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c
@@ -44,6 +44,7 @@ static struct etnaviv_gem_submit *submit_create(struct drm_device *dev,
 
                 /* initially, until copy_from_user() and bo lookup succeeds: */
                 submit->nr_bos = 0;
+                submit->fence = NULL;
 
                 ww_acquire_init(&submit->ticket, &reservation_ww_class);
         }
@@ -294,7 +295,8 @@ static void submit_cleanup(struct etnaviv_gem_submit *submit)
         }
 
         ww_acquire_fini(&submit->ticket);
-        dma_fence_put(submit->fence);
+        if (submit->fence)
+                dma_fence_put(submit->fence);
         kfree(submit);
 }
 
diff --git a/drivers/gpu/drm/gma500/psb_intel_lvds.c b/drivers/gpu/drm/gma500/psb_intel_lvds.c
index 0066fe7e622e..be3eefec5152 100644
--- a/drivers/gpu/drm/gma500/psb_intel_lvds.c
+++ b/drivers/gpu/drm/gma500/psb_intel_lvds.c
@@ -759,20 +759,23 @@ void psb_intel_lvds_init(struct drm_device *dev,
                 if (scan->type & DRM_MODE_TYPE_PREFERRED) {
                         mode_dev->panel_fixed_mode =
                             drm_mode_duplicate(dev, scan);
+                        DRM_DEBUG_KMS("Using mode from DDC\n");
                         goto out;       /* FIXME: check for quirks */
                 }
         }
 
         /* Failed to get EDID, what about VBT? do we need this? */
-        if (mode_dev->vbt_mode)
+        if (dev_priv->lfp_lvds_vbt_mode) {
                 mode_dev->panel_fixed_mode =
-                    drm_mode_duplicate(dev, mode_dev->vbt_mode);
+                        drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
 
-        if (!mode_dev->panel_fixed_mode)
-                if (dev_priv->lfp_lvds_vbt_mode)
-                        mode_dev->panel_fixed_mode =
-                                drm_mode_duplicate(dev,
-                                        dev_priv->lfp_lvds_vbt_mode);
+                if (mode_dev->panel_fixed_mode) {
+                        mode_dev->panel_fixed_mode->type |=
+                                DRM_MODE_TYPE_PREFERRED;
+                        DRM_DEBUG_KMS("Using mode from VBT\n");
+                        goto out;
+                }
+        }
 
         /*
          * If we didn't get EDID, try checking if the panel is already turned
@@ -789,6 +792,7 @@ void psb_intel_lvds_init(struct drm_device *dev,
                 if (mode_dev->panel_fixed_mode) {
                         mode_dev->panel_fixed_mode->type |=
                             DRM_MODE_TYPE_PREFERRED;
+                        DRM_DEBUG_KMS("Using pre-programmed mode\n");
                         goto out;       /* FIXME: check for quirks */
                 }
         }
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 0ad1a508e2af..c995e540ff96 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1244,7 +1244,7 @@ static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset,
         mode = vgpu_vreg(vgpu, offset);
 
         if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) {
-                WARN_ONCE(1, "VM(%d): iGVT-g doesn't supporte GuC\n",
+                WARN_ONCE(1, "VM(%d): iGVT-g doesn't support GuC\n",
                                 vgpu->id);
                 return 0;
         }
diff --git a/drivers/gpu/drm/i915/gvt/render.c b/drivers/gpu/drm/i915/gvt/render.c
index c6e7972ac21d..a5e11d89df2f 100644
--- a/drivers/gpu/drm/i915/gvt/render.c
+++ b/drivers/gpu/drm/i915/gvt/render.c
@@ -340,6 +340,9 @@ void intel_gvt_restore_render_mmio(struct intel_vgpu *vgpu, int ring_id)
                 } else
                         v = mmio->value;
 
+                if (mmio->in_context)
+                        continue;
+
                 I915_WRITE(mmio->reg, v);
                 POSTING_READ(mmio->reg);
 
diff --git a/drivers/gpu/drm/i915/gvt/sched_policy.c b/drivers/gpu/drm/i915/gvt/sched_policy.c
index 79ba4b3440aa..f25ff133865f 100644
--- a/drivers/gpu/drm/i915/gvt/sched_policy.c
+++ b/drivers/gpu/drm/i915/gvt/sched_policy.c
@@ -129,9 +129,13 @@ static void try_to_schedule_next_vgpu(struct intel_gvt *gvt)
         struct vgpu_sched_data *vgpu_data;
         ktime_t cur_time;
 
-        /* no target to schedule */
-        if (!scheduler->next_vgpu)
+        /* no need to schedule if next_vgpu is the same with current_vgpu,
+         * let scheduler chose next_vgpu again by setting it to NULL.
+         */
+        if (scheduler->next_vgpu == scheduler->current_vgpu) {
+                scheduler->next_vgpu = NULL;
                 return;
+        }
 
         /*
          * after the flag is set, workload dispatch thread will
diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c
index 6718c84fb862..8d1df5678eaa 100644
--- a/drivers/gpu/drm/nouveau/nouveau_display.c
+++ b/drivers/gpu/drm/nouveau/nouveau_display.c
@@ -337,6 +337,8 @@ nouveau_display_hpd_work(struct work_struct *work)
         pm_runtime_get_sync(drm->dev->dev);
 
         drm_helper_hpd_irq_event(drm->dev);
+        /* enable polling for external displays */
+        drm_kms_helper_poll_enable(drm->dev);
 
         pm_runtime_mark_last_busy(drm->dev->dev);
         pm_runtime_put_sync(drm->dev->dev);
@@ -390,10 +392,6 @@ nouveau_display_init(struct drm_device *dev)
         if (ret)
                 return ret;
 
-        /* enable polling for external displays */
-        if (!dev->mode_config.poll_enabled)
-                drm_kms_helper_poll_enable(dev);
-
         /* enable hotplug interrupts */
         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
                 struct nouveau_connector *conn = nouveau_connector(connector);
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c
index c3dc75fee700..6844372366d3 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
@@ -502,6 +502,9 @@ nouveau_drm_load(struct drm_device *dev, unsigned long flags)
                 pm_runtime_allow(dev->dev);
                 pm_runtime_mark_last_busy(dev->dev);
                 pm_runtime_put(dev->dev);
+        } else {
+                /* enable polling for external displays */
+                drm_kms_helper_poll_enable(dev);
         }
         return 0;
 
@@ -774,9 +777,6 @@ nouveau_pmops_runtime_resume(struct device *dev)
 
         ret = nouveau_do_resume(drm_dev, true);
 
-        if (!drm_dev->mode_config.poll_enabled)
-                drm_kms_helper_poll_enable(drm_dev);
-
         /* do magic */
         nvif_mask(&device->object, 0x088488, (1 << 25), (1 << 25));
         vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
index 3a24788c3185..a7e55c422501 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
@@ -148,7 +148,7 @@ gk104_fifo_runlist_commit(struct gk104_fifo *fifo, int runl)
         case NVKM_MEM_TARGET_NCOH: target = 3; break;
         default:
                 WARN_ON(1);
-                return;
+                goto unlock;
         }
 
         nvkm_wr32(device, 0x002270, (nvkm_memory_addr(mem) >> 12) |
@@ -160,6 +160,7 @@ gk104_fifo_runlist_commit(struct gk104_fifo *fifo, int runl)
                                        & 0x00100000),
                                msecs_to_jiffies(2000)) == 0)
                 nvkm_error(subdev, "runlist %d update timeout\n", runl);
+unlock:
         mutex_unlock(&subdev->mutex);
 }
 
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_gr.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_gr.c
index d1cf02d22db1..1b0c793c0192 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_gr.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_gr.c
@@ -116,6 +116,7 @@ ls_ucode_img_load_gr(const struct nvkm_subdev *subdev, struct ls_ucode_img *img,
         ret = nvkm_firmware_get(subdev->device, f, &sig);
         if (ret)
                 goto free_data;
+
         img->sig = kmemdup(sig->data, sig->size, GFP_KERNEL);
         if (!img->sig) {
                 ret = -ENOMEM;
@@ -126,8 +127,9 @@ ls_ucode_img_load_gr(const struct nvkm_subdev *subdev, struct ls_ucode_img *img,
         img->ucode_data = ls_ucode_img_build(bl, code, data,
                                              &img->ucode_desc);
         if (IS_ERR(img->ucode_data)) {
+                kfree(img->sig);
                 ret = PTR_ERR(img->ucode_data);
-                goto free_data;
+                goto free_sig;
         }
         img->ucode_size = img->ucode_desc.image_size;
 
diff --git a/drivers/gpu/drm/qxl/qxl_display.c b/drivers/gpu/drm/qxl/qxl_display.c
index f5ef81595f5a..03fe182203ce 100644
--- a/drivers/gpu/drm/qxl/qxl_display.c
+++ b/drivers/gpu/drm/qxl/qxl_display.c
@@ -574,8 +574,6 @@ static void qxl_cursor_atomic_update(struct drm_plane *plane,
         if (ret)
                 return;
 
-        cmd = (struct qxl_cursor_cmd *) qxl_release_map(qdev, release);
-
         if (fb != old_state->fb) {
                 obj = to_qxl_framebuffer(fb)->obj;
                 user_bo = gem_to_qxl_bo(obj);
@@ -613,6 +611,7 @@ static void qxl_cursor_atomic_update(struct drm_plane *plane,
                 qxl_bo_kunmap(cursor_bo);
                 qxl_bo_kunmap(user_bo);
 
+                cmd = (struct qxl_cursor_cmd *) qxl_release_map(qdev, release);
                 cmd->u.set.visible = 1;
                 cmd->u.set.shape = qxl_bo_physical_address(qdev,
                                                            cursor_bo, 0);
@@ -623,6 +622,7 @@ static void qxl_cursor_atomic_update(struct drm_plane *plane,
                 if (ret)
                         goto out_free_release;
 
+                cmd = (struct qxl_cursor_cmd *) qxl_release_map(qdev, release);
                 cmd->type = QXL_CURSOR_MOVE;
         }
 
diff --git a/drivers/gpu/drm/radeon/ci_dpm.c b/drivers/gpu/drm/radeon/ci_dpm.c
index f0cf99783c62..c97fbb2ab48b 100644
--- a/drivers/gpu/drm/radeon/ci_dpm.c
+++ b/drivers/gpu/drm/radeon/ci_dpm.c
@@ -776,6 +776,12 @@ bool ci_dpm_vblank_too_short(struct radeon_device *rdev)
         u32 vblank_time = r600_dpm_get_vblank_time(rdev);
         u32 switch_limit = pi->mem_gddr5 ? 450 : 300;
 
+        /* disable mclk switching if the refresh is >120Hz, even if the
+        * blanking period would allow it
+        */
+        if (r600_dpm_get_vrefresh(rdev) > 120)
+                return true;
+
         if (vblank_time < switch_limit)
                 return true;
         else
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index e368ce22bcc4..258912132b62 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -7401,7 +7401,7 @@ static inline void cik_irq_ack(struct radeon_device *rdev)
                 WREG32(DC_HPD5_INT_CONTROL, tmp);
         }
         if (rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_INTERRUPT) {
-                tmp = RREG32(DC_HPD5_INT_CONTROL);
+                tmp = RREG32(DC_HPD6_INT_CONTROL);
                 tmp |= DC_HPDx_INT_ACK;
                 WREG32(DC_HPD6_INT_CONTROL, tmp);
         }
@@ -7431,7 +7431,7 @@ static inline void cik_irq_ack(struct radeon_device *rdev)
                 WREG32(DC_HPD5_INT_CONTROL, tmp);
         }
         if (rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_RX_INTERRUPT) {
-                tmp = RREG32(DC_HPD5_INT_CONTROL);
+                tmp = RREG32(DC_HPD6_INT_CONTROL);
                 tmp |= DC_HPDx_RX_INT_ACK;
                 WREG32(DC_HPD6_INT_CONTROL, tmp);
         }
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index f130ec41ee4b..0bf103536404 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -4927,7 +4927,7 @@ static void evergreen_irq_ack(struct radeon_device *rdev)
                 WREG32(DC_HPD5_INT_CONTROL, tmp);
         }
         if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
-                tmp = RREG32(DC_HPD5_INT_CONTROL);
+                tmp = RREG32(DC_HPD6_INT_CONTROL);
                 tmp |= DC_HPDx_INT_ACK;
                 WREG32(DC_HPD6_INT_CONTROL, tmp);
         }
@@ -4958,7 +4958,7 @@ static void evergreen_irq_ack(struct radeon_device *rdev)
                 WREG32(DC_HPD5_INT_CONTROL, tmp);
         }
         if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_RX_INTERRUPT) {
-                tmp = RREG32(DC_HPD5_INT_CONTROL);
+                tmp = RREG32(DC_HPD6_INT_CONTROL);
                 tmp |= DC_HPDx_RX_INT_ACK;
                 WREG32(DC_HPD6_INT_CONTROL, tmp);
         }
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 0a085176e79b..e06e2d8feab3 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -3988,7 +3988,7 @@ static void r600_irq_ack(struct radeon_device *rdev)
                         WREG32(DC_HPD5_INT_CONTROL, tmp);
                 }
                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
-                        tmp = RREG32(DC_HPD5_INT_CONTROL);
+                        tmp = RREG32(DC_HPD6_INT_CONTROL);
                         tmp |= DC_HPDx_INT_ACK;
                         WREG32(DC_HPD6_INT_CONTROL, tmp);
                 }
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
index 6a68d440bc44..d0ad03674250 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -116,7 +116,7 @@ int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
         if ((radeon_runtime_pm != 0) &&
             radeon_has_atpx() &&
             ((flags & RADEON_IS_IGP) == 0) &&
-            !pci_is_thunderbolt_attached(rdev->pdev))
+            !pci_is_thunderbolt_attached(dev->pdev))
                 flags |= RADEON_IS_PX;
 
         /* radeon_device_init should report only fatal error
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index ceee87f029d9..76d1888528e6 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -6317,7 +6317,7 @@ static inline void si_irq_ack(struct radeon_device *rdev)
                 WREG32(DC_HPD5_INT_CONTROL, tmp);
         }
         if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
-                tmp = RREG32(DC_HPD5_INT_CONTROL);
+                tmp = RREG32(DC_HPD6_INT_CONTROL);
                 tmp |= DC_HPDx_INT_ACK;
                 WREG32(DC_HPD6_INT_CONTROL, tmp);
         }
@@ -6348,7 +6348,7 @@ static inline void si_irq_ack(struct radeon_device *rdev)
                 WREG32(DC_HPD5_INT_CONTROL, tmp);
         }
         if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_RX_INTERRUPT) {
-                tmp = RREG32(DC_HPD5_INT_CONTROL);
+                tmp = RREG32(DC_HPD6_INT_CONTROL);
                 tmp |= DC_HPDx_RX_INT_ACK;
                 WREG32(DC_HPD6_INT_CONTROL, tmp);
         }