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-rw-r--r--drivers/gpu/drm/amd/display/dc/dc_helper.c59
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c153
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h19
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c114
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h20
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/reg_helper.h56
6 files changed, 401 insertions, 20 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c
index 48e1fcf53d43..bd0fda0ceb91 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c
@@ -117,6 +117,65 @@ uint32_t generic_reg_get5(const struct dc_context *ctx, uint32_t addr,
117 return reg_val; 117 return reg_val;
118} 118}
119 119
120uint32_t generic_reg_get6(const struct dc_context *ctx, uint32_t addr,
121 uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
122 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
123 uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
124 uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
125 uint8_t shift5, uint32_t mask5, uint32_t *field_value5,
126 uint8_t shift6, uint32_t mask6, uint32_t *field_value6)
127{
128 uint32_t reg_val = dm_read_reg(ctx, addr);
129 *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
130 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
131 *field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);
132 *field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4);
133 *field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5);
134 *field_value6 = get_reg_field_value_ex(reg_val, mask6, shift6);
135 return reg_val;
136}
137
138uint32_t generic_reg_get7(const struct dc_context *ctx, uint32_t addr,
139 uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
140 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
141 uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
142 uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
143 uint8_t shift5, uint32_t mask5, uint32_t *field_value5,
144 uint8_t shift6, uint32_t mask6, uint32_t *field_value6,
145 uint8_t shift7, uint32_t mask7, uint32_t *field_value7)
146{
147 uint32_t reg_val = dm_read_reg(ctx, addr);
148 *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
149 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
150 *field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);
151 *field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4);
152 *field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5);
153 *field_value6 = get_reg_field_value_ex(reg_val, mask6, shift6);
154 *field_value7 = get_reg_field_value_ex(reg_val, mask7, shift7);
155 return reg_val;
156}
157
158uint32_t generic_reg_get8(const struct dc_context *ctx, uint32_t addr,
159 uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
160 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
161 uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
162 uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
163 uint8_t shift5, uint32_t mask5, uint32_t *field_value5,
164 uint8_t shift6, uint32_t mask6, uint32_t *field_value6,
165 uint8_t shift7, uint32_t mask7, uint32_t *field_value7,
166 uint8_t shift8, uint32_t mask8, uint32_t *field_value8)
167{
168 uint32_t reg_val = dm_read_reg(ctx, addr);
169 *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
170 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
171 *field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);
172 *field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4);
173 *field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5);
174 *field_value6 = get_reg_field_value_ex(reg_val, mask6, shift6);
175 *field_value7 = get_reg_field_value_ex(reg_val, mask7, shift7);
176 *field_value8 = get_reg_field_value_ex(reg_val, mask8, shift8);
177 return reg_val;
178}
120/* note: va version of this is pretty bad idea, since there is a output parameter pass by pointer 179/* note: va version of this is pretty bad idea, since there is a output parameter pass by pointer
121 * compiler won't be able to check for size match and is prone to stack corruption type of bugs 180 * compiler won't be able to check for size match and is prone to stack corruption type of bugs
122 181
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
index 4ca9b6e9a824..58062172cf3f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
@@ -756,9 +756,159 @@ void min_set_viewport(
756 PRI_VIEWPORT_Y_START_C, viewport_c->y); 756 PRI_VIEWPORT_Y_START_C, viewport_c->y);
757} 757}
758 758
759void hubp1_read_state(struct dcn10_hubp *hubp1, 759void hubp1_read_state(struct hubp *hubp,
760 struct dcn_hubp_state *s) 760 struct dcn_hubp_state *s)
761{ 761{
762 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
763 struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr;
764 struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr;
765 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
766
767 /* Requester */
768 REG_GET(HUBPRET_CONTROL,
769 DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address);
770 REG_GET_4(DCN_EXPANSION_MODE,
771 DRQ_EXPANSION_MODE, &rq_regs->drq_expansion_mode,
772 PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode,
773 MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode,
774 CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode);
775 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG,
776 CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size,
777 MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size,
778 META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size,
779 MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size,
780 DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size,
781 MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size,
782 SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height,
783 PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear);
784 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C,
785 CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size,
786 MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size,
787 META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size,
788 MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size,
789 DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size,
790 MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size,
791 SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height,
792 PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear);
793
794 /* DLG - Per hubp */
795 REG_GET_2(BLANK_OFFSET_0,
796 REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end,
797 DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end);
798
799 REG_GET(BLANK_OFFSET_1,
800 MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start);
801
802 REG_GET(DST_DIMENSIONS,
803 REFCYC_PER_HTOTAL, &dlg_attr->refcyc_per_htotal);
804
805 REG_GET_2(DST_AFTER_SCALER,
806 REFCYC_X_AFTER_SCALER, &dlg_attr->refcyc_x_after_scaler,
807 DST_Y_AFTER_SCALER, &dlg_attr->dst_y_after_scaler);
808
809 if (REG(PREFETCH_SETTINS))
810 REG_GET_2(PREFETCH_SETTINS,
811 DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch,
812 VRATIO_PREFETCH, &dlg_attr->vratio_prefetch);
813 else
814 REG_GET_2(PREFETCH_SETTINGS,
815 DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch,
816 VRATIO_PREFETCH, &dlg_attr->vratio_prefetch);
817
818 REG_GET_2(VBLANK_PARAMETERS_0,
819 DST_Y_PER_VM_VBLANK, &dlg_attr->dst_y_per_vm_vblank,
820 DST_Y_PER_ROW_VBLANK, &dlg_attr->dst_y_per_row_vblank);
821
822 REG_GET(REF_FREQ_TO_PIX_FREQ,
823 REF_FREQ_TO_PIX_FREQ, &dlg_attr->ref_freq_to_pix_freq);
824
825 /* DLG - Per luma/chroma */
826 REG_GET(VBLANK_PARAMETERS_1,
827 REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr->refcyc_per_pte_group_vblank_l);
828
829 REG_GET(VBLANK_PARAMETERS_3,
830 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l);
831
832 if (REG(NOM_PARAMETERS_0))
833 REG_GET(NOM_PARAMETERS_0,
834 DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr->dst_y_per_pte_row_nom_l);
835
836 if (REG(NOM_PARAMETERS_1))
837 REG_GET(NOM_PARAMETERS_1,
838 REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr->refcyc_per_pte_group_nom_l);
839
840 REG_GET(NOM_PARAMETERS_4,
841 DST_Y_PER_META_ROW_NOM_L, &dlg_attr->dst_y_per_meta_row_nom_l);
842
843 REG_GET(NOM_PARAMETERS_5,
844 REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr->refcyc_per_meta_chunk_nom_l);
845
846 REG_GET_2(PER_LINE_DELIVERY_PRE,
847 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l,
848 REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr->refcyc_per_line_delivery_pre_c);
849
850 REG_GET_2(PER_LINE_DELIVERY,
851 REFCYC_PER_LINE_DELIVERY_L, &dlg_attr->refcyc_per_line_delivery_l,
852 REFCYC_PER_LINE_DELIVERY_C, &dlg_attr->refcyc_per_line_delivery_c);
853
854 if (REG(PREFETCH_SETTINS_C))
855 REG_GET(PREFETCH_SETTINS_C,
856 VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c);
857 else
858 REG_GET(PREFETCH_SETTINGS_C,
859 VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c);
860
861 REG_GET(VBLANK_PARAMETERS_2,
862 REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr->refcyc_per_pte_group_vblank_c);
863
864 REG_GET(VBLANK_PARAMETERS_4,
865 REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr->refcyc_per_meta_chunk_vblank_c);
866
867 if (REG(NOM_PARAMETERS_2))
868 REG_GET(NOM_PARAMETERS_2,
869 DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr->dst_y_per_pte_row_nom_c);
870
871 if (REG(NOM_PARAMETERS_3))
872 REG_GET(NOM_PARAMETERS_3,
873 REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr->refcyc_per_pte_group_nom_c);
874
875 REG_GET(NOM_PARAMETERS_6,
876 DST_Y_PER_META_ROW_NOM_C, &dlg_attr->dst_y_per_meta_row_nom_c);
877
878 REG_GET(NOM_PARAMETERS_7,
879 REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr->refcyc_per_meta_chunk_nom_c);
880
881 /* TTU - per hubp */
882 REG_GET_2(DCN_TTU_QOS_WM,
883 QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm,
884 QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm);
885
886 REG_GET_2(DCN_GLOBAL_TTU_CNTL,
887 MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank,
888 QoS_LEVEL_FLIP, &ttu_attr->qos_level_flip);
889
890 /* TTU - per luma/chroma */
891 /* Assumed surf0 is luma and 1 is chroma */
892
893 REG_GET_3(DCN_SURF0_TTU_CNTL0,
894 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_l,
895 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_l,
896 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_l);
897
898 REG_GET(DCN_SURF0_TTU_CNTL1,
899 REFCYC_PER_REQ_DELIVERY_PRE,
900 &ttu_attr->refcyc_per_req_delivery_pre_l);
901
902 REG_GET_3(DCN_SURF1_TTU_CNTL0,
903 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_c,
904 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_c,
905 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_c);
906
907 REG_GET(DCN_SURF1_TTU_CNTL1,
908 REFCYC_PER_REQ_DELIVERY_PRE,
909 &ttu_attr->refcyc_per_req_delivery_pre_c);
910
911 /* Rest of hubp */
762 REG_GET(DCSURF_SURFACE_CONFIG, 912 REG_GET(DCSURF_SURFACE_CONFIG,
763 SURFACE_PIXEL_FORMAT, &s->pixel_format); 913 SURFACE_PIXEL_FORMAT, &s->pixel_format);
764 914
@@ -956,6 +1106,7 @@ static struct hubp_funcs dcn10_hubp_funcs = {
956 .hubp_disconnect = hubp1_disconnect, 1106 .hubp_disconnect = hubp1_disconnect,
957 .hubp_clk_cntl = hubp1_clk_cntl, 1107 .hubp_clk_cntl = hubp1_clk_cntl,
958 .hubp_vtg_sel = hubp1_vtg_sel, 1108 .hubp_vtg_sel = hubp1_vtg_sel,
1109 .hubp_read_state = hubp1_read_state,
959}; 1110};
960 1111
961/*****************************************/ 1112/*****************************************/
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
index e0d6d32357c0..920ae3a1b412 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
@@ -690,24 +690,7 @@ void dcn10_hubp_construct(
690 const struct dcn_mi_shift *hubp_shift, 690 const struct dcn_mi_shift *hubp_shift,
691 const struct dcn_mi_mask *hubp_mask); 691 const struct dcn_mi_mask *hubp_mask);
692 692
693 693void hubp1_read_state(struct hubp *hubp,
694struct dcn_hubp_state {
695 uint32_t pixel_format;
696 uint32_t inuse_addr_hi;
697 uint32_t viewport_width;
698 uint32_t viewport_height;
699 uint32_t rotation_angle;
700 uint32_t h_mirror_en;
701 uint32_t sw_mode;
702 uint32_t dcc_en;
703 uint32_t blank_en;
704 uint32_t underflow_status;
705 uint32_t ttu_disable;
706 uint32_t min_ttu_vblank;
707 uint32_t qos_level_low_wm;
708 uint32_t qos_level_high_wm;
709};
710void hubp1_read_state(struct dcn10_hubp *hubp1,
711 struct dcn_hubp_state *s); 694 struct dcn_hubp_state *s);
712 695
713enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch); 696enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index a6cf9ade9131..7dd130d15a67 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -112,6 +112,104 @@ void dcn10_log_hubbub_state(struct dc *dc)
112 DTN_INFO("\n"); 112 DTN_INFO("\n");
113} 113}
114 114
115static void print_rq_dlg_ttu_regs(struct dc_context *dc_ctx, struct dcn_hubp_state *s)
116{
117 struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &s->dlg_attr;
118 struct _vcs_dpi_display_ttu_regs_st *ttu_regs = &s->ttu_attr;
119 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
120
121 DTN_INFO("========Requester========\n");
122 DTN_INFO("drq_expansion_mode = 0x%0x\n", rq_regs->drq_expansion_mode);
123 DTN_INFO("prq_expansion_mode = 0x%0x\n", rq_regs->prq_expansion_mode);
124 DTN_INFO("mrq_expansion_mode = 0x%0x\n", rq_regs->mrq_expansion_mode);
125 DTN_INFO("crq_expansion_mode = 0x%0x\n", rq_regs->crq_expansion_mode);
126 DTN_INFO("plane1_base_address = 0x%0x\n", rq_regs->plane1_base_address);
127 DTN_INFO("==<LUMA>==\n");
128 DTN_INFO("chunk_size = 0x%0x\n", rq_regs->rq_regs_l.chunk_size);
129 DTN_INFO("min_chunk_size = 0x%0x\n", rq_regs->rq_regs_l.min_chunk_size);
130 DTN_INFO("meta_chunk_size = 0x%0x\n", rq_regs->rq_regs_l.meta_chunk_size);
131 DTN_INFO("min_meta_chunk_size = 0x%0x\n", rq_regs->rq_regs_l.min_meta_chunk_size);
132 DTN_INFO("dpte_group_size = 0x%0x\n", rq_regs->rq_regs_l.dpte_group_size);
133 DTN_INFO("mpte_group_size = 0x%0x\n", rq_regs->rq_regs_l.mpte_group_size);
134 DTN_INFO("swath_height = 0x%0x\n", rq_regs->rq_regs_l.swath_height);
135 DTN_INFO("pte_row_height_linear = 0x%0x\n", rq_regs->rq_regs_l.pte_row_height_linear);
136 DTN_INFO("==<CHROMA>==\n");
137 DTN_INFO("chunk_size = 0x%0x\n", rq_regs->rq_regs_c.chunk_size);
138 DTN_INFO("min_chunk_size = 0x%0x\n", rq_regs->rq_regs_c.min_chunk_size);
139 DTN_INFO("meta_chunk_size = 0x%0x\n", rq_regs->rq_regs_c.meta_chunk_size);
140 DTN_INFO("min_meta_chunk_size = 0x%0x\n", rq_regs->rq_regs_c.min_meta_chunk_size);
141 DTN_INFO("dpte_group_size = 0x%0x\n", rq_regs->rq_regs_c.dpte_group_size);
142 DTN_INFO("mpte_group_size = 0x%0x\n", rq_regs->rq_regs_c.mpte_group_size);
143 DTN_INFO("swath_height = 0x%0x\n", rq_regs->rq_regs_c.swath_height);
144 DTN_INFO("pte_row_height_linear = 0x%0x\n", rq_regs->rq_regs_c.pte_row_height_linear);
145
146 DTN_INFO("========DLG========\n");
147 DTN_INFO("refcyc_h_blank_end = 0x%0x\n", dlg_regs->refcyc_h_blank_end);
148 DTN_INFO("dlg_vblank_end = 0x%0x\n", dlg_regs->dlg_vblank_end);
149 DTN_INFO("min_dst_y_next_start = 0x%0x\n", dlg_regs->min_dst_y_next_start);
150 DTN_INFO("refcyc_per_htotal = 0x%0x\n", dlg_regs->refcyc_per_htotal);
151 DTN_INFO("refcyc_x_after_scaler = 0x%0x\n", dlg_regs->refcyc_x_after_scaler);
152 DTN_INFO("dst_y_after_scaler = 0x%0x\n", dlg_regs->dst_y_after_scaler);
153 DTN_INFO("dst_y_prefetch = 0x%0x\n", dlg_regs->dst_y_prefetch);
154 DTN_INFO("dst_y_per_vm_vblank = 0x%0x\n", dlg_regs->dst_y_per_vm_vblank);
155 DTN_INFO("dst_y_per_row_vblank = 0x%0x\n", dlg_regs->dst_y_per_row_vblank);
156 DTN_INFO("dst_y_per_vm_flip = 0x%0x\n", dlg_regs->dst_y_per_vm_flip);
157 DTN_INFO("dst_y_per_row_flip = 0x%0x\n", dlg_regs->dst_y_per_row_flip);
158 DTN_INFO("ref_freq_to_pix_freq = 0x%0x\n", dlg_regs->ref_freq_to_pix_freq);
159 DTN_INFO("vratio_prefetch = 0x%0x\n", dlg_regs->vratio_prefetch);
160 DTN_INFO("vratio_prefetch_c = 0x%0x\n", dlg_regs->vratio_prefetch_c);
161 DTN_INFO("refcyc_per_pte_group_vblank_l = 0x%0x\n", dlg_regs->refcyc_per_pte_group_vblank_l);
162 DTN_INFO("refcyc_per_pte_group_vblank_c = 0x%0x\n", dlg_regs->refcyc_per_pte_group_vblank_c);
163 DTN_INFO("refcyc_per_meta_chunk_vblank_l = 0x%0x\n", dlg_regs->refcyc_per_meta_chunk_vblank_l);
164 DTN_INFO("refcyc_per_meta_chunk_vblank_c = 0x%0x\n", dlg_regs->refcyc_per_meta_chunk_vblank_c);
165 DTN_INFO("refcyc_per_pte_group_flip_l = 0x%0x\n", dlg_regs->refcyc_per_pte_group_flip_l);
166 DTN_INFO("refcyc_per_pte_group_flip_c = 0x%0x\n", dlg_regs->refcyc_per_pte_group_flip_c);
167 DTN_INFO("refcyc_per_meta_chunk_flip_l = 0x%0x\n", dlg_regs->refcyc_per_meta_chunk_flip_l);
168 DTN_INFO("refcyc_per_meta_chunk_flip_c = 0x%0x\n", dlg_regs->refcyc_per_meta_chunk_flip_c);
169 DTN_INFO("dst_y_per_pte_row_nom_l = 0x%0x\n", dlg_regs->dst_y_per_pte_row_nom_l);
170 DTN_INFO("dst_y_per_pte_row_nom_c = 0x%0x\n", dlg_regs->dst_y_per_pte_row_nom_c);
171 DTN_INFO("refcyc_per_pte_group_nom_l = 0x%0x\n", dlg_regs->refcyc_per_pte_group_nom_l);
172 DTN_INFO("refcyc_per_pte_group_nom_c = 0x%0x\n", dlg_regs->refcyc_per_pte_group_nom_c);
173 DTN_INFO("dst_y_per_meta_row_nom_l = 0x%0x\n", dlg_regs->dst_y_per_meta_row_nom_l);
174 DTN_INFO("dst_y_per_meta_row_nom_c = 0x%0x\n", dlg_regs->dst_y_per_meta_row_nom_c);
175 DTN_INFO("refcyc_per_meta_chunk_nom_l = 0x%0x\n", dlg_regs->refcyc_per_meta_chunk_nom_l);
176 DTN_INFO("refcyc_per_meta_chunk_nom_c = 0x%0x\n", dlg_regs->refcyc_per_meta_chunk_nom_c);
177 DTN_INFO("refcyc_per_line_delivery_pre_l = 0x%0x\n", dlg_regs->refcyc_per_line_delivery_pre_l);
178 DTN_INFO("refcyc_per_line_delivery_pre_c = 0x%0x\n", dlg_regs->refcyc_per_line_delivery_pre_c);
179 DTN_INFO("refcyc_per_line_delivery_l = 0x%0x\n", dlg_regs->refcyc_per_line_delivery_l);
180 DTN_INFO("refcyc_per_line_delivery_c = 0x%0x\n", dlg_regs->refcyc_per_line_delivery_c);
181 DTN_INFO("chunk_hdl_adjust_cur0 = 0x%0x\n", dlg_regs->chunk_hdl_adjust_cur0);
182 DTN_INFO("dst_y_offset_cur1 = 0x%0x\n", dlg_regs->dst_y_offset_cur1);
183 DTN_INFO("chunk_hdl_adjust_cur1 = 0x%0x\n", dlg_regs->chunk_hdl_adjust_cur1);
184 DTN_INFO("vready_after_vcount0 = 0x%0x\n", dlg_regs->vready_after_vcount0);
185 DTN_INFO("dst_y_delta_drq_limit = 0x%0x\n", dlg_regs->dst_y_delta_drq_limit);
186 DTN_INFO("xfc_reg_transfer_delay = 0x%0x\n", dlg_regs->xfc_reg_transfer_delay);
187 DTN_INFO("xfc_reg_precharge_delay = 0x%0x\n", dlg_regs->xfc_reg_precharge_delay);
188 DTN_INFO("xfc_reg_remote_surface_flip_latency = 0x%0x\n", dlg_regs->xfc_reg_remote_surface_flip_latency);
189
190 DTN_INFO("========TTU========\n");
191 DTN_INFO("qos_level_low_wm = 0x%0x\n", ttu_regs->qos_level_low_wm);
192 DTN_INFO("qos_level_high_wm = 0x%0x\n", ttu_regs->qos_level_high_wm);
193 DTN_INFO("min_ttu_vblank = 0x%0x\n", ttu_regs->min_ttu_vblank);
194 DTN_INFO("qos_level_flip = 0x%0x\n", ttu_regs->qos_level_flip);
195 DTN_INFO("refcyc_per_req_delivery_pre_l = 0x%0x\n", ttu_regs->refcyc_per_req_delivery_pre_l);
196 DTN_INFO("refcyc_per_req_delivery_l = 0x%0x\n", ttu_regs->refcyc_per_req_delivery_l);
197 DTN_INFO("refcyc_per_req_delivery_pre_c = 0x%0x\n", ttu_regs->refcyc_per_req_delivery_pre_c);
198 DTN_INFO("refcyc_per_req_delivery_c = 0x%0x\n", ttu_regs->refcyc_per_req_delivery_c);
199 DTN_INFO("refcyc_per_req_delivery_cur0 = 0x%0x\n", ttu_regs->refcyc_per_req_delivery_cur0);
200 DTN_INFO("refcyc_per_req_delivery_pre_cur0 = 0x%0x\n", ttu_regs->refcyc_per_req_delivery_pre_cur0);
201 DTN_INFO("refcyc_per_req_delivery_cur1 = 0x%0x\n", ttu_regs->refcyc_per_req_delivery_cur1);
202 DTN_INFO("refcyc_per_req_delivery_pre_cur1 = 0x%0x\n", ttu_regs->refcyc_per_req_delivery_pre_cur1);
203 DTN_INFO("qos_level_fixed_l = 0x%0x\n", ttu_regs->qos_level_fixed_l);
204 DTN_INFO("qos_ramp_disable_l = 0x%0x\n", ttu_regs->qos_ramp_disable_l);
205 DTN_INFO("qos_level_fixed_c = 0x%0x\n", ttu_regs->qos_level_fixed_c);
206 DTN_INFO("qos_ramp_disable_c = 0x%0x\n", ttu_regs->qos_ramp_disable_c);
207 DTN_INFO("qos_level_fixed_cur0 = 0x%0x\n", ttu_regs->qos_level_fixed_cur0);
208 DTN_INFO("qos_ramp_disable_cur0 = 0x%0x\n", ttu_regs->qos_ramp_disable_cur0);
209 DTN_INFO("qos_level_fixed_cur1 = 0x%0x\n", ttu_regs->qos_level_fixed_cur1);
210 DTN_INFO("qos_ramp_disable_cur1 = 0x%0x\n", ttu_regs->qos_ramp_disable_cur1);
211}
212
115void dcn10_log_hw_state(struct dc *dc) 213void dcn10_log_hw_state(struct dc *dc)
116{ 214{
117 struct dc_context *dc_ctx = dc->ctx; 215 struct dc_context *dc_ctx = dc->ctx;
@@ -129,7 +227,7 @@ void dcn10_log_hw_state(struct dc *dc)
129 struct hubp *hubp = pool->hubps[i]; 227 struct hubp *hubp = pool->hubps[i];
130 struct dcn_hubp_state s; 228 struct dcn_hubp_state s;
131 229
132 hubp1_read_state(TO_DCN10_HUBP(hubp), &s); 230 hubp->funcs->hubp_read_state(hubp, &s);
133 231
134 DTN_INFO("[%2d]: %5xh %6xh %5d %6d %2xh %2xh %6xh" 232 DTN_INFO("[%2d]: %5xh %6xh %5d %6d %2xh %2xh %6xh"
135 " %6d %8d %7d %8xh", 233 " %6d %8d %7d %8xh",
@@ -201,6 +299,20 @@ void dcn10_log_hw_state(struct dc *dc)
201 } 299 }
202 DTN_INFO("\n"); 300 DTN_INFO("\n");
203 301
302 for (i = 0; i < pool->pipe_count; i++) {
303 struct hubp *hubp = pool->hubps[i];
304 struct dcn_hubp_state s = {0};
305
306 if (!dc->current_state->res_ctx.pipe_ctx[i].stream)
307 continue;
308
309 hubp->funcs->hubp_read_state(hubp, &s);
310 DTN_INFO("RQ-DLG-TTU registers for HUBP%d:\n", i);
311 print_rq_dlg_ttu_regs(dc_ctx, &s);
312 DTN_INFO("\n");
313 }
314 DTN_INFO("\n");
315
204 log_mpc_crc(dc); 316 log_mpc_crc(dc);
205 317
206 DTN_INFO_END(); 318 DTN_INFO_END();
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
index 9ced254e652c..3866147fb02a 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
@@ -56,6 +56,25 @@ struct hubp {
56 bool power_gated; 56 bool power_gated;
57}; 57};
58 58
59struct dcn_hubp_state {
60 struct _vcs_dpi_display_dlg_regs_st dlg_attr;
61 struct _vcs_dpi_display_ttu_regs_st ttu_attr;
62 struct _vcs_dpi_display_rq_regs_st rq_regs;
63 uint32_t pixel_format;
64 uint32_t inuse_addr_hi;
65 uint32_t viewport_width;
66 uint32_t viewport_height;
67 uint32_t rotation_angle;
68 uint32_t h_mirror_en;
69 uint32_t sw_mode;
70 uint32_t dcc_en;
71 uint32_t blank_en;
72 uint32_t underflow_status;
73 uint32_t ttu_disable;
74 uint32_t min_ttu_vblank;
75 uint32_t qos_level_low_wm;
76 uint32_t qos_level_high_wm;
77};
59 78
60struct hubp_funcs { 79struct hubp_funcs {
61 void (*hubp_setup)( 80 void (*hubp_setup)(
@@ -121,6 +140,7 @@ struct hubp_funcs {
121 140
122 void (*hubp_clk_cntl)(struct hubp *hubp, bool enable); 141 void (*hubp_clk_cntl)(struct hubp *hubp, bool enable);
123 void (*hubp_vtg_sel)(struct hubp *hubp, uint32_t otg_inst); 142 void (*hubp_vtg_sel)(struct hubp *hubp, uint32_t otg_inst);
143 void (*hubp_read_state)(struct hubp *hubp, struct dcn_hubp_state *s);
124 144
125}; 145};
126 146
diff --git a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
index 77eb72874e90..3306e7b0b3e3 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
@@ -183,6 +183,36 @@
183 FN(reg_name, f4), v4, \ 183 FN(reg_name, f4), v4, \
184 FN(reg_name, f5), v5) 184 FN(reg_name, f5), v5)
185 185
186#define REG_GET_6(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
187 generic_reg_get6(CTX, REG(reg_name), \
188 FN(reg_name, f1), v1, \
189 FN(reg_name, f2), v2, \
190 FN(reg_name, f3), v3, \
191 FN(reg_name, f4), v4, \
192 FN(reg_name, f5), v5, \
193 FN(reg_name, f6), v6)
194
195#define REG_GET_7(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
196 generic_reg_get7(CTX, REG(reg_name), \
197 FN(reg_name, f1), v1, \
198 FN(reg_name, f2), v2, \
199 FN(reg_name, f3), v3, \
200 FN(reg_name, f4), v4, \
201 FN(reg_name, f5), v5, \
202 FN(reg_name, f6), v6, \
203 FN(reg_name, f7), v7)
204
205#define REG_GET_8(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
206 generic_reg_get8(CTX, REG(reg_name), \
207 FN(reg_name, f1), v1, \
208 FN(reg_name, f2), v2, \
209 FN(reg_name, f3), v3, \
210 FN(reg_name, f4), v4, \
211 FN(reg_name, f5), v5, \
212 FN(reg_name, f6), v6, \
213 FN(reg_name, f7), v7, \
214 FN(reg_name, f8), v8)
215
186/* macro to poll and wait for a register field to read back given value */ 216/* macro to poll and wait for a register field to read back given value */
187 217
188#define REG_WAIT(reg_name, field, val, delay_between_poll_us, max_try) \ 218#define REG_WAIT(reg_name, field, val, delay_between_poll_us, max_try) \
@@ -389,4 +419,30 @@ uint32_t generic_reg_get5(const struct dc_context *ctx, uint32_t addr,
389 uint8_t shift4, uint32_t mask4, uint32_t *field_value4, 419 uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
390 uint8_t shift5, uint32_t mask5, uint32_t *field_value5); 420 uint8_t shift5, uint32_t mask5, uint32_t *field_value5);
391 421
422uint32_t generic_reg_get6(const struct dc_context *ctx, uint32_t addr,
423 uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
424 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
425 uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
426 uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
427 uint8_t shift5, uint32_t mask5, uint32_t *field_value5,
428 uint8_t shift6, uint32_t mask6, uint32_t *field_value6);
429
430uint32_t generic_reg_get7(const struct dc_context *ctx, uint32_t addr,
431 uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
432 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
433 uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
434 uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
435 uint8_t shift5, uint32_t mask5, uint32_t *field_value5,
436 uint8_t shift6, uint32_t mask6, uint32_t *field_value6,
437 uint8_t shift7, uint32_t mask7, uint32_t *field_value7);
438
439uint32_t generic_reg_get8(const struct dc_context *ctx, uint32_t addr,
440 uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
441 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
442 uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
443 uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
444 uint8_t shift5, uint32_t mask5, uint32_t *field_value5,
445 uint8_t shift6, uint32_t mask6, uint32_t *field_value6,
446 uint8_t shift7, uint32_t mask7, uint32_t *field_value7,
447 uint8_t shift8, uint32_t mask8, uint32_t *field_value8);
392#endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_REG_HELPER_H_ */ 448#endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_REG_HELPER_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-30 22:35:49 -0400