diff options
Diffstat (limited to 'drivers/gpu/drm')
| -rw-r--r-- | drivers/gpu/drm/exynos/exynos_drm_fimc.c | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/exynos/exynos_drm_gsc.c | 6 | ||||
| -rw-r--r-- | drivers/gpu/drm/exynos/exynos_hdmi.c | 7 | ||||
| -rw-r--r-- | drivers/gpu/drm/exynos/exynos_mixer.c | 21 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c | 29 | ||||
| -rw-r--r-- | drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c | 4 |
6 files changed, 32 insertions, 36 deletions
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimc.c b/drivers/gpu/drm/exynos/exynos_drm_fimc.c index 842d6b8dc3c4..2a652359af64 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimc.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimc.c | |||
| @@ -1745,7 +1745,6 @@ static int fimc_probe(struct platform_device *pdev) | |||
| 1745 | spin_lock_init(&ctx->lock); | 1745 | spin_lock_init(&ctx->lock); |
| 1746 | platform_set_drvdata(pdev, ctx); | 1746 | platform_set_drvdata(pdev, ctx); |
| 1747 | 1747 | ||
| 1748 | pm_runtime_set_active(dev); | ||
| 1749 | pm_runtime_enable(dev); | 1748 | pm_runtime_enable(dev); |
| 1750 | 1749 | ||
| 1751 | ret = exynos_drm_ippdrv_register(ippdrv); | 1750 | ret = exynos_drm_ippdrv_register(ippdrv); |
diff --git a/drivers/gpu/drm/exynos/exynos_drm_gsc.c b/drivers/gpu/drm/exynos/exynos_drm_gsc.c index 8040ed2a831f..f1c6b76c127f 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_gsc.c +++ b/drivers/gpu/drm/exynos/exynos_drm_gsc.c | |||
| @@ -593,8 +593,7 @@ static int gsc_src_set_transf(struct device *dev, | |||
| 593 | 593 | ||
| 594 | gsc_write(cfg, GSC_IN_CON); | 594 | gsc_write(cfg, GSC_IN_CON); |
| 595 | 595 | ||
| 596 | ctx->rotation = cfg & | 596 | ctx->rotation = (cfg & GSC_IN_ROT_90) ? 1 : 0; |
| 597 | (GSC_IN_ROT_90 | GSC_IN_ROT_270) ? 1 : 0; | ||
| 598 | *swap = ctx->rotation; | 597 | *swap = ctx->rotation; |
| 599 | 598 | ||
| 600 | return 0; | 599 | return 0; |
| @@ -857,8 +856,7 @@ static int gsc_dst_set_transf(struct device *dev, | |||
| 857 | 856 | ||
| 858 | gsc_write(cfg, GSC_IN_CON); | 857 | gsc_write(cfg, GSC_IN_CON); |
| 859 | 858 | ||
| 860 | ctx->rotation = cfg & | 859 | ctx->rotation = (cfg & GSC_IN_ROT_90) ? 1 : 0; |
| 861 | (GSC_IN_ROT_90 | GSC_IN_ROT_270) ? 1 : 0; | ||
| 862 | *swap = ctx->rotation; | 860 | *swap = ctx->rotation; |
| 863 | 861 | ||
| 864 | return 0; | 862 | return 0; |
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c index 99e286489031..4a00990e4ae4 100644 --- a/drivers/gpu/drm/exynos/exynos_hdmi.c +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c | |||
| @@ -1064,6 +1064,7 @@ static int hdmi_get_modes(struct drm_connector *connector) | |||
| 1064 | { | 1064 | { |
| 1065 | struct hdmi_context *hdata = ctx_from_connector(connector); | 1065 | struct hdmi_context *hdata = ctx_from_connector(connector); |
| 1066 | struct edid *edid; | 1066 | struct edid *edid; |
| 1067 | int ret; | ||
| 1067 | 1068 | ||
| 1068 | if (!hdata->ddc_adpt) | 1069 | if (!hdata->ddc_adpt) |
| 1069 | return -ENODEV; | 1070 | return -ENODEV; |
| @@ -1079,7 +1080,11 @@ static int hdmi_get_modes(struct drm_connector *connector) | |||
| 1079 | 1080 | ||
| 1080 | drm_mode_connector_update_edid_property(connector, edid); | 1081 | drm_mode_connector_update_edid_property(connector, edid); |
| 1081 | 1082 | ||
| 1082 | return drm_add_edid_modes(connector, edid); | 1083 | ret = drm_add_edid_modes(connector, edid); |
| 1084 | |||
| 1085 | kfree(edid); | ||
| 1086 | |||
| 1087 | return ret; | ||
| 1083 | } | 1088 | } |
| 1084 | 1089 | ||
| 1085 | static int hdmi_find_phy_conf(struct hdmi_context *hdata, u32 pixel_clock) | 1090 | static int hdmi_find_phy_conf(struct hdmi_context *hdata, u32 pixel_clock) |
diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c index cae98db33062..4706b56902b4 100644 --- a/drivers/gpu/drm/exynos/exynos_mixer.c +++ b/drivers/gpu/drm/exynos/exynos_mixer.c | |||
| @@ -718,6 +718,10 @@ static irqreturn_t mixer_irq_handler(int irq, void *arg) | |||
| 718 | 718 | ||
| 719 | /* handling VSYNC */ | 719 | /* handling VSYNC */ |
| 720 | if (val & MXR_INT_STATUS_VSYNC) { | 720 | if (val & MXR_INT_STATUS_VSYNC) { |
| 721 | /* vsync interrupt use different bit for read and clear */ | ||
| 722 | val |= MXR_INT_CLEAR_VSYNC; | ||
| 723 | val &= ~MXR_INT_STATUS_VSYNC; | ||
| 724 | |||
| 721 | /* interlace scan need to check shadow register */ | 725 | /* interlace scan need to check shadow register */ |
| 722 | if (ctx->interlace) { | 726 | if (ctx->interlace) { |
| 723 | base = mixer_reg_read(res, MXR_GRAPHIC_BASE(0)); | 727 | base = mixer_reg_read(res, MXR_GRAPHIC_BASE(0)); |
| @@ -743,11 +747,6 @@ static irqreturn_t mixer_irq_handler(int irq, void *arg) | |||
| 743 | 747 | ||
| 744 | out: | 748 | out: |
| 745 | /* clear interrupts */ | 749 | /* clear interrupts */ |
| 746 | if (~val & MXR_INT_EN_VSYNC) { | ||
| 747 | /* vsync interrupt use different bit for read and clear */ | ||
| 748 | val &= ~MXR_INT_EN_VSYNC; | ||
| 749 | val |= MXR_INT_CLEAR_VSYNC; | ||
| 750 | } | ||
| 751 | mixer_reg_write(res, MXR_INT_STATUS, val); | 750 | mixer_reg_write(res, MXR_INT_STATUS, val); |
| 752 | 751 | ||
| 753 | spin_unlock(&res->reg_slock); | 752 | spin_unlock(&res->reg_slock); |
| @@ -907,8 +906,8 @@ static int mixer_enable_vblank(struct exynos_drm_crtc *crtc) | |||
| 907 | } | 906 | } |
| 908 | 907 | ||
| 909 | /* enable vsync interrupt */ | 908 | /* enable vsync interrupt */ |
| 910 | mixer_reg_writemask(res, MXR_INT_EN, MXR_INT_EN_VSYNC, | 909 | mixer_reg_writemask(res, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC); |
| 911 | MXR_INT_EN_VSYNC); | 910 | mixer_reg_writemask(res, MXR_INT_EN, ~0, MXR_INT_EN_VSYNC); |
| 912 | 911 | ||
| 913 | return 0; | 912 | return 0; |
| 914 | } | 913 | } |
| @@ -918,7 +917,13 @@ static void mixer_disable_vblank(struct exynos_drm_crtc *crtc) | |||
| 918 | struct mixer_context *mixer_ctx = crtc->ctx; | 917 | struct mixer_context *mixer_ctx = crtc->ctx; |
| 919 | struct mixer_resources *res = &mixer_ctx->mixer_res; | 918 | struct mixer_resources *res = &mixer_ctx->mixer_res; |
| 920 | 919 | ||
| 920 | if (!mixer_ctx->powered) { | ||
| 921 | mixer_ctx->int_en &= MXR_INT_EN_VSYNC; | ||
| 922 | return; | ||
| 923 | } | ||
| 924 | |||
| 921 | /* disable vsync interrupt */ | 925 | /* disable vsync interrupt */ |
| 926 | mixer_reg_writemask(res, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC); | ||
| 922 | mixer_reg_writemask(res, MXR_INT_EN, 0, MXR_INT_EN_VSYNC); | 927 | mixer_reg_writemask(res, MXR_INT_EN, 0, MXR_INT_EN_VSYNC); |
| 923 | } | 928 | } |
| 924 | 929 | ||
| @@ -1047,6 +1052,8 @@ static void mixer_enable(struct exynos_drm_crtc *crtc) | |||
| 1047 | 1052 | ||
| 1048 | mixer_reg_writemask(res, MXR_STATUS, ~0, MXR_STATUS_SOFT_RESET); | 1053 | mixer_reg_writemask(res, MXR_STATUS, ~0, MXR_STATUS_SOFT_RESET); |
| 1049 | 1054 | ||
| 1055 | if (ctx->int_en & MXR_INT_EN_VSYNC) | ||
| 1056 | mixer_reg_writemask(res, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC); | ||
| 1050 | mixer_reg_write(res, MXR_INT_EN, ctx->int_en); | 1057 | mixer_reg_write(res, MXR_INT_EN, ctx->int_en); |
| 1051 | mixer_win_reset(ctx); | 1058 | mixer_win_reset(ctx); |
| 1052 | } | 1059 | } |
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c index 52c22b026005..e10f9644140f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c | |||
| @@ -166,30 +166,14 @@ gk104_fifo_context_attach(struct nvkm_object *parent, | |||
| 166 | } | 166 | } |
| 167 | 167 | ||
| 168 | static int | 168 | static int |
| 169 | gk104_fifo_chan_kick(struct gk104_fifo_chan *chan) | ||
| 170 | { | ||
| 171 | struct nvkm_object *obj = (void *)chan; | ||
| 172 | struct gk104_fifo_priv *priv = (void *)obj->engine; | ||
| 173 | |||
| 174 | nv_wr32(priv, 0x002634, chan->base.chid); | ||
| 175 | if (!nv_wait(priv, 0x002634, 0x100000, 0x000000)) { | ||
| 176 | nv_error(priv, "channel %d [%s] kick timeout\n", | ||
| 177 | chan->base.chid, nvkm_client_name(chan)); | ||
| 178 | return -EBUSY; | ||
| 179 | } | ||
| 180 | |||
| 181 | return 0; | ||
| 182 | } | ||
| 183 | |||
| 184 | static int | ||
| 185 | gk104_fifo_context_detach(struct nvkm_object *parent, bool suspend, | 169 | gk104_fifo_context_detach(struct nvkm_object *parent, bool suspend, |
| 186 | struct nvkm_object *object) | 170 | struct nvkm_object *object) |
| 187 | { | 171 | { |
| 188 | struct nvkm_bar *bar = nvkm_bar(parent); | 172 | struct nvkm_bar *bar = nvkm_bar(parent); |
| 173 | struct gk104_fifo_priv *priv = (void *)parent->engine; | ||
| 189 | struct gk104_fifo_base *base = (void *)parent->parent; | 174 | struct gk104_fifo_base *base = (void *)parent->parent; |
| 190 | struct gk104_fifo_chan *chan = (void *)parent; | 175 | struct gk104_fifo_chan *chan = (void *)parent; |
| 191 | u32 addr; | 176 | u32 addr; |
| 192 | int ret; | ||
| 193 | 177 | ||
| 194 | switch (nv_engidx(object->engine)) { | 178 | switch (nv_engidx(object->engine)) { |
| 195 | case NVDEV_ENGINE_SW : return 0; | 179 | case NVDEV_ENGINE_SW : return 0; |
| @@ -204,9 +188,13 @@ gk104_fifo_context_detach(struct nvkm_object *parent, bool suspend, | |||
| 204 | return -EINVAL; | 188 | return -EINVAL; |
| 205 | } | 189 | } |
| 206 | 190 | ||
| 207 | ret = gk104_fifo_chan_kick(chan); | 191 | nv_wr32(priv, 0x002634, chan->base.chid); |
| 208 | if (ret && suspend) | 192 | if (!nv_wait(priv, 0x002634, 0xffffffff, chan->base.chid)) { |
| 209 | return ret; | 193 | nv_error(priv, "channel %d [%s] kick timeout\n", |
| 194 | chan->base.chid, nvkm_client_name(chan)); | ||
| 195 | if (suspend) | ||
| 196 | return -EBUSY; | ||
| 197 | } | ||
| 210 | 198 | ||
| 211 | if (addr) { | 199 | if (addr) { |
| 212 | nv_wo32(base, addr + 0x00, 0x00000000); | 200 | nv_wo32(base, addr + 0x00, 0x00000000); |
| @@ -331,7 +319,6 @@ gk104_fifo_chan_fini(struct nvkm_object *object, bool suspend) | |||
| 331 | gk104_fifo_runlist_update(priv, chan->engine); | 319 | gk104_fifo_runlist_update(priv, chan->engine); |
| 332 | } | 320 | } |
| 333 | 321 | ||
| 334 | gk104_fifo_chan_kick(chan); | ||
| 335 | nv_wr32(priv, 0x800000 + (chid * 8), 0x00000000); | 322 | nv_wr32(priv, 0x800000 + (chid * 8), 0x00000000); |
| 336 | return nvkm_fifo_channel_fini(&chan->base, suspend); | 323 | return nvkm_fifo_channel_fini(&chan->base, suspend); |
| 337 | } | 324 | } |
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c index 654c8daeb5ab..97ad3bcb99a7 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c | |||
| @@ -2492,7 +2492,7 @@ int vmw_execbuf_process(struct drm_file *file_priv, | |||
| 2492 | ret = ttm_eu_reserve_buffers(&ticket, &sw_context->validate_nodes, | 2492 | ret = ttm_eu_reserve_buffers(&ticket, &sw_context->validate_nodes, |
| 2493 | true, NULL); | 2493 | true, NULL); |
| 2494 | if (unlikely(ret != 0)) | 2494 | if (unlikely(ret != 0)) |
| 2495 | goto out_err; | 2495 | goto out_err_nores; |
| 2496 | 2496 | ||
| 2497 | ret = vmw_validate_buffers(dev_priv, sw_context); | 2497 | ret = vmw_validate_buffers(dev_priv, sw_context); |
| 2498 | if (unlikely(ret != 0)) | 2498 | if (unlikely(ret != 0)) |
| @@ -2536,6 +2536,7 @@ int vmw_execbuf_process(struct drm_file *file_priv, | |||
| 2536 | vmw_resource_relocations_free(&sw_context->res_relocations); | 2536 | vmw_resource_relocations_free(&sw_context->res_relocations); |
| 2537 | 2537 | ||
| 2538 | vmw_fifo_commit(dev_priv, command_size); | 2538 | vmw_fifo_commit(dev_priv, command_size); |
| 2539 | mutex_unlock(&dev_priv->binding_mutex); | ||
| 2539 | 2540 | ||
| 2540 | vmw_query_bo_switch_commit(dev_priv, sw_context); | 2541 | vmw_query_bo_switch_commit(dev_priv, sw_context); |
| 2541 | ret = vmw_execbuf_fence_commands(file_priv, dev_priv, | 2542 | ret = vmw_execbuf_fence_commands(file_priv, dev_priv, |
| @@ -2551,7 +2552,6 @@ int vmw_execbuf_process(struct drm_file *file_priv, | |||
| 2551 | DRM_ERROR("Fence submission error. Syncing.\n"); | 2552 | DRM_ERROR("Fence submission error. Syncing.\n"); |
| 2552 | 2553 | ||
| 2553 | vmw_resource_list_unreserve(&sw_context->resource_list, false); | 2554 | vmw_resource_list_unreserve(&sw_context->resource_list, false); |
| 2554 | mutex_unlock(&dev_priv->binding_mutex); | ||
| 2555 | 2555 | ||
| 2556 | ttm_eu_fence_buffer_objects(&ticket, &sw_context->validate_nodes, | 2556 | ttm_eu_fence_buffer_objects(&ticket, &sw_context->validate_nodes, |
| 2557 | (void *) fence); | 2557 | (void *) fence); |
