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path: root/drivers/gpu/drm/tegra/hdmi.h
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Diffstat (limited to 'drivers/gpu/drm/tegra/hdmi.h')
-rw-r--r--drivers/gpu/drm/tegra/hdmi.h21
1 files changed, 20 insertions, 1 deletions
diff --git a/drivers/gpu/drm/tegra/hdmi.h b/drivers/gpu/drm/tegra/hdmi.h
index a882514389cd..2339f134a09a 100644
--- a/drivers/gpu/drm/tegra/hdmi.h
+++ b/drivers/gpu/drm/tegra/hdmi.h
@@ -468,9 +468,20 @@
468#define HDMI_NV_PDISP_KEY_SKEY_INDEX 0xa3 468#define HDMI_NV_PDISP_KEY_SKEY_INDEX 0xa3
469 469
470#define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0 0xac 470#define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0 0xac
471#define AUDIO_CNTRL0_INJECT_NULLSMPL (1 << 29) 471#define SOR_AUDIO_CNTRL0_SOURCE_SELECT_AUTO (0 << 20)
472#define SOR_AUDIO_CNTRL0_SOURCE_SELECT_SPDIF (1 << 20)
473#define SOR_AUDIO_CNTRL0_SOURCE_SELECT_HDAL (2 << 20)
474#define SOR_AUDIO_CNTRL0_INJECT_NULLSMPL (1 << 29)
475#define HDMI_NV_PDISP_SOR_AUDIO_SPARE0 0xae
476#define SOR_AUDIO_SPARE0_HBR_ENABLE (1 << 27)
477#define HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0 0xba
478#define SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID (1 << 30)
479#define SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK 0xffff
480#define HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1 0xbb
472#define HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR 0xbc 481#define HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR 0xbc
473#define HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE 0xbd 482#define HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE 0xbd
483#define SOR_AUDIO_HDA_PRESENSE_VALID (1 << 1)
484#define SOR_AUDIO_HDA_PRESENSE_PRESENT (1 << 0)
474 485
475#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320 0xbf 486#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320 0xbf
476#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441 0xc0 487#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441 0xc0
@@ -481,6 +492,14 @@
481#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920 0xc5 492#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920 0xc5
482#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT 0xc5 493#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT 0xc5
483 494
495#define HDMI_NV_PDISP_INT_STATUS 0xcc
496#define INT_SCRATCH (1 << 3)
497#define INT_CP_REQUEST (1 << 2)
498#define INT_CODEC_SCRATCH1 (1 << 1)
499#define INT_CODEC_SCRATCH0 (1 << 0)
500#define HDMI_NV_PDISP_INT_MASK 0xcd
501#define HDMI_NV_PDISP_INT_ENABLE 0xce
502
484#define HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT 0xd1 503#define HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT 0xd1
485#define PEAK_CURRENT_LANE0(x) (((x) & 0x7f) << 0) 504#define PEAK_CURRENT_LANE0(x) (((x) & 0x7f) << 0)
486#define PEAK_CURRENT_LANE1(x) (((x) & 0x7f) << 8) 505#define PEAK_CURRENT_LANE1(x) (((x) & 0x7f) << 8)