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path: root/drivers/gpu/drm/radeon/radeon_object.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_object.c')
-rw-r--r--drivers/gpu/drm/radeon/radeon_object.c52
1 files changed, 30 insertions, 22 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index b91118ccef86..883c95d8d90f 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -84,17 +84,34 @@ void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
84 rbo->placement.fpfn = 0; 84 rbo->placement.fpfn = 0;
85 rbo->placement.lpfn = 0; 85 rbo->placement.lpfn = 0;
86 rbo->placement.placement = rbo->placements; 86 rbo->placement.placement = rbo->placements;
87 rbo->placement.busy_placement = rbo->placements;
88 if (domain & RADEON_GEM_DOMAIN_VRAM) 87 if (domain & RADEON_GEM_DOMAIN_VRAM)
89 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | 88 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
90 TTM_PL_FLAG_VRAM; 89 TTM_PL_FLAG_VRAM;
91 if (domain & RADEON_GEM_DOMAIN_GTT) 90 if (domain & RADEON_GEM_DOMAIN_GTT) {
92 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 91 if (rbo->rdev->flags & RADEON_IS_AGP) {
93 if (domain & RADEON_GEM_DOMAIN_CPU) 92 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT;
94 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; 93 } else {
94 rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;
95 }
96 }
97 if (domain & RADEON_GEM_DOMAIN_CPU) {
98 if (rbo->rdev->flags & RADEON_IS_AGP) {
99 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_SYSTEM;
100 } else {
101 rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM;
102 }
103 }
95 if (!c) 104 if (!c)
96 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; 105 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
97 rbo->placement.num_placement = c; 106 rbo->placement.num_placement = c;
107
108 c = 0;
109 rbo->placement.busy_placement = rbo->busy_placements;
110 if (rbo->rdev->flags & RADEON_IS_AGP) {
111 rbo->busy_placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT;
112 } else {
113 rbo->busy_placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;
114 }
98 rbo->placement.num_busy_placement = c; 115 rbo->placement.num_busy_placement = c;
99} 116}
100 117
@@ -140,7 +157,7 @@ int radeon_bo_create(struct radeon_device *rdev,
140 /* Kernel allocation are uninterruptible */ 157 /* Kernel allocation are uninterruptible */
141 down_read(&rdev->pm.mclk_lock); 158 down_read(&rdev->pm.mclk_lock);
142 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type, 159 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
143 &bo->placement, page_align, 0, !kernel, NULL, 160 &bo->placement, page_align, !kernel, NULL,
144 acc_size, sg, &radeon_ttm_bo_destroy); 161 acc_size, sg, &radeon_ttm_bo_destroy);
145 up_read(&rdev->pm.mclk_lock); 162 up_read(&rdev->pm.mclk_lock);
146 if (unlikely(r != 0)) { 163 if (unlikely(r != 0)) {
@@ -240,7 +257,7 @@ int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
240 } 257 }
241 for (i = 0; i < bo->placement.num_placement; i++) 258 for (i = 0; i < bo->placement.num_placement; i++)
242 bo->placements[i] |= TTM_PL_FLAG_NO_EVICT; 259 bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
243 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false); 260 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
244 if (likely(r == 0)) { 261 if (likely(r == 0)) {
245 bo->pin_count = 1; 262 bo->pin_count = 1;
246 if (gpu_addr != NULL) 263 if (gpu_addr != NULL)
@@ -269,7 +286,7 @@ int radeon_bo_unpin(struct radeon_bo *bo)
269 return 0; 286 return 0;
270 for (i = 0; i < bo->placement.num_placement; i++) 287 for (i = 0; i < bo->placement.num_placement; i++)
271 bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT; 288 bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
272 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false); 289 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
273 if (unlikely(r != 0)) 290 if (unlikely(r != 0))
274 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo); 291 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
275 return r; 292 return r;
@@ -340,7 +357,6 @@ int radeon_bo_list_validate(struct list_head *head)
340{ 357{
341 struct radeon_bo_list *lobj; 358 struct radeon_bo_list *lobj;
342 struct radeon_bo *bo; 359 struct radeon_bo *bo;
343 u32 domain;
344 int r; 360 int r;
345 361
346 r = ttm_eu_reserve_buffers(head); 362 r = ttm_eu_reserve_buffers(head);
@@ -350,17 +366,9 @@ int radeon_bo_list_validate(struct list_head *head)
350 list_for_each_entry(lobj, head, tv.head) { 366 list_for_each_entry(lobj, head, tv.head) {
351 bo = lobj->bo; 367 bo = lobj->bo;
352 if (!bo->pin_count) { 368 if (!bo->pin_count) {
353 domain = lobj->wdomain ? lobj->wdomain : lobj->rdomain;
354
355 retry:
356 radeon_ttm_placement_from_domain(bo, domain);
357 r = ttm_bo_validate(&bo->tbo, &bo->placement, 369 r = ttm_bo_validate(&bo->tbo, &bo->placement,
358 true, false, false); 370 true, false);
359 if (unlikely(r)) { 371 if (unlikely(r)) {
360 if (r != -ERESTARTSYS && domain == RADEON_GEM_DOMAIN_VRAM) {
361 domain |= RADEON_GEM_DOMAIN_GTT;
362 goto retry;
363 }
364 return r; 372 return r;
365 } 373 }
366 } 374 }
@@ -384,7 +392,7 @@ int radeon_bo_get_surface_reg(struct radeon_bo *bo)
384 int steal; 392 int steal;
385 int i; 393 int i;
386 394
387 BUG_ON(!atomic_read(&bo->tbo.reserved)); 395 BUG_ON(!radeon_bo_is_reserved(bo));
388 396
389 if (!bo->tiling_flags) 397 if (!bo->tiling_flags)
390 return 0; 398 return 0;
@@ -510,7 +518,7 @@ void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
510 uint32_t *tiling_flags, 518 uint32_t *tiling_flags,
511 uint32_t *pitch) 519 uint32_t *pitch)
512{ 520{
513 BUG_ON(!atomic_read(&bo->tbo.reserved)); 521 BUG_ON(!radeon_bo_is_reserved(bo));
514 if (tiling_flags) 522 if (tiling_flags)
515 *tiling_flags = bo->tiling_flags; 523 *tiling_flags = bo->tiling_flags;
516 if (pitch) 524 if (pitch)
@@ -520,7 +528,7 @@ void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
520int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved, 528int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
521 bool force_drop) 529 bool force_drop)
522{ 530{
523 BUG_ON(!atomic_read(&bo->tbo.reserved)); 531 BUG_ON(!radeon_bo_is_reserved(bo) && !force_drop);
524 532
525 if (!(bo->tiling_flags & RADEON_TILING_SURFACE)) 533 if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
526 return 0; 534 return 0;
@@ -575,7 +583,7 @@ int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
575 /* hurrah the memory is not visible ! */ 583 /* hurrah the memory is not visible ! */
576 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM); 584 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
577 rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT; 585 rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
578 r = ttm_bo_validate(bo, &rbo->placement, false, true, false); 586 r = ttm_bo_validate(bo, &rbo->placement, false, false);
579 if (unlikely(r != 0)) 587 if (unlikely(r != 0))
580 return r; 588 return r;
581 offset = bo->mem.start << PAGE_SHIFT; 589 offset = bo->mem.start << PAGE_SHIFT;