diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_mode.h')
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_mode.h | 49 |
1 files changed, 37 insertions, 12 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h index 0c28ca3964b1..92c5f473cf08 100644 --- a/drivers/gpu/drm/radeon/radeon_mode.h +++ b/drivers/gpu/drm/radeon/radeon_mode.h | |||
@@ -251,8 +251,23 @@ struct radeon_mode_info { | |||
251 | 251 | ||
252 | /* pointer to fbdev info structure */ | 252 | /* pointer to fbdev info structure */ |
253 | struct radeon_fbdev *rfbdev; | 253 | struct radeon_fbdev *rfbdev; |
254 | /* firmware flags */ | ||
255 | u16 firmware_flags; | ||
256 | /* pointer to backlight encoder */ | ||
257 | struct radeon_encoder *bl_encoder; | ||
254 | }; | 258 | }; |
255 | 259 | ||
260 | #define RADEON_MAX_BL_LEVEL 0xFF | ||
261 | |||
262 | #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) | ||
263 | |||
264 | struct radeon_backlight_privdata { | ||
265 | struct radeon_encoder *encoder; | ||
266 | uint8_t negative; | ||
267 | }; | ||
268 | |||
269 | #endif | ||
270 | |||
256 | #define MAX_H_CODE_TIMING_LEN 32 | 271 | #define MAX_H_CODE_TIMING_LEN 32 |
257 | #define MAX_V_CODE_TIMING_LEN 32 | 272 | #define MAX_V_CODE_TIMING_LEN 32 |
258 | 273 | ||
@@ -268,6 +283,18 @@ struct radeon_tv_regs { | |||
268 | uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; | 283 | uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; |
269 | }; | 284 | }; |
270 | 285 | ||
286 | struct radeon_atom_ss { | ||
287 | uint16_t percentage; | ||
288 | uint8_t type; | ||
289 | uint16_t step; | ||
290 | uint8_t delay; | ||
291 | uint8_t range; | ||
292 | uint8_t refdiv; | ||
293 | /* asic_ss */ | ||
294 | uint16_t rate; | ||
295 | uint16_t amount; | ||
296 | }; | ||
297 | |||
271 | struct radeon_crtc { | 298 | struct radeon_crtc { |
272 | struct drm_crtc base; | 299 | struct drm_crtc base; |
273 | int crtc_id; | 300 | int crtc_id; |
@@ -292,6 +319,16 @@ struct radeon_crtc { | |||
292 | /* page flipping */ | 319 | /* page flipping */ |
293 | struct radeon_unpin_work *unpin_work; | 320 | struct radeon_unpin_work *unpin_work; |
294 | int deferred_flip_completion; | 321 | int deferred_flip_completion; |
322 | /* pll sharing */ | ||
323 | struct radeon_atom_ss ss; | ||
324 | bool ss_enabled; | ||
325 | u32 adjusted_clock; | ||
326 | int bpc; | ||
327 | u32 pll_reference_div; | ||
328 | u32 pll_post_div; | ||
329 | u32 pll_flags; | ||
330 | struct drm_encoder *encoder; | ||
331 | struct drm_connector *connector; | ||
295 | }; | 332 | }; |
296 | 333 | ||
297 | struct radeon_encoder_primary_dac { | 334 | struct radeon_encoder_primary_dac { |
@@ -345,18 +382,6 @@ struct radeon_encoder_ext_tmds { | |||
345 | }; | 382 | }; |
346 | 383 | ||
347 | /* spread spectrum */ | 384 | /* spread spectrum */ |
348 | struct radeon_atom_ss { | ||
349 | uint16_t percentage; | ||
350 | uint8_t type; | ||
351 | uint16_t step; | ||
352 | uint8_t delay; | ||
353 | uint8_t range; | ||
354 | uint8_t refdiv; | ||
355 | /* asic_ss */ | ||
356 | uint16_t rate; | ||
357 | uint16_t amount; | ||
358 | }; | ||
359 | |||
360 | struct radeon_encoder_atom_dig { | 385 | struct radeon_encoder_atom_dig { |
361 | bool linkb; | 386 | bool linkb; |
362 | /* atom dig */ | 387 | /* atom dig */ |