diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_device.c')
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon_device.c | 38 |
1 files changed, 25 insertions, 13 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c index b51e15725c6e..c4d00a171411 100644 --- a/drivers/gpu/drm/radeon/radeon_device.c +++ b/drivers/gpu/drm/radeon/radeon_device.c | |||
| @@ -716,7 +716,7 @@ int radeon_device_init(struct radeon_device *rdev, | |||
| 716 | 716 | ||
| 717 | /* mutex initialization are all done here so we | 717 | /* mutex initialization are all done here so we |
| 718 | * can recall function without having locking issues */ | 718 | * can recall function without having locking issues */ |
| 719 | mutex_init(&rdev->cs_mutex); | 719 | radeon_mutex_init(&rdev->cs_mutex); |
| 720 | mutex_init(&rdev->ib_pool.mutex); | 720 | mutex_init(&rdev->ib_pool.mutex); |
| 721 | mutex_init(&rdev->cp.mutex); | 721 | mutex_init(&rdev->cp.mutex); |
| 722 | mutex_init(&rdev->dc_hw_i2c_mutex); | 722 | mutex_init(&rdev->dc_hw_i2c_mutex); |
| @@ -750,14 +750,15 @@ int radeon_device_init(struct radeon_device *rdev, | |||
| 750 | 750 | ||
| 751 | /* set DMA mask + need_dma32 flags. | 751 | /* set DMA mask + need_dma32 flags. |
| 752 | * PCIE - can handle 40-bits. | 752 | * PCIE - can handle 40-bits. |
| 753 | * IGP - can handle 40-bits (in theory) | 753 | * IGP - can handle 40-bits |
| 754 | * AGP - generally dma32 is safest | 754 | * AGP - generally dma32 is safest |
| 755 | * PCI - only dma32 | 755 | * PCI - dma32 for legacy pci gart, 40 bits on newer asics |
| 756 | */ | 756 | */ |
| 757 | rdev->need_dma32 = false; | 757 | rdev->need_dma32 = false; |
| 758 | if (rdev->flags & RADEON_IS_AGP) | 758 | if (rdev->flags & RADEON_IS_AGP) |
| 759 | rdev->need_dma32 = true; | 759 | rdev->need_dma32 = true; |
| 760 | if (rdev->flags & RADEON_IS_PCI) | 760 | if ((rdev->flags & RADEON_IS_PCI) && |
| 761 | (rdev->family < CHIP_RS400)) | ||
| 761 | rdev->need_dma32 = true; | 762 | rdev->need_dma32 = true; |
| 762 | 763 | ||
| 763 | dma_bits = rdev->need_dma32 ? 32 : 40; | 764 | dma_bits = rdev->need_dma32 ? 32 : 40; |
| @@ -817,7 +818,7 @@ int radeon_device_init(struct radeon_device *rdev, | |||
| 817 | radeon_test_moves(rdev); | 818 | radeon_test_moves(rdev); |
| 818 | } | 819 | } |
| 819 | if (radeon_benchmarking) { | 820 | if (radeon_benchmarking) { |
| 820 | radeon_benchmark(rdev); | 821 | radeon_benchmark(rdev, radeon_benchmarking); |
| 821 | } | 822 | } |
| 822 | return 0; | 823 | return 0; |
| 823 | } | 824 | } |
| @@ -954,6 +955,9 @@ int radeon_gpu_reset(struct radeon_device *rdev) | |||
| 954 | int r; | 955 | int r; |
| 955 | int resched; | 956 | int resched; |
| 956 | 957 | ||
| 958 | /* Prevent CS ioctl from interfering */ | ||
| 959 | radeon_mutex_lock(&rdev->cs_mutex); | ||
| 960 | |||
| 957 | radeon_save_bios_scratch_regs(rdev); | 961 | radeon_save_bios_scratch_regs(rdev); |
| 958 | /* block TTM */ | 962 | /* block TTM */ |
| 959 | resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); | 963 | resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); |
| @@ -966,10 +970,15 @@ int radeon_gpu_reset(struct radeon_device *rdev) | |||
| 966 | radeon_restore_bios_scratch_regs(rdev); | 970 | radeon_restore_bios_scratch_regs(rdev); |
| 967 | drm_helper_resume_force_mode(rdev->ddev); | 971 | drm_helper_resume_force_mode(rdev->ddev); |
| 968 | ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); | 972 | ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); |
| 969 | return 0; | ||
| 970 | } | 973 | } |
| 971 | /* bad news, how to tell it to userspace ? */ | 974 | |
| 972 | dev_info(rdev->dev, "GPU reset failed\n"); | 975 | radeon_mutex_unlock(&rdev->cs_mutex); |
| 976 | |||
| 977 | if (r) { | ||
| 978 | /* bad news, how to tell it to userspace ? */ | ||
| 979 | dev_info(rdev->dev, "GPU reset failed\n"); | ||
| 980 | } | ||
| 981 | |||
| 973 | return r; | 982 | return r; |
| 974 | } | 983 | } |
| 975 | 984 | ||
| @@ -981,7 +990,7 @@ struct radeon_debugfs { | |||
| 981 | struct drm_info_list *files; | 990 | struct drm_info_list *files; |
| 982 | unsigned num_files; | 991 | unsigned num_files; |
| 983 | }; | 992 | }; |
| 984 | static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES]; | 993 | static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; |
| 985 | static unsigned _radeon_debugfs_count = 0; | 994 | static unsigned _radeon_debugfs_count = 0; |
| 986 | 995 | ||
| 987 | int radeon_debugfs_add_files(struct radeon_device *rdev, | 996 | int radeon_debugfs_add_files(struct radeon_device *rdev, |
| @@ -996,14 +1005,17 @@ int radeon_debugfs_add_files(struct radeon_device *rdev, | |||
| 996 | return 0; | 1005 | return 0; |
| 997 | } | 1006 | } |
| 998 | } | 1007 | } |
| 999 | if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) { | 1008 | |
| 1000 | DRM_ERROR("Reached maximum number of debugfs files.\n"); | 1009 | i = _radeon_debugfs_count + 1; |
| 1001 | DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n"); | 1010 | if (i > RADEON_DEBUGFS_MAX_COMPONENTS) { |
| 1011 | DRM_ERROR("Reached maximum number of debugfs components.\n"); | ||
| 1012 | DRM_ERROR("Report so we increase " | ||
| 1013 | "RADEON_DEBUGFS_MAX_COMPONENTS.\n"); | ||
| 1002 | return -EINVAL; | 1014 | return -EINVAL; |
| 1003 | } | 1015 | } |
| 1004 | _radeon_debugfs[_radeon_debugfs_count].files = files; | 1016 | _radeon_debugfs[_radeon_debugfs_count].files = files; |
| 1005 | _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles; | 1017 | _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles; |
| 1006 | _radeon_debugfs_count++; | 1018 | _radeon_debugfs_count = i; |
| 1007 | #if defined(CONFIG_DEBUG_FS) | 1019 | #if defined(CONFIG_DEBUG_FS) |
| 1008 | drm_debugfs_create_files(files, nfiles, | 1020 | drm_debugfs_create_files(files, nfiles, |
| 1009 | rdev->ddev->control->debugfs_root, | 1021 | rdev->ddev->control->debugfs_root, |
