diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_clocks.c')
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon_clocks.c | 23 |
1 files changed, 21 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_clocks.c b/drivers/gpu/drm/radeon/radeon_clocks.c index a81354167621..b062109efbee 100644 --- a/drivers/gpu/drm/radeon/radeon_clocks.c +++ b/drivers/gpu/drm/radeon/radeon_clocks.c | |||
| @@ -44,6 +44,10 @@ uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev) | |||
| 44 | 44 | ||
| 45 | ref_div = | 45 | ref_div = |
| 46 | RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK; | 46 | RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK; |
| 47 | |||
| 48 | if (ref_div == 0) | ||
| 49 | return 0; | ||
| 50 | |||
| 47 | sclk = fb_div / ref_div; | 51 | sclk = fb_div / ref_div; |
| 48 | 52 | ||
| 49 | post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK; | 53 | post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK; |
| @@ -70,6 +74,10 @@ static uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev) | |||
| 70 | 74 | ||
| 71 | ref_div = | 75 | ref_div = |
| 72 | RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK; | 76 | RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK; |
| 77 | |||
| 78 | if (ref_div == 0) | ||
| 79 | return 0; | ||
| 80 | |||
| 73 | mclk = fb_div / ref_div; | 81 | mclk = fb_div / ref_div; |
| 74 | 82 | ||
| 75 | post_div = RREG32_PLL(RADEON_MCLK_CNTL) & 0x7; | 83 | post_div = RREG32_PLL(RADEON_MCLK_CNTL) & 0x7; |
| @@ -98,8 +106,19 @@ void radeon_get_clock_info(struct drm_device *dev) | |||
| 98 | ret = radeon_combios_get_clock_info(dev); | 106 | ret = radeon_combios_get_clock_info(dev); |
| 99 | 107 | ||
| 100 | if (ret) { | 108 | if (ret) { |
| 101 | if (p1pll->reference_div < 2) | 109 | if (p1pll->reference_div < 2) { |
| 102 | p1pll->reference_div = 12; | 110 | if (!ASIC_IS_AVIVO(rdev)) { |
| 111 | u32 tmp = RREG32_PLL(RADEON_PPLL_REF_DIV); | ||
| 112 | if (ASIC_IS_R300(rdev)) | ||
| 113 | p1pll->reference_div = | ||
| 114 | (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT; | ||
| 115 | else | ||
| 116 | p1pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK; | ||
| 117 | if (p1pll->reference_div < 2) | ||
| 118 | p1pll->reference_div = 12; | ||
| 119 | } else | ||
| 120 | p1pll->reference_div = 12; | ||
| 121 | } | ||
| 103 | if (p2pll->reference_div < 2) | 122 | if (p2pll->reference_div < 2) |
| 104 | p2pll->reference_div = 12; | 123 | p2pll->reference_div = 12; |
| 105 | if (rdev->family < CHIP_RS600) { | 124 | if (rdev->family < CHIP_RS600) { |
