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path: root/drivers/gpu/drm/radeon/evergreen.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/evergreen.c')
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index f37d39d2bbbc..85995b4e3338 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -2345,6 +2345,9 @@ void evergreen_bandwidth_update(struct radeon_device *rdev)
2345 u32 num_heads = 0, lb_size; 2345 u32 num_heads = 0, lb_size;
2346 int i; 2346 int i;
2347 2347
2348 if (!rdev->mode_info.mode_config_initialized)
2349 return;
2350
2348 radeon_update_display_priority(rdev); 2351 radeon_update_display_priority(rdev);
2349 2352
2350 for (i = 0; i < rdev->num_crtc; i++) { 2353 for (i = 0; i < rdev->num_crtc; i++) {
@@ -2552,6 +2555,7 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav
2552 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); 2555 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
2553 tmp |= EVERGREEN_CRTC_BLANK_DATA_EN; 2556 tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
2554 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp); 2557 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
2558 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
2555 } 2559 }
2556 } else { 2560 } else {
2557 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); 2561 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);