1 files changed, 169 insertions, 84 deletions

diff --git a/drivers/gpu/drm/radeon/cik_sdma.c b/drivers/gpu/drm/radeon/cik_sdma.c
index 8e9d0f1d858e..192278bc993c 100644
--- a/drivers/gpu/drm/radeon/cik_sdma.c
+++ b/drivers/gpu/drm/radeon/cik_sdma.c
@@ -24,6 +24,7 @@
 #include <linux/firmware.h>
 #include <drm/drmP.h>
 #include "radeon.h"
+#include "radeon_ucode.h"
 #include "radeon_asic.h"
 #include "radeon_trace.h"
 #include "cikd.h"
@@ -118,6 +119,7 @@ void cik_sdma_set_wptr(struct radeon_device *rdev,
                 reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET;
 
         WREG32(reg, (ring->wptr << 2) & 0x3fffc);
+        (void)RREG32(reg);
 }
 
 /**
@@ -419,7 +421,6 @@ static int cik_sdma_rlc_resume(struct radeon_device *rdev)
  */
 static int cik_sdma_load_microcode(struct radeon_device *rdev)
 {
-        const __be32 *fw_data;
         int i;
 
         if (!rdev->sdma_fw)
@@ -428,19 +429,48 @@ static int cik_sdma_load_microcode(struct radeon_device *rdev)
         /* halt the MEs */
         cik_sdma_enable(rdev, false);
 
-        /* sdma0 */
-        fw_data = (const __be32 *)rdev->sdma_fw->data;
-        WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0);
-        for (i = 0; i < CIK_SDMA_UCODE_SIZE; i++)
-                WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, be32_to_cpup(fw_data++));
-        WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);
-
-        /* sdma1 */
-        fw_data = (const __be32 *)rdev->sdma_fw->data;
-        WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0);
-        for (i = 0; i < CIK_SDMA_UCODE_SIZE; i++)
-                WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, be32_to_cpup(fw_data++));
-        WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);
+        if (rdev->new_fw) {
+                const struct sdma_firmware_header_v1_0 *hdr =
+                        (const struct sdma_firmware_header_v1_0 *)rdev->sdma_fw->data;
+                const __le32 *fw_data;
+                u32 fw_size;
+
+                radeon_ucode_print_sdma_hdr(&hdr->header);
+
+                /* sdma0 */
+                fw_data = (const __le32 *)
+                        (rdev->sdma_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
+                fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
+                WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0);
+                for (i = 0; i < fw_size; i++)
+                        WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, le32_to_cpup(fw_data++));
+                WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);
+
+                /* sdma1 */
+                fw_data = (const __le32 *)
+                        (rdev->sdma_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
+                fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
+                WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0);
+                for (i = 0; i < fw_size; i++)
+                        WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, le32_to_cpup(fw_data++));
+                WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);
+        } else {
+                const __be32 *fw_data;
+
+                /* sdma0 */
+                fw_data = (const __be32 *)rdev->sdma_fw->data;
+                WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0);
+                for (i = 0; i < CIK_SDMA_UCODE_SIZE; i++)
+                        WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, be32_to_cpup(fw_data++));
+                WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);
+
+                /* sdma1 */
+                fw_data = (const __be32 *)rdev->sdma_fw->data;
+                WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0);
+                for (i = 0; i < CIK_SDMA_UCODE_SIZE; i++)
+                        WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, be32_to_cpup(fw_data++));
+                WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);
+        }
 
         WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0);
         WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0);
@@ -566,7 +596,7 @@ int cik_copy_dma(struct radeon_device *rdev,
                 return r;
         }
 
-        radeon_ring_unlock_commit(rdev, ring);
+        radeon_ring_unlock_commit(rdev, ring, false);
         radeon_semaphore_free(rdev, &sem, *fence);
 
         return r;
@@ -608,7 +638,7 @@ int cik_sdma_ring_test(struct radeon_device *rdev,
         radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr));
         radeon_ring_write(ring, 1); /* number of DWs to follow */
         radeon_ring_write(ring, 0xDEADBEEF);
-        radeon_ring_unlock_commit(rdev, ring);
+        radeon_ring_unlock_commit(rdev, ring, false);
 
         for (i = 0; i < rdev->usec_timeout; i++) {
                 tmp = readl(ptr);
@@ -665,7 +695,7 @@ int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
         ib.ptr[4] = 0xDEADBEEF;
         ib.length_dw = 5;
 
-        r = radeon_ib_schedule(rdev, &ib, NULL);
+        r = radeon_ib_schedule(rdev, &ib, NULL, false);
         if (r) {
                 radeon_ib_free(rdev, &ib);
                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
@@ -719,7 +749,43 @@ bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
 }
 
 /**
- * cik_sdma_vm_set_page - update the page tables using sDMA
+ * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART
+ *
+ * @rdev: radeon_device pointer
+ * @ib: indirect buffer to fill with commands
+ * @pe: addr of the page entry
+ * @src: src addr to copy from
+ * @count: number of page entries to update
+ *
+ * Update PTEs by copying them from the GART using sDMA (CIK).
+ */
+void cik_sdma_vm_copy_pages(struct radeon_device *rdev,
+                            struct radeon_ib *ib,
+                            uint64_t pe, uint64_t src,
+                            unsigned count)
+{
+        while (count) {
+                unsigned bytes = count * 8;
+                if (bytes > 0x1FFFF8)
+                        bytes = 0x1FFFF8;
+
+                ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY,
+                        SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
+                ib->ptr[ib->length_dw++] = bytes;
+                ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
+                ib->ptr[ib->length_dw++] = lower_32_bits(src);
+                ib->ptr[ib->length_dw++] = upper_32_bits(src);
+                ib->ptr[ib->length_dw++] = lower_32_bits(pe);
+                ib->ptr[ib->length_dw++] = upper_32_bits(pe);
+
+                pe += bytes;
+                src += bytes;
+                count -= bytes / 8;
+        }
+}
+
+/**
+ * cik_sdma_vm_write_pages - update PTEs by writing them manually
  *
  * @rdev: radeon_device pointer
  * @ib: indirect buffer to fill with commands
@@ -729,84 +795,103 @@ bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
  * @incr: increase next addr by incr bytes
  * @flags: access flags
  *
- * Update the page tables using sDMA (CIK).
+ * Update PTEs by writing them manually using sDMA (CIK).
  */
-void cik_sdma_vm_set_page(struct radeon_device *rdev,
-                          struct radeon_ib *ib,
-                          uint64_t pe,
-                          uint64_t addr, unsigned count,
-                          uint32_t incr, uint32_t flags)
+void cik_sdma_vm_write_pages(struct radeon_device *rdev,
+                             struct radeon_ib *ib,
+                             uint64_t pe,
+                             uint64_t addr, unsigned count,
+                             uint32_t incr, uint32_t flags)
 {
         uint64_t value;
         unsigned ndw;
 
-        trace_radeon_vm_set_page(pe, addr, count, incr, flags);
-
-        if (flags == R600_PTE_GART) {
-                uint64_t src = rdev->gart.table_addr + (addr >> 12) * 8;
-                while (count) {
-                        unsigned bytes = count * 8;
-                        if (bytes > 0x1FFFF8)
-                                bytes = 0x1FFFF8;
-
-                        ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
-                        ib->ptr[ib->length_dw++] = bytes;
-                        ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
-                        ib->ptr[ib->length_dw++] = lower_32_bits(src);
-                        ib->ptr[ib->length_dw++] = upper_32_bits(src);
-                        ib->ptr[ib->length_dw++] = lower_32_bits(pe);
-                        ib->ptr[ib->length_dw++] = upper_32_bits(pe);
-
-                        pe += bytes;
-                        src += bytes;
-                        count -= bytes / 8;
-                }
-        } else if (flags & R600_PTE_SYSTEM) {
-                while (count) {
-                        ndw = count * 2;
-                        if (ndw > 0xFFFFE)
-                                ndw = 0xFFFFE;
-
-                        /* for non-physically contiguous pages (system) */
-                        ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
-                        ib->ptr[ib->length_dw++] = pe;
-                        ib->ptr[ib->length_dw++] = upper_32_bits(pe);
-                        ib->ptr[ib->length_dw++] = ndw;
-                        for (; ndw > 0; ndw -= 2, --count, pe += 8) {
+        while (count) {
+                ndw = count * 2;
+                if (ndw > 0xFFFFE)
+                        ndw = 0xFFFFE;
+
+                /* for non-physically contiguous pages (system) */
+                ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
+                        SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
+                ib->ptr[ib->length_dw++] = pe;
+                ib->ptr[ib->length_dw++] = upper_32_bits(pe);
+                ib->ptr[ib->length_dw++] = ndw;
+                for (; ndw > 0; ndw -= 2, --count, pe += 8) {
+                        if (flags & R600_PTE_SYSTEM) {
                                 value = radeon_vm_map_gart(rdev, addr);
                                 value &= 0xFFFFFFFFFFFFF000ULL;
-                                addr += incr;
-                                value |= flags;
-                                ib->ptr[ib->length_dw++] = value;
-                                ib->ptr[ib->length_dw++] = upper_32_bits(value);
-                        }
-                }
-        } else {
-                while (count) {
-                        ndw = count;
-                        if (ndw > 0x7FFFF)
-                                ndw = 0x7FFFF;
-
-                        if (flags & R600_PTE_VALID)
+                        } else if (flags & R600_PTE_VALID) {
                                 value = addr;
-                        else
+                        } else {
                                 value = 0;
-                        /* for physically contiguous pages (vram) */
-                        ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0);
-                        ib->ptr[ib->length_dw++] = pe; /* dst addr */
-                        ib->ptr[ib->length_dw++] = upper_32_bits(pe);
-                        ib->ptr[ib->length_dw++] = flags; /* mask */
-                        ib->ptr[ib->length_dw++] = 0;
-                        ib->ptr[ib->length_dw++] = value; /* value */
+                        }
+                        addr += incr;
+                        value |= flags;
+                        ib->ptr[ib->length_dw++] = value;
                         ib->ptr[ib->length_dw++] = upper_32_bits(value);
-                        ib->ptr[ib->length_dw++] = incr; /* increment size */
-                        ib->ptr[ib->length_dw++] = 0;
-                        ib->ptr[ib->length_dw++] = ndw; /* number of entries */
-                        pe += ndw * 8;
-                        addr += ndw * incr;
-                        count -= ndw;
                 }
         }
+}
+
+/**
+ * cik_sdma_vm_set_pages - update the page tables using sDMA
+ *
+ * @rdev: radeon_device pointer
+ * @ib: indirect buffer to fill with commands
+ * @pe: addr of the page entry
+ * @addr: dst addr to write into pe
+ * @count: number of page entries to update
+ * @incr: increase next addr by incr bytes
+ * @flags: access flags
+ *
+ * Update the page tables using sDMA (CIK).
+ */
+void cik_sdma_vm_set_pages(struct radeon_device *rdev,
+                           struct radeon_ib *ib,
+                           uint64_t pe,
+                           uint64_t addr, unsigned count,
+                           uint32_t incr, uint32_t flags)
+{
+        uint64_t value;
+        unsigned ndw;
+
+        while (count) {
+                ndw = count;
+                if (ndw > 0x7FFFF)
+                        ndw = 0x7FFFF;
+
+                if (flags & R600_PTE_VALID)
+                        value = addr;
+                else
+                        value = 0;
+
+                /* for physically contiguous pages (vram) */
+                ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0);
+                ib->ptr[ib->length_dw++] = pe; /* dst addr */
+                ib->ptr[ib->length_dw++] = upper_32_bits(pe);
+                ib->ptr[ib->length_dw++] = flags; /* mask */
+                ib->ptr[ib->length_dw++] = 0;
+                ib->ptr[ib->length_dw++] = value; /* value */
+                ib->ptr[ib->length_dw++] = upper_32_bits(value);
+                ib->ptr[ib->length_dw++] = incr; /* increment size */
+                ib->ptr[ib->length_dw++] = 0;
+                ib->ptr[ib->length_dw++] = ndw; /* number of entries */
+
+                pe += ndw * 8;
+                addr += ndw * incr;
+                count -= ndw;
+        }
+}
+
+/**
+ * cik_sdma_vm_pad_ib - pad the IB to the required number of dw
+ *
+ * @ib: indirect buffer to fill with padding
+ *
+ */
+void cik_sdma_vm_pad_ib(struct radeon_ib *ib)
+{
         while (ib->length_dw & 0x7)
                 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0);
 }