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path: root/drivers/gpu/drm/omapdrm/dss/dispc.c
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Diffstat (limited to 'drivers/gpu/drm/omapdrm/dss/dispc.c')
-rw-r--r--drivers/gpu/drm/omapdrm/dss/dispc.c15
1 files changed, 8 insertions, 7 deletions
diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c
index ddb9d9d28157..c732d6c70c66 100644
--- a/drivers/gpu/drm/omapdrm/dss/dispc.c
+++ b/drivers/gpu/drm/omapdrm/dss/dispc.c
@@ -2869,8 +2869,8 @@ int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
2869 } else { 2869 } else {
2870 int wbdelay; 2870 int wbdelay;
2871 2871
2872 wbdelay = min(mgr_timings->vfp + mgr_timings->vsync_len + 2872 wbdelay = min(mgr_timings->vfront_porch +
2873 mgr_timings->vbp, 255); 2873 mgr_timings->vsync_len + mgr_timings->vbp, 255);
2874 2874
2875 /* WBDELAYCOUNT */ 2875 /* WBDELAYCOUNT */
2876 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), wbdelay, 7, 0); 2876 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), wbdelay, 7, 0);
@@ -3133,7 +3133,8 @@ bool dispc_mgr_timings_ok(enum omap_channel channel,
3133 3133
3134 if (!_dispc_lcd_timings_ok(timings->hsync_len, 3134 if (!_dispc_lcd_timings_ok(timings->hsync_len,
3135 timings->hfront_porch, timings->hback_porch, 3135 timings->hfront_porch, timings->hback_porch,
3136 timings->vsync_len, timings->vfp, timings->vbp)) 3136 timings->vsync_len, timings->vfront_porch,
3137 timings->vbp))
3137 return false; 3138 return false;
3138 } 3139 }
3139 3140
@@ -3270,12 +3271,12 @@ void dispc_mgr_set_timings(enum omap_channel channel,
3270 3271
3271 if (dss_mgr_is_lcd(channel)) { 3272 if (dss_mgr_is_lcd(channel)) {
3272 _dispc_mgr_set_lcd_timings(channel, t.hsync_len, t.hfront_porch, 3273 _dispc_mgr_set_lcd_timings(channel, t.hsync_len, t.hfront_porch,
3273 t.hback_porch, t.vsync_len, t.vfp, t.vbp, 3274 t.hback_porch, t.vsync_len, t.vfront_porch, t.vbp,
3274 t.vsync_level, t.hsync_level, t.data_pclk_edge, 3275 t.vsync_level, t.hsync_level, t.data_pclk_edge,
3275 t.de_level, t.sync_pclk_edge); 3276 t.de_level, t.sync_pclk_edge);
3276 3277
3277 xtot = t.hactive + t.hfront_porch + t.hsync_len + t.hback_porch; 3278 xtot = t.hactive + t.hfront_porch + t.hsync_len + t.hback_porch;
3278 ytot = t.vactive + t.vfp + t.vsync_len + t.vbp; 3279 ytot = t.vactive + t.vfront_porch + t.vsync_len + t.vbp;
3279 3280
3280 ht = timings->pixelclock / xtot; 3281 ht = timings->pixelclock / xtot;
3281 vt = timings->pixelclock / xtot / ytot; 3282 vt = timings->pixelclock / xtot / ytot;
@@ -3283,7 +3284,7 @@ void dispc_mgr_set_timings(enum omap_channel channel,
3283 DSSDBG("pck %u\n", timings->pixelclock); 3284 DSSDBG("pck %u\n", timings->pixelclock);
3284 DSSDBG("hsync_len %d hfp %d hbp %d vsw %d vfp %d vbp %d\n", 3285 DSSDBG("hsync_len %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
3285 t.hsync_len, t.hfront_porch, t.hback_porch, 3286 t.hsync_len, t.hfront_porch, t.hback_porch,
3286 t.vsync_len, t.vfp, t.vbp); 3287 t.vsync_len, t.vfront_porch, t.vbp);
3287 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n", 3288 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
3288 t.vsync_level, t.hsync_level, t.data_pclk_edge, 3289 t.vsync_level, t.hsync_level, t.data_pclk_edge,
3289 t.de_level, t.sync_pclk_edge); 3290 t.de_level, t.sync_pclk_edge);
@@ -4227,7 +4228,7 @@ static const struct dispc_errata_i734_data {
4227 .hactive = 8, .vactive = 1, 4228 .hactive = 8, .vactive = 1,
4228 .pixelclock = 16000000, 4229 .pixelclock = 16000000,
4229 .hsync_len = 8, .hfront_porch = 4, .hback_porch = 4, 4230 .hsync_len = 8, .hfront_porch = 4, .hback_porch = 4,
4230 .vsync_len = 1, .vfp = 1, .vbp = 1, 4231 .vsync_len = 1, .vfront_porch = 1, .vbp = 1,
4231 .vsync_level = OMAPDSS_SIG_ACTIVE_LOW, 4232 .vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
4232 .hsync_level = OMAPDSS_SIG_ACTIVE_LOW, 4233 .hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
4233 .interlace = false, 4234 .interlace = false,