diff options
Diffstat (limited to 'drivers/gpu/drm/nouveau/nv50_fence.c')
| -rw-r--r-- | drivers/gpu/drm/nouveau/nv50_fence.c | 31 |
1 files changed, 14 insertions, 17 deletions
diff --git a/drivers/gpu/drm/nouveau/nv50_fence.c b/drivers/gpu/drm/nouveau/nv50_fence.c index 0ee363840035..195cf51a7c31 100644 --- a/drivers/gpu/drm/nouveau/nv50_fence.c +++ b/drivers/gpu/drm/nouveau/nv50_fence.c | |||
| @@ -22,8 +22,8 @@ | |||
| 22 | * Authors: Ben Skeggs <bskeggs@redhat.com> | 22 | * Authors: Ben Skeggs <bskeggs@redhat.com> |
| 23 | */ | 23 | */ |
| 24 | 24 | ||
| 25 | #include <core/object.h> | 25 | #include <nvif/os.h> |
| 26 | #include <core/class.h> | 26 | #include <nvif/class.h> |
| 27 | 27 | ||
| 28 | #include "nouveau_drm.h" | 28 | #include "nouveau_drm.h" |
| 29 | #include "nouveau_dma.h" | 29 | #include "nouveau_dma.h" |
| @@ -38,7 +38,6 @@ nv50_fence_context_new(struct nouveau_channel *chan) | |||
| 38 | struct nv10_fence_priv *priv = chan->drm->fence; | 38 | struct nv10_fence_priv *priv = chan->drm->fence; |
| 39 | struct nv10_fence_chan *fctx; | 39 | struct nv10_fence_chan *fctx; |
| 40 | struct ttm_mem_reg *mem = &priv->bo->bo.mem; | 40 | struct ttm_mem_reg *mem = &priv->bo->bo.mem; |
| 41 | struct nouveau_object *object; | ||
| 42 | u32 start = mem->start * PAGE_SIZE; | 41 | u32 start = mem->start * PAGE_SIZE; |
| 43 | u32 limit = start + mem->size - 1; | 42 | u32 limit = start + mem->size - 1; |
| 44 | int ret, i; | 43 | int ret, i; |
| @@ -52,15 +51,14 @@ nv50_fence_context_new(struct nouveau_channel *chan) | |||
| 52 | fctx->base.read = nv10_fence_read; | 51 | fctx->base.read = nv10_fence_read; |
| 53 | fctx->base.sync = nv17_fence_sync; | 52 | fctx->base.sync = nv17_fence_sync; |
| 54 | 53 | ||
| 55 | ret = nouveau_object_new(nv_object(chan->cli), chan->handle, | 54 | ret = nvif_object_init(chan->object, NULL, NvSema, NV_DMA_IN_MEMORY, |
| 56 | NvSema, 0x003d, | 55 | &(struct nv_dma_v0) { |
| 57 | &(struct nv_dma_class) { | 56 | .target = NV_DMA_V0_TARGET_VRAM, |
| 58 | .flags = NV_DMA_TARGET_VRAM | | 57 | .access = NV_DMA_V0_ACCESS_RDWR, |
| 59 | NV_DMA_ACCESS_RDWR, | ||
| 60 | .start = start, | 58 | .start = start, |
| 61 | .limit = limit, | 59 | .limit = limit, |
| 62 | }, sizeof(struct nv_dma_class), | 60 | }, sizeof(struct nv_dma_v0), |
| 63 | &object); | 61 | &fctx->sema); |
| 64 | 62 | ||
| 65 | /* dma objects for display sync channel semaphore blocks */ | 63 | /* dma objects for display sync channel semaphore blocks */ |
| 66 | for (i = 0; !ret && i < dev->mode_config.num_crtc; i++) { | 64 | for (i = 0; !ret && i < dev->mode_config.num_crtc; i++) { |
| @@ -68,15 +66,14 @@ nv50_fence_context_new(struct nouveau_channel *chan) | |||
| 68 | u32 start = bo->bo.mem.start * PAGE_SIZE; | 66 | u32 start = bo->bo.mem.start * PAGE_SIZE; |
| 69 | u32 limit = start + bo->bo.mem.size - 1; | 67 | u32 limit = start + bo->bo.mem.size - 1; |
| 70 | 68 | ||
| 71 | ret = nouveau_object_new(nv_object(chan->cli), chan->handle, | 69 | ret = nvif_object_init(chan->object, NULL, NvEvoSema0 + i, |
| 72 | NvEvoSema0 + i, 0x003d, | 70 | NV_DMA_IN_MEMORY, &(struct nv_dma_v0) { |
| 73 | &(struct nv_dma_class) { | 71 | .target = NV_DMA_V0_TARGET_VRAM, |
| 74 | .flags = NV_DMA_TARGET_VRAM | | 72 | .access = NV_DMA_V0_ACCESS_RDWR, |
| 75 | NV_DMA_ACCESS_RDWR, | ||
| 76 | .start = start, | 73 | .start = start, |
| 77 | .limit = limit, | 74 | .limit = limit, |
| 78 | }, sizeof(struct nv_dma_class), | 75 | }, sizeof(struct nv_dma_v0), |
| 79 | &object); | 76 | &fctx->head[i]); |
| 80 | } | 77 | } |
| 81 | 78 | ||
| 82 | if (ret) | 79 | if (ret) |