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path: root/drivers/gpu/drm/nouveau/nv04_fbcon.c
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Diffstat (limited to 'drivers/gpu/drm/nouveau/nv04_fbcon.c')
-rw-r--r--drivers/gpu/drm/nouveau/nv04_fbcon.c59
1 files changed, 28 insertions, 31 deletions
diff --git a/drivers/gpu/drm/nouveau/nv04_fbcon.c b/drivers/gpu/drm/nouveau/nv04_fbcon.c
index 8fe32bbed99a..4ef602c5469d 100644
--- a/drivers/gpu/drm/nouveau/nv04_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nv04_fbcon.c
@@ -22,8 +22,6 @@
22 * DEALINGS IN THE SOFTWARE. 22 * DEALINGS IN THE SOFTWARE.
23 */ 23 */
24 24
25#include <core/object.h>
26
27#include "nouveau_drm.h" 25#include "nouveau_drm.h"
28#include "nouveau_dma.h" 26#include "nouveau_dma.h"
29#include "nouveau_fbcon.h" 27#include "nouveau_fbcon.h"
@@ -141,8 +139,7 @@ nv04_fbcon_accel_init(struct fb_info *info)
141 struct drm_device *dev = nfbdev->dev; 139 struct drm_device *dev = nfbdev->dev;
142 struct nouveau_drm *drm = nouveau_drm(dev); 140 struct nouveau_drm *drm = nouveau_drm(dev);
143 struct nouveau_channel *chan = drm->channel; 141 struct nouveau_channel *chan = drm->channel;
144 struct nouveau_device *device = nv_device(drm->device); 142 struct nvif_device *device = &drm->device;
145 struct nouveau_object *object;
146 int surface_fmt, pattern_fmt, rect_fmt; 143 int surface_fmt, pattern_fmt, rect_fmt;
147 int ret; 144 int ret;
148 145
@@ -174,35 +171,35 @@ nv04_fbcon_accel_init(struct fb_info *info)
174 return -EINVAL; 171 return -EINVAL;
175 } 172 }
176 173
177 ret = nouveau_object_new(nv_object(chan->cli), NVDRM_CHAN, NvCtxSurf2D, 174 ret = nvif_object_init(chan->object, NULL, 0x0062,
178 device->card_type >= NV_10 ? 0x0062 : 0x0042, 175 device->info.family >= NV_DEVICE_INFO_V0_CELSIUS ?
179 NULL, 0, &object); 176 0x0062 : 0x0042, NULL, 0, &nfbdev->surf2d);
180 if (ret) 177 if (ret)
181 return ret; 178 return ret;
182 179
183 ret = nouveau_object_new(nv_object(chan->cli), NVDRM_CHAN, NvClipRect, 180 ret = nvif_object_init(chan->object, NULL, 0x0019, 0x0019, NULL, 0,
184 0x0019, NULL, 0, &object); 181 &nfbdev->clip);
185 if (ret) 182 if (ret)
186 return ret; 183 return ret;
187 184
188 ret = nouveau_object_new(nv_object(chan->cli), NVDRM_CHAN, NvRop, 185 ret = nvif_object_init(chan->object, NULL, 0x0043, 0x0043, NULL, 0,
189 0x0043, NULL, 0, &object); 186 &nfbdev->rop);
190 if (ret) 187 if (ret)
191 return ret; 188 return ret;
192 189
193 ret = nouveau_object_new(nv_object(chan->cli), NVDRM_CHAN, NvImagePatt, 190 ret = nvif_object_init(chan->object, NULL, 0x0044, 0x0044, NULL, 0,
194 0x0044, NULL, 0, &object); 191 &nfbdev->patt);
195 if (ret) 192 if (ret)
196 return ret; 193 return ret;
197 194
198 ret = nouveau_object_new(nv_object(chan->cli), NVDRM_CHAN, NvGdiRect, 195 ret = nvif_object_init(chan->object, NULL, 0x004a, 0x004a, NULL, 0,
199 0x004a, NULL, 0, &object); 196 &nfbdev->gdi);
200 if (ret) 197 if (ret)
201 return ret; 198 return ret;
202 199
203 ret = nouveau_object_new(nv_object(chan->cli), NVDRM_CHAN, NvImageBlit, 200 ret = nvif_object_init(chan->object, NULL, 0x005f,
204 device->chipset >= 0x11 ? 0x009f : 0x005f, 201 device->info.chipset >= 0x11 ? 0x009f : 0x005f,
205 NULL, 0, &object); 202 NULL, 0, &nfbdev->blit);
206 if (ret) 203 if (ret)
207 return ret; 204 return ret;
208 205
@@ -212,10 +209,10 @@ nv04_fbcon_accel_init(struct fb_info *info)
212 } 209 }
213 210
214 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1); 211 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1);
215 OUT_RING(chan, NvCtxSurf2D); 212 OUT_RING(chan, nfbdev->surf2d.handle);
216 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0184, 2); 213 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0184, 2);
217 OUT_RING(chan, NvDmaFB); 214 OUT_RING(chan, chan->vram.handle);
218 OUT_RING(chan, NvDmaFB); 215 OUT_RING(chan, chan->vram.handle);
219 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 4); 216 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 4);
220 OUT_RING(chan, surface_fmt); 217 OUT_RING(chan, surface_fmt);
221 OUT_RING(chan, info->fix.line_length | (info->fix.line_length << 16)); 218 OUT_RING(chan, info->fix.line_length | (info->fix.line_length << 16));
@@ -223,12 +220,12 @@ nv04_fbcon_accel_init(struct fb_info *info)
223 OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base); 220 OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base);
224 221
225 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1); 222 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1);
226 OUT_RING(chan, NvRop); 223 OUT_RING(chan, nfbdev->rop.handle);
227 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 1); 224 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 1);
228 OUT_RING(chan, 0x55); 225 OUT_RING(chan, 0x55);
229 226
230 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1); 227 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1);
231 OUT_RING(chan, NvImagePatt); 228 OUT_RING(chan, nfbdev->patt.handle);
232 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 8); 229 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 8);
233 OUT_RING(chan, pattern_fmt); 230 OUT_RING(chan, pattern_fmt);
234#ifdef __BIG_ENDIAN 231#ifdef __BIG_ENDIAN
@@ -244,18 +241,18 @@ nv04_fbcon_accel_init(struct fb_info *info)
244 OUT_RING(chan, ~0); 241 OUT_RING(chan, ~0);
245 242
246 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1); 243 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1);
247 OUT_RING(chan, NvClipRect); 244 OUT_RING(chan, nfbdev->clip.handle);
248 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 2); 245 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 2);
249 OUT_RING(chan, 0); 246 OUT_RING(chan, 0);
250 OUT_RING(chan, (info->var.yres_virtual << 16) | info->var.xres_virtual); 247 OUT_RING(chan, (info->var.yres_virtual << 16) | info->var.xres_virtual);
251 248
252 BEGIN_NV04(chan, NvSubImageBlit, 0x0000, 1); 249 BEGIN_NV04(chan, NvSubImageBlit, 0x0000, 1);
253 OUT_RING(chan, NvImageBlit); 250 OUT_RING(chan, nfbdev->blit.handle);
254 BEGIN_NV04(chan, NvSubImageBlit, 0x019c, 1); 251 BEGIN_NV04(chan, NvSubImageBlit, 0x019c, 1);
255 OUT_RING(chan, NvCtxSurf2D); 252 OUT_RING(chan, nfbdev->surf2d.handle);
256 BEGIN_NV04(chan, NvSubImageBlit, 0x02fc, 1); 253 BEGIN_NV04(chan, NvSubImageBlit, 0x02fc, 1);
257 OUT_RING(chan, 3); 254 OUT_RING(chan, 3);
258 if (device->chipset >= 0x11 /*XXX: oclass == 0x009f*/) { 255 if (device->info.chipset >= 0x11 /*XXX: oclass == 0x009f*/) {
259 BEGIN_NV04(chan, NvSubImageBlit, 0x0120, 3); 256 BEGIN_NV04(chan, NvSubImageBlit, 0x0120, 3);
260 OUT_RING(chan, 0); 257 OUT_RING(chan, 0);
261 OUT_RING(chan, 1); 258 OUT_RING(chan, 1);
@@ -263,12 +260,12 @@ nv04_fbcon_accel_init(struct fb_info *info)
263 } 260 }
264 261
265 BEGIN_NV04(chan, NvSubGdiRect, 0x0000, 1); 262 BEGIN_NV04(chan, NvSubGdiRect, 0x0000, 1);
266 OUT_RING(chan, NvGdiRect); 263 OUT_RING(chan, nfbdev->gdi.handle);
267 BEGIN_NV04(chan, NvSubGdiRect, 0x0198, 1); 264 BEGIN_NV04(chan, NvSubGdiRect, 0x0198, 1);
268 OUT_RING(chan, NvCtxSurf2D); 265 OUT_RING(chan, nfbdev->surf2d.handle);
269 BEGIN_NV04(chan, NvSubGdiRect, 0x0188, 2); 266 BEGIN_NV04(chan, NvSubGdiRect, 0x0188, 2);
270 OUT_RING(chan, NvImagePatt); 267 OUT_RING(chan, nfbdev->patt.handle);
271 OUT_RING(chan, NvRop); 268 OUT_RING(chan, nfbdev->rop.handle);
272 BEGIN_NV04(chan, NvSubGdiRect, 0x0304, 1); 269 BEGIN_NV04(chan, NvSubGdiRect, 0x0304, 1);
273 OUT_RING(chan, 1); 270 OUT_RING(chan, 1);
274 BEGIN_NV04(chan, NvSubGdiRect, 0x0300, 1); 271 BEGIN_NV04(chan, NvSubGdiRect, 0x0300, 1);