diff options
Diffstat (limited to 'drivers/gpu/drm/nouveau/nouveau_dma.c')
| -rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_dma.c | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.c b/drivers/gpu/drm/nouveau/nouveau_dma.c index c177272152e2..8508603cc8c3 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dma.c +++ b/drivers/gpu/drm/nouveau/nouveau_dma.c | |||
| @@ -24,8 +24,6 @@ | |||
| 24 | * | 24 | * |
| 25 | */ | 25 | */ |
| 26 | 26 | ||
| 27 | #include <core/client.h> | ||
| 28 | |||
| 29 | #include "nouveau_drm.h" | 27 | #include "nouveau_drm.h" |
| 30 | #include "nouveau_dma.h" | 28 | #include "nouveau_dma.h" |
| 31 | 29 | ||
| @@ -54,9 +52,9 @@ READ_GET(struct nouveau_channel *chan, uint64_t *prev_get, int *timeout) | |||
| 54 | { | 52 | { |
| 55 | uint64_t val; | 53 | uint64_t val; |
| 56 | 54 | ||
| 57 | val = nv_ro32(chan->object, chan->user_get); | 55 | val = nvif_rd32(chan, chan->user_get); |
| 58 | if (chan->user_get_hi) | 56 | if (chan->user_get_hi) |
| 59 | val |= (uint64_t)nv_ro32(chan->object, chan->user_get_hi) << 32; | 57 | val |= (uint64_t)nvif_rd32(chan, chan->user_get_hi) << 32; |
| 60 | 58 | ||
| 61 | /* reset counter as long as GET is still advancing, this is | 59 | /* reset counter as long as GET is still advancing, this is |
| 62 | * to avoid misdetecting a GPU lockup if the GPU happens to | 60 | * to avoid misdetecting a GPU lockup if the GPU happens to |
| @@ -84,12 +82,13 @@ void | |||
| 84 | nv50_dma_push(struct nouveau_channel *chan, struct nouveau_bo *bo, | 82 | nv50_dma_push(struct nouveau_channel *chan, struct nouveau_bo *bo, |
| 85 | int delta, int length) | 83 | int delta, int length) |
| 86 | { | 84 | { |
| 85 | struct nouveau_cli *cli = (void *)nvif_client(&chan->device->base); | ||
| 87 | struct nouveau_bo *pb = chan->push.buffer; | 86 | struct nouveau_bo *pb = chan->push.buffer; |
| 88 | struct nouveau_vma *vma; | 87 | struct nouveau_vma *vma; |
| 89 | int ip = (chan->dma.ib_put * 2) + chan->dma.ib_base; | 88 | int ip = (chan->dma.ib_put * 2) + chan->dma.ib_base; |
| 90 | u64 offset; | 89 | u64 offset; |
| 91 | 90 | ||
| 92 | vma = nouveau_bo_vma_find(bo, nv_client(chan->cli)->vm); | 91 | vma = nouveau_bo_vma_find(bo, cli->vm); |
| 93 | BUG_ON(!vma); | 92 | BUG_ON(!vma); |
| 94 | offset = vma->offset + delta; | 93 | offset = vma->offset + delta; |
| 95 | 94 | ||
| @@ -104,7 +103,7 @@ nv50_dma_push(struct nouveau_channel *chan, struct nouveau_bo *bo, | |||
| 104 | /* Flush writes. */ | 103 | /* Flush writes. */ |
| 105 | nouveau_bo_rd32(pb, 0); | 104 | nouveau_bo_rd32(pb, 0); |
| 106 | 105 | ||
| 107 | nv_wo32(chan->object, 0x8c, chan->dma.ib_put); | 106 | nvif_wr32(chan, 0x8c, chan->dma.ib_put); |
| 108 | chan->dma.ib_free--; | 107 | chan->dma.ib_free--; |
| 109 | } | 108 | } |
| 110 | 109 | ||
| @@ -114,7 +113,7 @@ nv50_dma_push_wait(struct nouveau_channel *chan, int count) | |||
| 114 | uint32_t cnt = 0, prev_get = 0; | 113 | uint32_t cnt = 0, prev_get = 0; |
| 115 | 114 | ||
| 116 | while (chan->dma.ib_free < count) { | 115 | while (chan->dma.ib_free < count) { |
| 117 | uint32_t get = nv_ro32(chan->object, 0x88); | 116 | uint32_t get = nvif_rd32(chan, 0x88); |
| 118 | if (get != prev_get) { | 117 | if (get != prev_get) { |
| 119 | prev_get = get; | 118 | prev_get = get; |
| 120 | cnt = 0; | 119 | cnt = 0; |
