diff options
Diffstat (limited to 'drivers/gpu/drm/nouveau/dispnv04/dac.c')
| -rw-r--r-- | drivers/gpu/drm/nouveau/dispnv04/dac.c | 54 |
1 files changed, 27 insertions, 27 deletions
diff --git a/drivers/gpu/drm/nouveau/dispnv04/dac.c b/drivers/gpu/drm/nouveau/dispnv04/dac.c index a96dda48718e..2d8056cde996 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/dac.c +++ b/drivers/gpu/drm/nouveau/dispnv04/dac.c | |||
| @@ -65,8 +65,8 @@ int nv04_dac_output_offset(struct drm_encoder *encoder) | |||
| 65 | 65 | ||
| 66 | static int sample_load_twice(struct drm_device *dev, bool sense[2]) | 66 | static int sample_load_twice(struct drm_device *dev, bool sense[2]) |
| 67 | { | 67 | { |
| 68 | struct nouveau_device *device = nouveau_dev(dev); | 68 | struct nvif_device *device = &nouveau_drm(dev)->device; |
| 69 | struct nouveau_timer *ptimer = nouveau_timer(device); | 69 | struct nouveau_timer *ptimer = nvkm_timer(device); |
| 70 | int i; | 70 | int i; |
| 71 | 71 | ||
| 72 | for (i = 0; i < 2; i++) { | 72 | for (i = 0; i < 2; i++) { |
| @@ -95,15 +95,15 @@ static int sample_load_twice(struct drm_device *dev, bool sense[2]) | |||
| 95 | 95 | ||
| 96 | udelay(100); | 96 | udelay(100); |
| 97 | /* when level triggers, sense is _LO_ */ | 97 | /* when level triggers, sense is _LO_ */ |
| 98 | sense_a = nv_rd08(device, NV_PRMCIO_INP0) & 0x10; | 98 | sense_a = nvif_rd08(device, NV_PRMCIO_INP0) & 0x10; |
| 99 | 99 | ||
| 100 | /* take another reading until it agrees with sense_a... */ | 100 | /* take another reading until it agrees with sense_a... */ |
| 101 | do { | 101 | do { |
| 102 | udelay(100); | 102 | udelay(100); |
| 103 | sense_b = nv_rd08(device, NV_PRMCIO_INP0) & 0x10; | 103 | sense_b = nvif_rd08(device, NV_PRMCIO_INP0) & 0x10; |
| 104 | if (sense_a != sense_b) { | 104 | if (sense_a != sense_b) { |
| 105 | sense_b_prime = | 105 | sense_b_prime = |
| 106 | nv_rd08(device, NV_PRMCIO_INP0) & 0x10; | 106 | nvif_rd08(device, NV_PRMCIO_INP0) & 0x10; |
| 107 | if (sense_b == sense_b_prime) { | 107 | if (sense_b == sense_b_prime) { |
| 108 | /* ... unless two consecutive subsequent | 108 | /* ... unless two consecutive subsequent |
| 109 | * samples agree; sense_a is replaced */ | 109 | * samples agree; sense_a is replaced */ |
| @@ -128,7 +128,7 @@ static enum drm_connector_status nv04_dac_detect(struct drm_encoder *encoder, | |||
| 128 | struct drm_connector *connector) | 128 | struct drm_connector *connector) |
| 129 | { | 129 | { |
| 130 | struct drm_device *dev = encoder->dev; | 130 | struct drm_device *dev = encoder->dev; |
| 131 | struct nouveau_device *device = nouveau_dev(dev); | 131 | struct nvif_device *device = &nouveau_drm(dev)->device; |
| 132 | struct nouveau_drm *drm = nouveau_drm(dev); | 132 | struct nouveau_drm *drm = nouveau_drm(dev); |
| 133 | uint8_t saved_seq1, saved_pi, saved_rpc1, saved_cr_mode; | 133 | uint8_t saved_seq1, saved_pi, saved_rpc1, saved_cr_mode; |
| 134 | uint8_t saved_palette0[3], saved_palette_mask; | 134 | uint8_t saved_palette0[3], saved_palette_mask; |
| @@ -164,11 +164,11 @@ static enum drm_connector_status nv04_dac_detect(struct drm_encoder *encoder, | |||
| 164 | saved_rpc1 = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX); | 164 | saved_rpc1 = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX); |
| 165 | NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX, saved_rpc1 & ~0xc0); | 165 | NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX, saved_rpc1 & ~0xc0); |
| 166 | 166 | ||
| 167 | nv_wr08(device, NV_PRMDIO_READ_MODE_ADDRESS, 0x0); | 167 | nvif_wr08(device, NV_PRMDIO_READ_MODE_ADDRESS, 0x0); |
| 168 | for (i = 0; i < 3; i++) | 168 | for (i = 0; i < 3; i++) |
| 169 | saved_palette0[i] = nv_rd08(device, NV_PRMDIO_PALETTE_DATA); | 169 | saved_palette0[i] = nvif_rd08(device, NV_PRMDIO_PALETTE_DATA); |
| 170 | saved_palette_mask = nv_rd08(device, NV_PRMDIO_PIXEL_MASK); | 170 | saved_palette_mask = nvif_rd08(device, NV_PRMDIO_PIXEL_MASK); |
| 171 | nv_wr08(device, NV_PRMDIO_PIXEL_MASK, 0); | 171 | nvif_wr08(device, NV_PRMDIO_PIXEL_MASK, 0); |
| 172 | 172 | ||
| 173 | saved_rgen_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_GENERAL_CONTROL); | 173 | saved_rgen_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_GENERAL_CONTROL); |
| 174 | NVWriteRAMDAC(dev, 0, NV_PRAMDAC_GENERAL_CONTROL, | 174 | NVWriteRAMDAC(dev, 0, NV_PRAMDAC_GENERAL_CONTROL, |
| @@ -181,11 +181,11 @@ static enum drm_connector_status nv04_dac_detect(struct drm_encoder *encoder, | |||
| 181 | do { | 181 | do { |
| 182 | bool sense_pair[2]; | 182 | bool sense_pair[2]; |
| 183 | 183 | ||
| 184 | nv_wr08(device, NV_PRMDIO_WRITE_MODE_ADDRESS, 0); | 184 | nvif_wr08(device, NV_PRMDIO_WRITE_MODE_ADDRESS, 0); |
| 185 | nv_wr08(device, NV_PRMDIO_PALETTE_DATA, 0); | 185 | nvif_wr08(device, NV_PRMDIO_PALETTE_DATA, 0); |
| 186 | nv_wr08(device, NV_PRMDIO_PALETTE_DATA, 0); | 186 | nvif_wr08(device, NV_PRMDIO_PALETTE_DATA, 0); |
| 187 | /* testing blue won't find monochrome monitors. I don't care */ | 187 | /* testing blue won't find monochrome monitors. I don't care */ |
| 188 | nv_wr08(device, NV_PRMDIO_PALETTE_DATA, blue); | 188 | nvif_wr08(device, NV_PRMDIO_PALETTE_DATA, blue); |
| 189 | 189 | ||
| 190 | i = 0; | 190 | i = 0; |
| 191 | /* take sample pairs until both samples in the pair agree */ | 191 | /* take sample pairs until both samples in the pair agree */ |
| @@ -208,11 +208,11 @@ static enum drm_connector_status nv04_dac_detect(struct drm_encoder *encoder, | |||
| 208 | } while (++blue < 0x18 && sense); | 208 | } while (++blue < 0x18 && sense); |
| 209 | 209 | ||
| 210 | out: | 210 | out: |
| 211 | nv_wr08(device, NV_PRMDIO_PIXEL_MASK, saved_palette_mask); | 211 | nvif_wr08(device, NV_PRMDIO_PIXEL_MASK, saved_palette_mask); |
| 212 | NVWriteRAMDAC(dev, 0, NV_PRAMDAC_GENERAL_CONTROL, saved_rgen_ctrl); | 212 | NVWriteRAMDAC(dev, 0, NV_PRAMDAC_GENERAL_CONTROL, saved_rgen_ctrl); |
| 213 | nv_wr08(device, NV_PRMDIO_WRITE_MODE_ADDRESS, 0); | 213 | nvif_wr08(device, NV_PRMDIO_WRITE_MODE_ADDRESS, 0); |
| 214 | for (i = 0; i < 3; i++) | 214 | for (i = 0; i < 3; i++) |
| 215 | nv_wr08(device, NV_PRMDIO_PALETTE_DATA, saved_palette0[i]); | 215 | nvif_wr08(device, NV_PRMDIO_PALETTE_DATA, saved_palette0[i]); |
| 216 | NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL, saved_rtest_ctrl); | 216 | NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL, saved_rtest_ctrl); |
| 217 | NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_PIXEL_INDEX, saved_pi); | 217 | NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_PIXEL_INDEX, saved_pi); |
| 218 | NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX, saved_rpc1); | 218 | NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX, saved_rpc1); |
| @@ -231,8 +231,8 @@ uint32_t nv17_dac_sample_load(struct drm_encoder *encoder) | |||
| 231 | { | 231 | { |
| 232 | struct drm_device *dev = encoder->dev; | 232 | struct drm_device *dev = encoder->dev; |
| 233 | struct nouveau_drm *drm = nouveau_drm(dev); | 233 | struct nouveau_drm *drm = nouveau_drm(dev); |
| 234 | struct nouveau_device *device = nouveau_dev(dev); | 234 | struct nvif_device *device = &nouveau_drm(dev)->device; |
| 235 | struct nouveau_gpio *gpio = nouveau_gpio(device); | 235 | struct nouveau_gpio *gpio = nvkm_gpio(device); |
| 236 | struct dcb_output *dcb = nouveau_encoder(encoder)->dcb; | 236 | struct dcb_output *dcb = nouveau_encoder(encoder)->dcb; |
| 237 | uint32_t sample, testval, regoffset = nv04_dac_output_offset(encoder); | 237 | uint32_t sample, testval, regoffset = nv04_dac_output_offset(encoder); |
| 238 | uint32_t saved_powerctrl_2 = 0, saved_powerctrl_4 = 0, saved_routput, | 238 | uint32_t saved_powerctrl_2 = 0, saved_powerctrl_4 = 0, saved_routput, |
| @@ -256,12 +256,12 @@ uint32_t nv17_dac_sample_load(struct drm_encoder *encoder) | |||
| 256 | NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, | 256 | NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, |
| 257 | saved_rtest_ctrl & ~NV_PRAMDAC_TEST_CONTROL_PWRDWN_DAC_OFF); | 257 | saved_rtest_ctrl & ~NV_PRAMDAC_TEST_CONTROL_PWRDWN_DAC_OFF); |
| 258 | 258 | ||
| 259 | saved_powerctrl_2 = nv_rd32(device, NV_PBUS_POWERCTRL_2); | 259 | saved_powerctrl_2 = nvif_rd32(device, NV_PBUS_POWERCTRL_2); |
| 260 | 260 | ||
| 261 | nv_wr32(device, NV_PBUS_POWERCTRL_2, saved_powerctrl_2 & 0xd7ffffff); | 261 | nvif_wr32(device, NV_PBUS_POWERCTRL_2, saved_powerctrl_2 & 0xd7ffffff); |
| 262 | if (regoffset == 0x68) { | 262 | if (regoffset == 0x68) { |
| 263 | saved_powerctrl_4 = nv_rd32(device, NV_PBUS_POWERCTRL_4); | 263 | saved_powerctrl_4 = nvif_rd32(device, NV_PBUS_POWERCTRL_4); |
| 264 | nv_wr32(device, NV_PBUS_POWERCTRL_4, saved_powerctrl_4 & 0xffffffcf); | 264 | nvif_wr32(device, NV_PBUS_POWERCTRL_4, saved_powerctrl_4 & 0xffffffcf); |
| 265 | } | 265 | } |
| 266 | 266 | ||
| 267 | if (gpio) { | 267 | if (gpio) { |
| @@ -283,7 +283,7 @@ uint32_t nv17_dac_sample_load(struct drm_encoder *encoder) | |||
| 283 | /* nv driver and nv31 use 0xfffffeee, nv34 and 6600 use 0xfffffece */ | 283 | /* nv driver and nv31 use 0xfffffeee, nv34 and 6600 use 0xfffffece */ |
| 284 | routput = (saved_routput & 0xfffffece) | head << 8; | 284 | routput = (saved_routput & 0xfffffece) | head << 8; |
| 285 | 285 | ||
| 286 | if (nv_device(drm->device)->card_type >= NV_40) { | 286 | if (drm->device.info.family >= NV_DEVICE_INFO_V0_CURIE) { |
| 287 | if (dcb->type == DCB_OUTPUT_TV) | 287 | if (dcb->type == DCB_OUTPUT_TV) |
| 288 | routput |= 0x1a << 16; | 288 | routput |= 0x1a << 16; |
| 289 | else | 289 | else |
| @@ -316,8 +316,8 @@ uint32_t nv17_dac_sample_load(struct drm_encoder *encoder) | |||
| 316 | NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, saved_routput); | 316 | NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, saved_routput); |
| 317 | NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, saved_rtest_ctrl); | 317 | NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, saved_rtest_ctrl); |
| 318 | if (regoffset == 0x68) | 318 | if (regoffset == 0x68) |
| 319 | nv_wr32(device, NV_PBUS_POWERCTRL_4, saved_powerctrl_4); | 319 | nvif_wr32(device, NV_PBUS_POWERCTRL_4, saved_powerctrl_4); |
| 320 | nv_wr32(device, NV_PBUS_POWERCTRL_2, saved_powerctrl_2); | 320 | nvif_wr32(device, NV_PBUS_POWERCTRL_2, saved_powerctrl_2); |
| 321 | 321 | ||
| 322 | if (gpio) { | 322 | if (gpio) { |
| 323 | gpio->set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, saved_gpio1); | 323 | gpio->set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, saved_gpio1); |
| @@ -398,7 +398,7 @@ static void nv04_dac_mode_set(struct drm_encoder *encoder, | |||
| 398 | } | 398 | } |
| 399 | 399 | ||
| 400 | /* This could use refinement for flatpanels, but it should work this way */ | 400 | /* This could use refinement for flatpanels, but it should work this way */ |
| 401 | if (nv_device(drm->device)->chipset < 0x44) | 401 | if (drm->device.info.chipset < 0x44) |
| 402 | NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0xf0000000); | 402 | NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0xf0000000); |
| 403 | else | 403 | else |
| 404 | NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0x00100000); | 404 | NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0x00100000); |
