aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c')
-rw-r--r--drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c24
1 files changed, 14 insertions, 10 deletions
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c
index 1188f4bf1e60..de97c08f3f1f 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c
@@ -36,7 +36,7 @@ static struct mdp5_kms *get_kms(struct drm_encoder *encoder)
36 return to_mdp5_kms(to_mdp_kms(priv->kms)); 36 return to_mdp5_kms(to_mdp_kms(priv->kms));
37} 37}
38 38
39#ifdef CONFIG_MSM_BUS_SCALING 39#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
40#include <mach/board.h> 40#include <mach/board.h>
41#include <mach/msm_bus.h> 41#include <mach/msm_bus.h>
42#include <mach/msm_bus_board.h> 42#include <mach/msm_bus_board.h>
@@ -144,10 +144,14 @@ static void mdp5_encoder_mode_set(struct drm_encoder *encoder,
144 mode->type, mode->flags); 144 mode->type, mode->flags);
145 145
146 ctrl_pol = 0; 146 ctrl_pol = 0;
147 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 147
148 ctrl_pol |= MDP5_INTF_POLARITY_CTL_HSYNC_LOW; 148 /* DSI controller cannot handle active-low sync signals. */
149 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 149 if (mdp5_encoder->intf.type != INTF_DSI) {
150 ctrl_pol |= MDP5_INTF_POLARITY_CTL_VSYNC_LOW; 150 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
151 ctrl_pol |= MDP5_INTF_POLARITY_CTL_HSYNC_LOW;
152 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
153 ctrl_pol |= MDP5_INTF_POLARITY_CTL_VSYNC_LOW;
154 }
151 /* probably need to get DATA_EN polarity from panel.. */ 155 /* probably need to get DATA_EN polarity from panel.. */
152 156
153 dtv_hsync_skew = 0; /* get this from panel? */ 157 dtv_hsync_skew = 0; /* get this from panel? */
@@ -304,9 +308,9 @@ int mdp5_encoder_set_split_display(struct drm_encoder *encoder,
304 * to use the master's enable signal for the slave encoder. 308 * to use the master's enable signal for the slave encoder.
305 */ 309 */
306 if (intf_num == 1) 310 if (intf_num == 1)
307 data |= MDP5_SPLIT_DPL_LOWER_INTF2_TG_SYNC; 311 data |= MDP5_MDP_SPLIT_DPL_LOWER_INTF2_TG_SYNC;
308 else if (intf_num == 2) 312 else if (intf_num == 2)
309 data |= MDP5_SPLIT_DPL_LOWER_INTF1_TG_SYNC; 313 data |= MDP5_MDP_SPLIT_DPL_LOWER_INTF1_TG_SYNC;
310 else 314 else
311 return -EINVAL; 315 return -EINVAL;
312 316
@@ -315,9 +319,9 @@ int mdp5_encoder_set_split_display(struct drm_encoder *encoder,
315 mdp5_write(mdp5_kms, REG_MDP5_MDP_SPARE_0(0), 319 mdp5_write(mdp5_kms, REG_MDP5_MDP_SPARE_0(0),
316 MDP5_MDP_SPARE_0_SPLIT_DPL_SINGLE_FLUSH_EN); 320 MDP5_MDP_SPARE_0_SPLIT_DPL_SINGLE_FLUSH_EN);
317 /* Dumb Panel, Sync mode */ 321 /* Dumb Panel, Sync mode */
318 mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_UPPER, 0); 322 mdp5_write(mdp5_kms, REG_MDP5_MDP_SPLIT_DPL_UPPER(0), 0);
319 mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_LOWER, data); 323 mdp5_write(mdp5_kms, REG_MDP5_MDP_SPLIT_DPL_LOWER(0), data);
320 mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_EN, 1); 324 mdp5_write(mdp5_kms, REG_MDP5_MDP_SPLIT_DPL_EN(0), 1);
321 mdp5_disable(mdp5_kms); 325 mdp5_disable(mdp5_kms);
322 326
323 return 0; 327 return 0;