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path: root/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
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Diffstat (limited to 'drivers/gpu/drm/mediatek/mtk_drm_crtc.c')
-rw-r--r--drivers/gpu/drm/mediatek/mtk_drm_crtc.c21
1 files changed, 10 insertions, 11 deletions
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index 58725d34d411..01a21dd835b5 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -31,7 +31,7 @@
31 * struct mtk_drm_crtc - MediaTek specific crtc structure. 31 * struct mtk_drm_crtc - MediaTek specific crtc structure.
32 * @base: crtc object. 32 * @base: crtc object.
33 * @enabled: records whether crtc_enable succeeded 33 * @enabled: records whether crtc_enable succeeded
34 * @planes: array of 4 mtk_drm_plane structures, one for each overlay plane 34 * @planes: array of 4 drm_plane structures, one for each overlay plane
35 * @pending_planes: whether any plane has pending changes to be applied 35 * @pending_planes: whether any plane has pending changes to be applied
36 * @config_regs: memory mapped mmsys configuration register space 36 * @config_regs: memory mapped mmsys configuration register space
37 * @mutex: handle to one of the ten disp_mutex streams 37 * @mutex: handle to one of the ten disp_mutex streams
@@ -45,7 +45,7 @@ struct mtk_drm_crtc {
45 bool pending_needs_vblank; 45 bool pending_needs_vblank;
46 struct drm_pending_vblank_event *event; 46 struct drm_pending_vblank_event *event;
47 47
48 struct mtk_drm_plane planes[OVL_LAYER_NR]; 48 struct drm_plane planes[OVL_LAYER_NR];
49 bool pending_planes; 49 bool pending_planes;
50 50
51 void __iomem *config_regs; 51 void __iomem *config_regs;
@@ -112,8 +112,7 @@ static void mtk_drm_crtc_reset(struct drm_crtc *crtc)
112 struct mtk_crtc_state *state; 112 struct mtk_crtc_state *state;
113 113
114 if (crtc->state) { 114 if (crtc->state) {
115 if (crtc->state->mode_blob) 115 __drm_atomic_helper_crtc_destroy_state(crtc->state);
116 drm_property_unreference_blob(crtc->state->mode_blob);
117 116
118 state = to_mtk_crtc_state(crtc->state); 117 state = to_mtk_crtc_state(crtc->state);
119 memset(state, 0, sizeof(*state)); 118 memset(state, 0, sizeof(*state));
@@ -287,7 +286,7 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
287 286
288 /* Initially configure all planes */ 287 /* Initially configure all planes */
289 for (i = 0; i < OVL_LAYER_NR; i++) { 288 for (i = 0; i < OVL_LAYER_NR; i++) {
290 struct drm_plane *plane = &mtk_crtc->planes[i].base; 289 struct drm_plane *plane = &mtk_crtc->planes[i];
291 struct mtk_plane_state *plane_state; 290 struct mtk_plane_state *plane_state;
292 291
293 plane_state = to_mtk_plane_state(plane->state); 292 plane_state = to_mtk_plane_state(plane->state);
@@ -366,7 +365,7 @@ static void mtk_drm_crtc_disable(struct drm_crtc *crtc)
366 365
367 /* Set all pending plane state to disabled */ 366 /* Set all pending plane state to disabled */
368 for (i = 0; i < OVL_LAYER_NR; i++) { 367 for (i = 0; i < OVL_LAYER_NR; i++) {
369 struct drm_plane *plane = &mtk_crtc->planes[i].base; 368 struct drm_plane *plane = &mtk_crtc->planes[i];
370 struct mtk_plane_state *plane_state; 369 struct mtk_plane_state *plane_state;
371 370
372 plane_state = to_mtk_plane_state(plane->state); 371 plane_state = to_mtk_plane_state(plane->state);
@@ -412,7 +411,7 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
412 if (mtk_crtc->event) 411 if (mtk_crtc->event)
413 mtk_crtc->pending_needs_vblank = true; 412 mtk_crtc->pending_needs_vblank = true;
414 for (i = 0; i < OVL_LAYER_NR; i++) { 413 for (i = 0; i < OVL_LAYER_NR; i++) {
415 struct drm_plane *plane = &mtk_crtc->planes[i].base; 414 struct drm_plane *plane = &mtk_crtc->planes[i];
416 struct mtk_plane_state *plane_state; 415 struct mtk_plane_state *plane_state;
417 416
418 plane_state = to_mtk_plane_state(plane->state); 417 plane_state = to_mtk_plane_state(plane->state);
@@ -490,7 +489,7 @@ void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *ovl)
490 489
491 if (mtk_crtc->pending_planes) { 490 if (mtk_crtc->pending_planes) {
492 for (i = 0; i < OVL_LAYER_NR; i++) { 491 for (i = 0; i < OVL_LAYER_NR; i++) {
493 struct drm_plane *plane = &mtk_crtc->planes[i].base; 492 struct drm_plane *plane = &mtk_crtc->planes[i];
494 struct mtk_plane_state *plane_state; 493 struct mtk_plane_state *plane_state;
495 494
496 plane_state = to_mtk_plane_state(plane->state); 495 plane_state = to_mtk_plane_state(plane->state);
@@ -578,13 +577,13 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
578 (zpos == 1) ? DRM_PLANE_TYPE_CURSOR : 577 (zpos == 1) ? DRM_PLANE_TYPE_CURSOR :
579 DRM_PLANE_TYPE_OVERLAY; 578 DRM_PLANE_TYPE_OVERLAY;
580 ret = mtk_plane_init(drm_dev, &mtk_crtc->planes[zpos], 579 ret = mtk_plane_init(drm_dev, &mtk_crtc->planes[zpos],
581 BIT(pipe), type, zpos); 580 BIT(pipe), type);
582 if (ret) 581 if (ret)
583 goto unprepare; 582 goto unprepare;
584 } 583 }
585 584
586 ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, &mtk_crtc->planes[0].base, 585 ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, &mtk_crtc->planes[0],
587 &mtk_crtc->planes[1].base, pipe); 586 &mtk_crtc->planes[1], pipe);
588 if (ret < 0) 587 if (ret < 0)
589 goto unprepare; 588 goto unprepare;
590 drm_mode_crtc_set_gamma_size(&mtk_crtc->base, MTK_LUT_SIZE); 589 drm_mode_crtc_set_gamma_size(&mtk_crtc->base, MTK_LUT_SIZE);