1 files changed, 92 insertions, 0 deletions

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 585943c81e1f..b0a5cffe345a 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -31,14 +31,31 @@
 #define RDMA_REG_UPDATE_INT                             BIT(0)
 #define DISP_REG_RDMA_GLOBAL_CON                0x0010
 #define RDMA_ENGINE_EN                                  BIT(0)
+#define RDMA_MODE_MEMORY                                BIT(1)
 #define DISP_REG_RDMA_SIZE_CON_0                0x0014
+#define RDMA_MATRIX_ENABLE                              BIT(17)
+#define RDMA_MATRIX_INT_MTX_SEL                         GENMASK(23, 20)
+#define RDMA_MATRIX_INT_MTX_BT601_to_RGB                (6 << 20)
 #define DISP_REG_RDMA_SIZE_CON_1                0x0018
 #define DISP_REG_RDMA_TARGET_LINE               0x001c
+#define DISP_RDMA_MEM_CON                       0x0024
+#define MEM_MODE_INPUT_FORMAT_RGB565                    (0x000 << 4)
+#define MEM_MODE_INPUT_FORMAT_RGB888                    (0x001 << 4)
+#define MEM_MODE_INPUT_FORMAT_RGBA8888                  (0x002 << 4)
+#define MEM_MODE_INPUT_FORMAT_ARGB8888                  (0x003 << 4)
+#define MEM_MODE_INPUT_FORMAT_UYVY                      (0x004 << 4)
+#define MEM_MODE_INPUT_FORMAT_YUYV                      (0x005 << 4)
+#define MEM_MODE_INPUT_SWAP                             BIT(8)
+#define DISP_RDMA_MEM_SRC_PITCH                 0x002c
+#define DISP_RDMA_MEM_GMC_SETTING_0             0x0030
 #define DISP_REG_RDMA_FIFO_CON                  0x0040
 #define RDMA_FIFO_UNDERFLOW_EN                          BIT(31)
 #define RDMA_FIFO_PSEUDO_SIZE(bytes)                    (((bytes) / 16) << 16)
 #define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes)         ((bytes) / 16)
 #define RDMA_FIFO_SIZE(rdma)                    ((rdma)->data->fifo_size)
+#define DISP_RDMA_MEM_START_ADDR                0x0f00
+
+#define RDMA_MEM_GMC                            0x40402020
 
 struct mtk_disp_rdma_data {
         unsigned int fifo_size;
@@ -138,12 +155,87 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
         writel(reg, comp->regs + DISP_REG_RDMA_FIFO_CON);
 }
 
+static unsigned int rdma_fmt_convert(struct mtk_disp_rdma *rdma,
+                                     unsigned int fmt)
+{
+        /* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX"
+         * is defined in mediatek HW data sheet.
+         * The alphabet order in XXX is no relation to data
+         * arrangement in memory.
+         */
+        switch (fmt) {
+        default:
+        case DRM_FORMAT_RGB565:
+                return MEM_MODE_INPUT_FORMAT_RGB565;
+        case DRM_FORMAT_BGR565:
+                return MEM_MODE_INPUT_FORMAT_RGB565 | MEM_MODE_INPUT_SWAP;
+        case DRM_FORMAT_RGB888:
+                return MEM_MODE_INPUT_FORMAT_RGB888;
+        case DRM_FORMAT_BGR888:
+                return MEM_MODE_INPUT_FORMAT_RGB888 | MEM_MODE_INPUT_SWAP;
+        case DRM_FORMAT_RGBX8888:
+        case DRM_FORMAT_RGBA8888:
+                return MEM_MODE_INPUT_FORMAT_ARGB8888;
+        case DRM_FORMAT_BGRX8888:
+        case DRM_FORMAT_BGRA8888:
+                return MEM_MODE_INPUT_FORMAT_ARGB8888 | MEM_MODE_INPUT_SWAP;
+        case DRM_FORMAT_XRGB8888:
+        case DRM_FORMAT_ARGB8888:
+                return MEM_MODE_INPUT_FORMAT_RGBA8888;
+        case DRM_FORMAT_XBGR8888:
+        case DRM_FORMAT_ABGR8888:
+                return MEM_MODE_INPUT_FORMAT_RGBA8888 | MEM_MODE_INPUT_SWAP;
+        case DRM_FORMAT_UYVY:
+                return MEM_MODE_INPUT_FORMAT_UYVY;
+        case DRM_FORMAT_YUYV:
+                return MEM_MODE_INPUT_FORMAT_YUYV;
+        }
+}
+
+static unsigned int mtk_rdma_layer_nr(struct mtk_ddp_comp *comp)
+{
+        return 1;
+}
+
+static void mtk_rdma_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
+                                  struct mtk_plane_state *state)
+{
+        struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
+        struct mtk_plane_pending_state *pending = &state->pending;
+        unsigned int addr = pending->addr;
+        unsigned int pitch = pending->pitch & 0xffff;
+        unsigned int fmt = pending->format;
+        unsigned int con;
+
+        con = rdma_fmt_convert(rdma, fmt);
+        writel_relaxed(con, comp->regs + DISP_RDMA_MEM_CON);
+
+        if (fmt == DRM_FORMAT_UYVY || fmt == DRM_FORMAT_YUYV) {
+                rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0,
+                                 RDMA_MATRIX_ENABLE, RDMA_MATRIX_ENABLE);
+                rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0,
+                                 RDMA_MATRIX_INT_MTX_SEL,
+                                 RDMA_MATRIX_INT_MTX_BT601_to_RGB);
+        } else {
+                rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0,
+                                 RDMA_MATRIX_ENABLE, 0);
+        }
+
+        writel_relaxed(addr, comp->regs + DISP_RDMA_MEM_START_ADDR);
+        writel_relaxed(pitch, comp->regs + DISP_RDMA_MEM_SRC_PITCH);
+        writel(RDMA_MEM_GMC, comp->regs + DISP_RDMA_MEM_GMC_SETTING_0);
+        rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON,
+                         RDMA_MODE_MEMORY, RDMA_MODE_MEMORY);
+}
+
 static const struct mtk_ddp_comp_funcs mtk_disp_rdma_funcs = {
         .config = mtk_rdma_config,
         .start = mtk_rdma_start,
         .stop = mtk_rdma_stop,
         .enable_vblank = mtk_rdma_enable_vblank,
         .disable_vblank = mtk_rdma_disable_vblank,
+        .layer_nr = mtk_rdma_layer_nr,
+        .layer_config = mtk_rdma_layer_config,
 };
 
 static int mtk_disp_rdma_bind(struct device *dev, struct device *master,