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-rw-r--r--drivers/gpu/drm/i915/intel_lrc.c7
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index dab73e7d9a6b..a88380876ce9 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -530,13 +530,18 @@ static void intel_lrc_irq_handler(unsigned long data)
530 530
531 intel_uncore_forcewake_get(dev_priv, engine->fw_domains); 531 intel_uncore_forcewake_get(dev_priv, engine->fw_domains);
532 532
533 while (test_and_clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted)) { 533 /* Prefer doing test_and_clear_bit() as a two stage operation to avoid
534 * imposing the cost of a locked atomic transaction when submitting a
535 * new request (outside of the context-switch interrupt).
536 */
537 while (test_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted)) {
534 u32 __iomem *csb_mmio = 538 u32 __iomem *csb_mmio =
535 dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)); 539 dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine));
536 u32 __iomem *buf = 540 u32 __iomem *buf =
537 dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)); 541 dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0));
538 unsigned int csb, head, tail; 542 unsigned int csb, head, tail;
539 543
544 clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
540 csb = readl(csb_mmio); 545 csb = readl(csb_mmio);
541 head = GEN8_CSB_READ_PTR(csb); 546 head = GEN8_CSB_READ_PTR(csb);
542 tail = GEN8_CSB_WRITE_PTR(csb); 547 tail = GEN8_CSB_WRITE_PTR(csb);