1 files changed, 22 insertions, 10 deletions

diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index c3998188cf35..1a840bf92eea 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -51,7 +51,9 @@ static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn,
 
         WARN_ON(!mutex_is_locked(&dev_priv->sb_lock));
 
-        if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, 5)) {
+        if (intel_wait_for_register(dev_priv,
+                                    VLV_IOSF_DOORBELL_REQ, IOSF_SB_BUSY, 0,
+                                    5)) {
                 DRM_DEBUG_DRIVER("IOSF sideband idle wait (%s) timed out\n",
                                  is_read ? "read" : "write");
                 return -EAGAIN;
@@ -62,7 +64,9 @@ static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn,
                 I915_WRITE(VLV_IOSF_DATA, *val);
         I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd);
 
-        if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, 5)) {
+        if (intel_wait_for_register(dev_priv,
+                                    VLV_IOSF_DOORBELL_REQ, IOSF_SB_BUSY, 0,
+                                    5)) {
                 DRM_DEBUG_DRIVER("IOSF sideband finish wait (%s) timed out\n",
                                  is_read ? "read" : "write");
                 return -ETIMEDOUT;
@@ -202,8 +206,9 @@ u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
         u32 value = 0;
         WARN_ON(!mutex_is_locked(&dev_priv->sb_lock));
 
-        if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
-                                100)) {
+        if (intel_wait_for_register(dev_priv,
+                                    SBI_CTL_STAT, SBI_BUSY, 0,
+                                    100)) {
                 DRM_ERROR("timeout waiting for SBI to become ready\n");
                 return 0;
         }
@@ -216,8 +221,11 @@ u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
                 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
         I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
 
-        if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
-                                100)) {
+        if (intel_wait_for_register(dev_priv,
+                                    SBI_CTL_STAT,
+                                    SBI_BUSY | SBI_RESPONSE_FAIL,
+                                    0,
+                                    100)) {
                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
                 return 0;
         }
@@ -232,8 +240,9 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
 
         WARN_ON(!mutex_is_locked(&dev_priv->sb_lock));
 
-        if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
-                                100)) {
+        if (intel_wait_for_register(dev_priv,
+                                    SBI_CTL_STAT, SBI_BUSY, 0,
+                                    100)) {
                 DRM_ERROR("timeout waiting for SBI to become ready\n");
                 return;
         }
@@ -247,8 +256,11 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
                 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
         I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
 
-        if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
-                                100)) {
+        if (intel_wait_for_register(dev_priv,
+                                    SBI_CTL_STAT,
+                                    SBI_BUSY | SBI_RESPONSE_FAIL,
+                                    0,
+                                    100)) {
                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
                 return;
         }