1 files changed, 48 insertions, 28 deletions
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index e856d49d6dc3..6b78295f53db 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -287,7 +287,7 @@ void intel_display_set_init_power(struct drm_i915_private *dev_priv,
 */
 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
 {
-        struct drm_device *dev = dev_priv->dev;
+        struct drm_device *dev = &dev_priv->drm;
        /*
         * After we re-enable the power well, if we touch VGA register 0x3d5
@@ -318,7 +318,7 @@ static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv)
 static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
                                       struct i915_power_well *power_well)
 {
-        struct drm_device *dev = dev_priv->dev;
+        struct drm_device *dev = &dev_priv->drm;
        /*
         * After we re-enable the power well, if we touch VGA register 0x3d5
@@ -365,8 +365,11 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
                if (!is_enabled) {
                        DRM_DEBUG_KMS("Enabling power well\n");
-                        if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
+                        if (intel_wait_for_register(dev_priv,
-                                      HSW_PWR_WELL_STATE_ENABLED), 20))
+                                                    HSW_PWR_WELL_DRIVER,
+                                                    HSW_PWR_WELL_STATE_ENABLED,
+                                                    HSW_PWR_WELL_STATE_ENABLED,
+                                                    20))
                                DRM_ERROR("Timeout enabling power well\n");
                        hsw_power_well_post_enable(dev_priv);
                }
@@ -578,6 +581,7 @@ void bxt_enable_dc9(struct drm_i915_private *dev_priv)
        DRM_DEBUG_KMS("Enabling DC9\n");
+        intel_power_sequencer_reset(dev_priv);
        gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
 }
@@ -699,8 +703,11 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
        switch (power_well->data) {
        case SKL_DISP_PW_1:
-                if (wait_for((I915_READ(SKL_FUSE_STATUS) &
+                if (intel_wait_for_register(dev_priv,
-                        SKL_FUSE_PG0_DIST_STATUS), 1)) {
+                                            SKL_FUSE_STATUS,
+                                            SKL_FUSE_PG0_DIST_STATUS,
+                                            SKL_FUSE_PG0_DIST_STATUS,
+                                            1)) {
                        DRM_ERROR("PG0 not enabled\n");
                        return;
                }
@@ -761,12 +768,18 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
        if (check_fuse_status) {
                if (power_well->data == SKL_DISP_PW_1) {
-                        if (wait_for((I915_READ(SKL_FUSE_STATUS) &
+                        if (intel_wait_for_register(dev_priv,
-                                SKL_FUSE_PG1_DIST_STATUS), 1))
+                                                    SKL_FUSE_STATUS,
+                                                    SKL_FUSE_PG1_DIST_STATUS,
+                                                    SKL_FUSE_PG1_DIST_STATUS,
+                                                    1))
                                DRM_ERROR("PG1 distributing status timeout\n");
                } else if (power_well->data == SKL_DISP_PW_2) {
-                        if (wait_for((I915_READ(SKL_FUSE_STATUS) &
+                        if (intel_wait_for_register(dev_priv,
-                                SKL_FUSE_PG2_DIST_STATUS), 1))
+                                                    SKL_FUSE_STATUS,
+                                                    SKL_FUSE_PG2_DIST_STATUS,
+                                                    SKL_FUSE_PG2_DIST_STATUS,
+                                                    1))
                                DRM_ERROR("PG2 distributing status timeout\n");
                }
        }
@@ -917,7 +930,7 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
        gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
        WARN_ON(dev_priv->cdclk_freq !=
-                dev_priv->display.get_display_clock_speed(dev_priv->dev));
+                dev_priv->display.get_display_clock_speed(&dev_priv->drm));
        gen9_assert_dbuf_enabled(dev_priv);
@@ -1075,7 +1088,7 @@ static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
         *
         * CHV DPLL B/C have some issues if VGA mode is enabled.
         */
-        for_each_pipe(dev_priv->dev, pipe) {
+        for_each_pipe(&dev_priv->drm, pipe) {
                u32 val = I915_READ(DPLL(pipe));
                val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
@@ -1100,7 +1113,7 @@ static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
        intel_hpd_init(dev_priv);
-        i915_redisable_vga_power_on(dev_priv->dev);
+        i915_redisable_vga_power_on(&dev_priv->drm);
 }
 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
@@ -1110,9 +1123,9 @@ static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
        spin_unlock_irq(&dev_priv->irq_lock);
        /* make sure we're done processing display irqs */
-        synchronize_irq(dev_priv->dev->irq);
+        synchronize_irq(dev_priv->drm.irq);
-        vlv_power_sequencer_reset(dev_priv);
+        intel_power_sequencer_reset(dev_priv);
 }
 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
@@ -1205,7 +1218,6 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
        u32 phy_control = dev_priv->chv_phy_control;
        u32 phy_status = 0;
        u32 phy_status_mask = 0xffffffff;
-        u32 tmp;
        /*
         * The BIOS can leave the PHY is some weird state
@@ -1293,10 +1305,14 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
         * The PHY may be busy with some initial calibration and whatnot,
         * so the power state can take a while to actually change.
         */
-        if (wait_for((tmp = I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask) == phy_status, 10))
+        if (intel_wait_for_register(dev_priv,
-                WARN(phy_status != tmp,
+                                    DISPLAY_PHY_STATUS,
-                     "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
+                                    phy_status_mask,
-                     tmp, phy_status, dev_priv->chv_phy_control);
+                                    phy_status,
+                                    10))
+                DRM_ERROR("Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
+                          I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask,
+                           phy_status, dev_priv->chv_phy_control);
 }
 #undef BITS_SET
@@ -1324,7 +1340,11 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
        vlv_set_power_well(dev_priv, power_well, true);
        /* Poll for phypwrgood signal */
-        if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
+        if (intel_wait_for_register(dev_priv,
+                                    DISPLAY_PHY_STATUS,
+                                    PHY_POWERGOOD(phy),
+                                    PHY_POWERGOOD(phy),
+                                    1))
                DRM_ERROR("Display PHY %d is not power up\n", phy);
        mutex_lock(&dev_priv->sb_lock);
@@ -2255,7 +2275,7 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
 */
 void intel_power_domains_fini(struct drm_i915_private *dev_priv)
 {
-        struct device *device = &dev_priv->dev->pdev->dev;
+        struct device *device = &dev_priv->drm.pdev->dev;
        /*
         * The i915.ko module is still not prepared to be loaded when
@@ -2556,7 +2576,7 @@ static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
 */
 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
 {
-        struct drm_device *dev = dev_priv->dev;
+        struct drm_device *dev = &dev_priv->drm;
        struct i915_power_domains *power_domains = &dev_priv->power_domains;
        power_domains->initializing = true;
@@ -2618,7 +2638,7 @@ void intel_power_domains_suspend(struct drm_i915_private *dev_priv)
 */
 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
 {
-        struct drm_device *dev = dev_priv->dev;
+        struct drm_device *dev = &dev_priv->drm;
        struct device *device = &dev->pdev->dev;
        pm_runtime_get_sync(device);
@@ -2639,7 +2659,7 @@ void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
 */
 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv)
 {
-        struct drm_device *dev = dev_priv->dev;
+        struct drm_device *dev = &dev_priv->drm;
        struct device *device = &dev->pdev->dev;
        if (IS_ENABLED(CONFIG_PM)) {
@@ -2681,7 +2701,7 @@ bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv)
 */
 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
 {
-        struct drm_device *dev = dev_priv->dev;
+        struct drm_device *dev = &dev_priv->drm;
        struct device *device = &dev->pdev->dev;
        assert_rpm_wakelock_held(dev_priv);
@@ -2700,7 +2720,7 @@ void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
 */
 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
 {
-        struct drm_device *dev = dev_priv->dev;
+        struct drm_device *dev = &dev_priv->drm;
        struct device *device = &dev->pdev->dev;
        assert_rpm_wakelock_held(dev_priv);
@@ -2723,7 +2743,7 @@ void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
 */
 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
 {
-        struct drm_device *dev = dev_priv->dev;
+        struct drm_device *dev = &dev_priv->drm;
        struct device *device = &dev->pdev->dev;
        pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */